SPT7871 10-BIT, 100 MSPS TTL A/D CONVERTER FEATURES APPLICATIONS • • • • • • • • • • • • • • 10-Bit, 100 MSPS Analog-to-Digital Converter Monolithic Bipolar Single-Ended Bipolar Analog Input -1.0 V to +1.0 V Analog Input Range Internal Sample-and-Hold Internal Voltage Reference Programmable Data Output Formats Single Ended TTL Outputs Differential ECL Clock Input GENERAL DESCRIPTION Professional Video HDTV Communications Imaging Digital Oscilloscopes The resolution and performance of this device makes it well suited for professional video and HDTV applications. The onchip track-and-hold provides for excellent AC performance enabling this device to be a converter of choice for RF communications and digital sampling oscilloscopes. The SPT7871 is available in a 44L cerquad package in the industrial temperature range and in die form. The SPT7871 is a 10-bit, 100 MSPS analog-to-digital converter, with a two stage subranging flash/folder architecture. The bipolar, single-ended analog input provides an easy interface for most applications. Programmable data output formats provide additional ease of implementation and flexibility. The device supports high speed TTL outputs. BLOCK DIAGRAM VEE AVCC DVCC AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Analog Input AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Σ AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA * AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA * AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAA AAAAAAAAAAAAAAA * AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA T/H VIN 3-Bit Flash (MSB) T/H 3-Bit DAC 8-Bit Folder ADC (LSB) Error Correction Logic Output Latches and Buffers (TTL) Internal +1.0 V Reference VT VM VB D10 (Overrange) D9 (MSB) D8 D7 D6 D5 D4 D3 D2 D1 D0 Reference Ladder Internal -1.0 V Reference Timing and Control * Provided for reference decoupling purposes only. AGND DGND MINV (CMOS/TTL) LINV (CMOS/TTL) CLK (ECL) NCLK (ECL) ABSOLUTE MAXIMUM RATING (Beyond which damage may occur)1 Output Digital Outputs ......................................... +30 to -30 mA Supply Voltages AVCC ........................................................................ 0 to +6.5 V DVCC ........................................................................ 0 to +6.5 V VEE ............................................................................. 0 to -6.5 V Temperature Operating Temperature ............................. -40 to + 85 °C Junction Temperature ........................................ + 175 °C Lead, Soldering (10 seconds) ............................ + 300 °C Storage .................................................... -60 to + 150 °C Input Voltages Analog Input ............................................. VEE≤VIN≤VCC LINV/MINV Inputs .......................... -0.5 V to VCC +0.5 V CLK/NCLK Inputs ........................................... VEE to 0 V Note: 1. Operation at any Absolute Maximum Ratings is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. ELECTRICAL SPECIFICATIONS TA = +25 °C , DVCC =AVCC = +5.0 V, VEE = -5.2 V, VIN = ±1.0 V, fclock = 80 MHz, 50% clock duty cycle, unless otherwise specified. PARAMETERS DC Performance Resolution Differential Linearity Integral Linearity, Best Fit No Missing Codes Analog Input Input Voltage Range Input Bias Current Input Resistance Input Capacitance Input Bandwidth ±FS Offset Error Timing Characteristics Minimum Conversion Rate Maximum Conversion Rate Pipeline Delay (Latency) Transient Response Overvoltage Recovery Time Output Delay (td) Aperture Delay Time Aperture Jitter Time Dynamic Performance Effective Number of Bits fIN = 10 MHz fIN = 25 MHz fIN = 25 MHz fIN = 50 MHz fIN = 50 MHz Signal-To-Noise Ratio fIN = 10 MHz fIN = 25 MHz fIN = 25 MHz fIN = 50 MHz fIN = 50 MHz Total Harmonic Distortion1 fIN = 10 MHz fIN = 25 MHz fIN = 25 MHz fIN = 50 MHz fIN = 50 MHz TEST CONDITIONS TEST LEVEL fClock = 6.4 MHz fClock = 6.4 MHz Full Temperature fClock = 6.4 MHz I I V I Full Temperature V I I V V IV I Full Power V IV IV V V V V V fclock = 100 MHz fclock = 100 MHz fclock = 100 MHz fclock = 100 MHz fclock = 100 MHz fclock = 100 MHz MIN -1.0 -100 50 150 TYP 10 ±0.5 ±1.0 ±2.5 Guaranteed ±1.0 25 150 100 5 180 ±20 MAX UNITS ±1.25 ±2.0 100 ±100 2 8.1 8.1 I I V I V 52 52 I I V I V -56 -56 7.5 52 -48 V µA kΩ kΩ pF MHz mV 2 10 10 3 1 5 MSPS MSPS Clock ns ns ns ns ps (rms) 8.5 8.5 8.0 7.8 7.5 Bits Bits Bits Bits Bits 54 54 51 54 50 dB dB dB dB dB -62 -60 -56 -51 -50 dBc dBc dBc dBc dBc 100 I I V I V Bits LSB LSB LSB SPT7871 2 9/7/98 ELECTRICAL SPECIFICATIONS TA = +25 °C , DVCC =AVCC = +5.0 V, VEE = -5.2 V, VIN = ±1.0 V, fclock = 80 MHz, 50% clock duty cycle, unless otherwise specified. TEST TEST PARAMETERS CONDITIONS LEVEL MIN TYP MAX Dynamic Performance Signal-to-Noise + Distortion (SINAD) fIN =10 MHz I 51 53 fIN = 25 MHz I 51 53 fIN = 25 MHz fclock = 100 MHz V 50 fIN = 50 MHz I 47 49 fIN = 50 MHz fclock = 100 MHz V 47 Spurious Free Dynamic Range fIN = 10 MHz V 65 fIN = 25 MHz V 63 fIN = 50 MHz V 52 Two-Tone IMD Rejection2 V -65 Differential Phase V 0.5 Differential Gain V 1 Power Supply Requirements AVCC Supply Voltage IV 4.75 5.0 5.25 DVCC Supply Voltage IV 4.75 5.0 5.25 VEE Supply Voltage IV -4.95 -5.2 -5.45 VCC Supply Current Full Temperature VI 210 248 VEE Supply Current Full Temperature VI 128 151 Power Dissipation Full Temperature VI 1.7 2.0 Power Supply Rejection Ratio IV 30 Digital Inputs LINV, MINV V CMOS/TTL Clock Inputs Logic 1 Voltage (ECL) VI -1.1 Logic 0 Voltage (ECL) VI -1.5 Maximum Input Current Low VI -100 +100 Maximum Input Current High VI -100 +100 Pulse Width Low (CLK) IV 4.0 250 Pulse Width High (CLK) IV 4.0 250 Rise/Fall Time 20% to 80% IV 1.5 Digital Outputs Logic 1 Voltage (TTL) 2 mA VI 2.4 2.8 Logic 0 Voltage (TTL) 2 mA VI 0.5 0.8 tRise 10% to 90% V 2.0 tFall 10% to 90% V 2.0 12048 pt FFT using distortion harmonics 2 through 10. 2Measured as a second order (f1-f2) intermodulation product from a two-tone test with each input tone at 0 dBm. TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. UNITS dB dB dB dB dB dB FS dB FS dB FS dBc Degree % V V V mA mA W dB Logic V V µA µA ns ns ns V V ns ns TEST LEVEL I TEST PROCEDURE 100% production tested at the specified temperature. II 100% production tested at TA = +25 °C, and sample tested at the specified temperatures. III IV QA sample tested only at the specified temperatures. V Parameter is a typical value for information purposes only. 100% production tested at TA = +25 °C. Parameter is guaranteed over specified temperature range. Parameter is guaranteed (but not tested) by design and characterization data. VI Unless otherwise noted, all tests are pulsed tests; therefore, TJ = TC = TA. SPT7871 3 9/7/98 Figure 1 - Timing Diagram A AA AA AA CLK OUTPUT DATA N-3 A A A A A A AA AAA AA N+1 N tclk tpwh AA A AA tpwl A A A N+2 td N-2 DATA VALID N-1 DATA VALID N Table I - Data Output Timing Parameters Timing Parameter fclock Clock Pulse Width High (tpwh) Clock Pulse Width Low (tpwl) Switching Delay (td) Clock Latency Minimum 2 MHz 4.0 ns 4.0 ns Typical Maximum 100 MHz 250 ns 250 ns 3 ns 2 clock cycles resultant 10-bit data conversion is internally latched and presented on the data output pins via buffered output drivers. THEORY OF OPERATION The SPT7871 uses a two stage subranging architecture incorporating a 3-bit flash MSB conversion stage followed by an 8-bit interpolating folder conversion stage. Digital error correction logic combines the results of both stages to produce a 10-bit data conversion digital output. TYPICAL INTERFACE CIRCUIT The SPT7871 requires few external components to achieve the stated operation and performance. Figure 2 shows the typical interface requirements when using the SPT7871 in normal circuit operation. The following section is a description of the pin functions and outlines critical performance criteria to consider for achieving the optimal device performance. The analog signal is input directly to the 3-bit flash converter which performs a 3-bit conversion and in turn drives an internal DAC used to set the second stage voltage reference level. The 3-bit result from the flash conversion is input to the digital error correction logic and used in calculation of the upper most significant bits of the data output. POWER SUPPLIES AND GROUNDING The SPT7871 requires the use of three supply voltages: VEE, AVCC and DVCC. The VEE and AVCC supplies should be treated as analog supply sources. This means the VEE and VCC ground returns of the device should both be connected to the analog ground plane. Each power supply pin should be bypassed as closely as possible to the device with .01 µF and 2.2 µF capacitors as shown in figure 2. The analog input is also input directly to an internal track-andhold amplifier. The signal is held and amplified for use in the second stage conversion. The output of the track-and-hold is input into a summing junction that takes the difference between the track-and-hold amplifier and the 3-bit DAC output. The residual is captured by a second track-and-hold which holds and amplifies this residual voltage. The two grounds available on the SPT7871 are AGND and DGND. DGND is used only for TTL outputs and is to be referenced to the output pullup voltage. These grounds are not tied together internal to the device. The use of ground planes is recommended to achieve the best performance of the SPT7871. The AGND and the DGND ground planes should be separated from each other and only connected together at the device through an inductance or ferrite bead. Doing this will minimize the ground noise pickup. The residual held by the track-and-hold amplifier is input to an 8-bit interpolating folder stage for data conversion. The 8-bit converted data from the folder stage is input into the digital error correction logic and used in calculation of the lower significant bits. The error correction logic incorporates a proprietary scheme for compensation of any internal offset and gain errors that might exist to determine the 10-bit conversion result. The SPT7871 4 9/7/98 available and are controlled by the MINV and LINV pins. Table III shows the four possible output formats possible as a function of MINV and LINV. Table II shows the output coding data format versus analog input voltage relationship. ANALOG INPUT The SPT7871 has a single-ended analog input with a bipolar input range from -1 V to +1 V. The bipolar input allows for easier interface by external op amps when compared to unipolar input devices. Because the input common mode is 0 V, the external op amp can operate without a voltage offset on the output, thereby maximizing op amp head room and minimizing distortion. Table II - Output Coding Data Format VIN >+1.0 V (+FS) In addition, the 0 V common mode allows for a very simple DC coupled analog input connection if desired. The current drive requirements for the analog input are minimal when compared to conventional flash converters due to the SPT7871’s low input capacitance of only 5 pF and very high input impedance of 150 kΩ. D10 1 0 D9…D0 (Binary*) D9…D0 (2's Comp*) 11 1111 1111 01 1111 1111 11 1111 1111 01 1111 1111 +1.0 V -1 LSB 0.0 V 0 0 11 1111 1110 10 0000 0000 01 1111 1110 00 0000 0000 -1.0 V +1 LSB (-FS) 0 0 0 01 1111 1111 00 0000 0001 00 0000 0000 11 1111 1111 10 0000 0001 10 0000 0000 <-1.0 V 0 00 0000 0000 10 0000 0000 CLOCK INPUTS *Refer to table III for possible output formats. The clock inputs are designed to be driven differentially with ECL levels. For optimal noise performance, the clock input rise time should be a maximum of 1.5 ns. Because of this, the use of fast logic is recommended. The analog input signal is latched on the rising edge of the CLK. OVERRANGE BIT - D10 D10 is the overrange bit which is asserted whenever the analog input signal exceeds the positive full scale input by 1 LSB. When this condition occurs the D10 bit will be asserted to logic high and remain high continuously until the overrange condition is removed from the input. The clock may be driven single-ended since the NCLK pin is internally biased to -1.3 V. NCLK may be left open but a .01 µF bypass capacitor from NCLK to AGND is recommended. NOTE: System performance may be degraded due to increased clock noise or jitter. All other output signals will also stay at their maximum encoded output throughout this condition. D10 is not asserted for an underscale condition when the input exceeds the negative full scale. The performance of the SPT7871 is specified and tested with a 50% clock duty cycle. However, at sample rates greater than 80 MSPS, additional gains in the dynamic performance of the device may be obtained by adjusting the clock duty cycle. Typically, operation near 55% duty cycle will yield improved results. DIGITAL OUTPUT DATA TIMING The data is presented on the output pins two clock cycles after the input is sampled with an additional output delay of typically 3 ns. The data is held valid for one clock cycle. Refer to the timing diagram shown in figure 1. INTERNAL VOLTAGE REFERENCE DIGITAL OUTPUT CONTROL PINS - MINV, LINV The SPT7871 incorporates an on-chip voltage reference. The top and bottom reference voltages are each internally tied to their respective top and bottom of the internal reference ladder. The pins for the voltage references and the ladder (including the center of the ladder) are brought out to pins on the device for decoupling purposes only (pins VT, VM, and VB). A .01 µF capacitor should be used on each pin and tied to AGND. See the typical interface circuit (figure 2). Two digital output control pins control the digital output format. See table III. The MINV pin is a CMOS/TTL-compatible input. It inverts the most-significant bit (D9) when tied to +5 V. The most-significant bit (D9) is noninverted when MINV is tied to ground or floated. The MINV pin is internally pulled down to ground. The LINV pin is a CMOS/TTL-compatible input. It inverts the least-significant bits (D8 through D0) when tied to +5 V. The least-significant bits (D8 through D0) are noninverted when LINV is tied to ground or floated. The LINV pin is internally pulled down to ground. The internal voltage reference and the internal error correction logic eliminate the need for driving externally the voltage reference ladder. In fact, the voltage reference ladder should not be driven with an external voltage reference source as the internal error correction circuitry already compensates for the internal voltage and no improvement will result. Table III - Data Output Bits MINV 0V 0V +5 V +5 V DIGITAL OUTPUTS DIGITAL OUTPUT DATA FORMAT - D0 - D9 D0 is the least-significant bit for the digital data output, and D9 is the most-significant bit. Four data output formats are LINV 0V +5 V 0V +5 V Description of Data Binary (Noninverted) Two's Complement (Inverted) Two's Complement (Noninverted) Binary (Inverted) SPT7871 5 9/7/98 TYPICAL PERFORMANCE CHARACTERISTICS Dynamic Performance vs. Sample Rate Input Frequency = 25MHz 65 Dynamic Performance vs. Input Frequency Sample Rate = 80 MSPS 70 60 65 THD THD 60 55 dB dB SNR SNR 55 SINAD 50 50 SINAD 45 40 45 60 70 80 90 100 Sample Rate (MSPS) 40 110 Dynamic Performance vs. Input Frequency Sample Rate = 100 MSPS 60 0 65 20 40 60 80 Input Frequency (MHz) 100 Dynamic Performance vs. Temperature Sample Rate = 80 MSPS Input Frequency = 25 MHz THD THD 55 60 SNR dB dB 50 SINAD 45 SNR 55 40 35 SINAD 0 20 40 60 80 Input Frequency (MHz) 50 -25 100 0 Power Relative to ADC Full Scale (dB) Power Relative to ADC Full Scale (dB) Single Tone at 4.9 MHz Sample Rate = 80 MSPS -10 -20 -30 -40 -50 -60 -70 -80 -90 0 10 20 Frequency (MHz) 30 40 0 25 50 Temperature (°C) 75 100 Single Tone at 14.9 MHz Sample Rate = 80 MSPS 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 0 10 20 Frequency (MHz) 30 40 SPT7871 6 9/7/98 adequate thermal performance under laboratory tests. Air flow may be required for operation at elevated ambient temperature. Fairchild recommends that the junction temperature be maintained under +150 °C. TTL DIGITAL OUTPUT LEVELS The SPT7871 supports TTL and some CMOS logic levels. (Refer to minimum high voltage level for selected digital parts that will interface with the SPT7871.) It has single-ended outputs that are driven off a separate +5 V digital supply (DVCC). THERMAL MANAGEMENT The thermal impedance values for the cerquad package are θJC = 3.3 °C/W and θJA = 70 °C/W (junction to ambient in still air with no heat sink). Fairchild recommends that a heat sink be used for this device to ensure rated performance. A heat sink in still air provides Figure 3 - Clock Input Equivalent Circuit AVCC Figure 2 - Typical Interface Circuit AGND -A5.2 (ESD) +A5 (ESD) FB2 6 kΩ 26 kΩ FB3 NCLK * VEE AGND AVCC Analog Input CLK .01 * 26 kΩ DGND DVCC D10 52 kΩ D8 .01 VT D7 D6 .01 VM SPT7871 Interfacing Logics D5 .01 D4 VB VEE Figure 4 - Digital Outputs Equivalent Circuit D3 DVCC D2 ECL Differential Clock Input (ESD) (ESD) D9 VIN -1.3 V X CLK X CLK D1 D0 MINV LINV (ESD) FB1 +A5 +D5 Notes: +A5 1) X = Line termination 2) * = 0.01 µF chip cap. in parallel with 2.2 µF, tant cap. -A5.2 10µF 10 µF + + +D5 TTL OUT 10 µF + (ESD) 3) Immediate output buffer is highly recommended +5 V to optimize the performance due to reflection. AGND -5.2 V DGND +5V DGND PACKAGE OUTLINE 44L Cerquad INCHES 44 C 1 A D B SYMBOL MIN A 0.550 typ MIN MAX 13.97 typ B 0.685 0.709 17.40 18.00 C 0.037 0.041 0.94 1.04 D 0.016 typ E 0.008 typ F 0.027 G 0.006 typ H 0.080 0.41 typ 0.20 typ 0.051 0.69 1.30 0.15 typ 0.150 0 - 5° A MILLIMETERS MAX 2.03 3.81 H G E B F SPT7871 7 9/7/98 AGND AVCC AVCC 35 34 AGND 37 36 VEE VEE 39 38 LINV N/C 40 DVCC PIN FUNCTIONS 41 42 43 44 N/C DGND PIN ASSIGNMENTS DØ 1 33 D1 D2 2 32 VB N/C 3 31 N/C D3 4 30 VM D4 D5 5 29 N/C 28 VIN D6 7 27 N/C D7 8 26 N/C D8 D9 9 25 10 24 VT AVCC D1Ø 11 23 I/O I O O I I LINV I MINV I VT N/A VM N/A VB N/A 22 AVCC AGND 21 AGND VEE 20 19 VEE 18 17 NCLK N/C 16 MINV CLK 14 DVCC 13 12 N/C DGND 15 44L Cerquad 6 Name VIN D0-D9 D10 CLK NCLK AVCC DVCC VEE N/C AGND DGND I I I I I Function Analog Input Digital Output Data (D0 = LSB) (TTL) Overflow (TTL) Clock (Internal Pull-Down to Ground) Inverted Clock (ECL) (Internal Pull-Down to -1.3 V) Invert Least Significant Bits (D0-D8); CMOS/TTL Level; Invert=+5 V; Internal Pull-Down to Ground Invert MSB (D9); CMOS/TTL Level; Invert=+5 V; Internal Pull-Down to Ground Internal Top Reference Decoupling (+1 V typical) Internal Mid-Point Reference Decoupling (0 V typical) Internal Bottom Reference Decoupling (-1 V typical) +5 V Analog Supply +5 V Digital Supply -5.2 V Supply Not Connected Analog Ground Digital Ground ORDERING INFORMATION PART NUMBER TEMPERATURE RANGE SPT7871SIQ -40 to +85 °C SPT7871SCU +25 °C PACKAGE 44L Cerquad Die* *Please see the die specification for guaranteed electrical performance. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com © Copyright 2002 Fairchild Semiconductor Corporation SPT7871 8 9/7/98