60V, 1A/2A Peak, 1/2 Bridge Driver with 4V UVLO HIP2103, HIP2104 Features The HIP2103 and HIP2104 are half bridge drivers designed for applications using DC motors, three-phase brushless DC motors, or other similar loads. • 60V maximum bootstrap supply voltage • 3.3V and 12V LDOs with dedicated enable pins (HIP2104) • 5µA sleep mode quiescent current Two inputs (HI and LI) are provided to independently control the high side driver (HO) and the low side driver (LO). Furthermore, the two inputs can be configured to enable/disable the device, thus lowering the number of connections to a microcontroller and lowering costs. • 4V undervoltage lockout • 3.3V or 5V CMOS compatible inputs with hysteresis • Integrated bootstrap FET (replaces traditional boot strap diode) Applications The very low IDD bias current in the Sleep Mode prevents battery drain when the device is not in use, thus eliminating the need for an external switch to disconnect the driver from the battery. • Half bridge, full bridge and BLDC motor drives (see Figures 21, 22, 23) • UPS and inverters A fail-safe mechanism is included to improve system reliability and to minimize the possibility of catastrophic bridge failures due to controller malfunction. Internal logic prevents both outputs from turning on simultaneously when HI and LI are both high simultaneously. Dead-time is still required on the rising edge of the HI (or LI) input when the LI (or HI) input transitions low. • Class-D amplifiers • Any switch mode power circuit requiring a half bridge driver Related Literature • AN1896 “HIP2103, HIP2104 Evaluation Board User’s Guide” • AN1899 “HIP2103, HIP2104 3-phase, Full or Half Bridge Motor Drive” Integrated pull-down resistors on all of the inputs (LI, HI, VDen and VCen) reduces the need for external resistors. An active low resistance pull-down on the LO output ensures that the low side bridge FET remains off during the Sleep Mode or when VDD is below the undervoltage lockout (UVLO) threshold. The HIP2104 has a 12V linear regulator and a 3.3V linear regulator with separate enable pins. The 12V regulator provides internal bias for VDD and the 3.3V regulator provides bias for an external microcontroller (and/or other low voltage ICs), thus eliminating the need for discrete LDOs or DC/DC converters. The HIP2103 is available in a 3x3mm, 8 Ld TDFN package and the HIP2104 is available in a 4x4mm, 12 Ld DFN package. VBAT 5.5 VBAT VBAT 5.0 VDen VCen VCC 4.5 HB VDD HO HI HO HI HIP2104 HS LI DC MOTOR LO µController HS HIP2103 LO VSS LI VDD IBAT (µA) HB VDD 4.0 3.5 3.0 VSS 2.5 EPAD 2.0 EPAD 10 20 30 40 50 VBAT (VDC) FIGURE 1. TYPICAL FULL BRIDGE APPLICATION November 27, 2013 FN8276.0 1 FIGURE 2. HIP2104 SHUTDOWN CURRENT vs VBAT CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2013. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. HIP2103, HIP2104 Block Diagram VBAT VDD VCC 155C OT 3.3V LDO 12V LDO 1 MSEC DELAY VCen 1 MSEC DELAY VDen 100kΩ 100KΩ 2104 2103 VDD SEE FIGURES 3 AND 4 FOR SLEEP MODE TIMING DETAILS 1 HB 4V UNDER VOLTAGE 2104 2103 VBAT Boot FET 20 US DELAY R 20 US DELAY LOGIC BIAS Q S SLEEP MODE LEVEL SHIFT HI 100kΩ HO 4V UNDER VOLTAGE Logic prevents shoot-through when LI and HI are both high E P A D 2MΩ HS VDD LO LI Active pull-down 100Ω keeps bridge FET off during UV, OT, or sleep 100kΩ VSS Symbol Glossary 10 US DELAY Time delay functional block with rising edge prop delay (as indicated by the rising arrow on the input) and minimal falling edge delay. HIP2103 2 2104 2103 Optional connections as indicated by part numbers HIP2104 FN8276.0 November 27, 2013 HIP2103, HIP2104 Pin Configurations HIP2104 (12 LD 4x4 DFN) TOP VIEW HIP2103 (8 LD 3x3 TDFN) TOP VIEW VDD 1 HI 2 LI 3 EPAD (VSS) VSS 4 8 HB VDen 1 12 VBAT 7 HO VCen 2 11 HB 6 HS VCC 3 5 LO VDD 4 EPAD (VSS) 10 HO 9 HS HI 5 8 LO LI 6 7 VSS Pin Descriptions HIP2103 HIP2104 8 LD TDFN 12 LD DFN SYMBOL DESCRIPTION - 1 VDen (HIP2104 only) VDD enable input, 3.3V or 5V logic compatible, VBAT tolerant. VDD output is turned on after 1ms debouncing period. - 2 VCen (HIP2104 only) VCC enable input, 3.3V or 5V logic compatible. VBAT tolerant. VCC output is turned on after 1ms debouncing period. - 3 VCC (HIP2104 only) 3.3V output voltage of linear regulator, 75mA. Enabled by VCen. 1 4 VDD (HIP2103) Input voltage 14V max. (HIP2104) 0utput voltage of linear regulator, 12V nominal, 75mA. Enabled by VDen. 2 5 HI High side input, 3.3V or 5V logic compatible. (HI -> HO). 3 6 LI Low side Input, 3.3V or 5V logic compatible. (LI -> LO). 4 7 VSS Signal ground. 5 8 LO Low side driver Output. (LI ->LO). 6 9 HS High side FET Source connection (low side boot capacitor connection). 7 10 HO High side driver Output. (HI -> HO) 8 11 HB High side Boot capacitor. - 12 VBAT (HIP2104 only) Positive battery (bridge voltage) connection. EP EP EPAD Exposed Pad, must be connected to signal ground. 3 FN8276.0 November 27, 2013 HIP2103, HIP2104 Ordering Information PART NUMBER (Notes 1, 2, 3, 4) PART MARKING UVLO (V) VCC REGULATOR (V) VDD REGULATOR (V) PACKAGE (Pb-Free) PKG. DWG. # HIP2103FRTAAZ DZBF 4.0 N/A N/A 8 Ld 3x3 TDFN L8.3x3A HIP2104FRAANZ 2104AN 4.0 3.3 12 12 Ld 4x4 DFN L12.4x4A HIP2103_4DEMO1Z HIP2103, HIP2104 3-phase, Full, or Half Bridge Motor Drive Demonstration Board HIP2103_4MBEVAL1Z HIP2103, HIP2104 Evaluation Board NOTES: 1. Add “-T*”, suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for HIP2103, HIP2104. For more information on MSL, please see Technical Brief TB363 4. All part numbers are rated -40°C to +125°C for the recommended operating junction temperature range. 4 FN8276.0 November 27, 2013 HIP2103, HIP2104 Absolute Maximum Ratings Thermal Information (Note 5) Supply Voltage VDD (HIP2103 only) . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V Bridge Supply Voltage VBAT (HIP2104 Only) . . . . . . . . . . . . . . . -0.3V to 60V High side Bias Voltage (VHB - VHS) (Note 10). . . . . . . . . . . . . . . -0.3V to 16V Logic Inputs VCen, VDen (HIP2104 Only) . . . . . . . . . . - 0.3v to VBAT+ 0.3V Logic Inputs LI, HI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3v to VDD+ 0.3V Output Voltage LO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3V to VDD + 0.3V Output Voltage HO . . . . . . . . . . . . . . . . . . . . . . . . . . VHS - 0.3V to VHB+ 0.3V Voltage on HS (Note 9, 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10V to 60V Voltage on HB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VHS - 0.3V to 66V Average Current in Boot Diode (Note 6). . . . . . . . . . . . . . . . . . . . . . . 100mA Maximum Boot Cap Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10µF Average Output Current in HO and LO (Note 6) . . . . . . . . . . . . . . . . 200mA ESD Ratings Human Body Model Class 2 (Tested per JESD22-A114E) . . . . . . 2000V Charged Device Model Class IV . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000V Latch-Up (Tested per JESD-78B; Class 2, Level A) all pins. . . . . . . . 100mA Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 8 Ld DFN Package (Notes 7, 8). . . . . . . . . . 46 7 12 Ld TDFN Package (Notes 7, 8) . . . . . . . 44 7 Max Power Dissipation at +25°C in free air 8 Ld DFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3W 12 Ld TDFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2W Max Power Dissipation at +25°C on copper plane 8 Ld DFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3W 12 Ld TDFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3W Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Maximum Operating Junction Temperature Range. . . . . . -40°C to +150°C Nominal Over Temperature Shut-down . . . . . . . . . . . . . . . . . . . . . . .+155°C Over Temperature Shut-down Range . . . . . . . . . . . . . . . +145°C to +165°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions (Note 5) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C Supply Voltage, VBAT(HIP2104 only) (Note 11). . . . . . . . . . . . . 5.0V to 50V Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 14V High Side Bias Voltage (VHB - VHS) (Note 10) . . . . . . . . . . . . . . -0.3V to 14V Voltage on HS, Continuous, VHS (Note 9, 10) . . . . . . . . . . . . . . .-10V to 50V Voltage on HB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHS - 0.3V to 60V Logic Inputs VCen, VDen (HIP2104 only). . . . . . . . . . . . . . . . . . . .0V to VBAT Output Voltage (LO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to VDD Output Voltage (HO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHS to VHB Average Output Current in HO and LO (Note 6) . . . . . . . . . . . . 0 to 150mA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 5. All voltages are referenced to VSS unless otherwise specified. 6. The average output current, when driving a power MOSFET or similar capacitive load, is the average of the rectified output current. The peak output currents of this driver are self limiting by trans conductance or rDS(ON) and do not required any external components to minimize the peaks. If the output is driving a non-capacitive load, such as an LED, the maximum output current must be limited by external means to less than the specified recommended rectified average output current. 7. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 8. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. 9. The the maximum value of VHS must be limited so that VHB does not exceed 60V. 10. The -10V limit for VHS has no time duration restrictions as far as the HS pin is concerned however, be aware that if the duration of the negative voltage is significant with respect to the time constant to charge the boot capacitor (across HB and HS) the voltage on the boot capacitor can charge as high as VDD - (-VHS) = (VDD +VHS) potentially violating the Voltage Rating for (VHB - VHS). 11. When VBAT < ~13V, the output of VDD will sag. The 5V minimum specified for VBAT is the minimum level for which the UVLO will not activate. DC Electrical Specifications VDD = VHB = 12V (for HIP2103), VSS = VHS = 0V, VBAT = 18V (for HIP2104), LI = HI = 0V. No load on HO and LO unless otherwise specified. Boldface limits apply over the operating junction temperature range, -40°C to +125°C. TJ = +25°C PARAMETERS SYMBOL TEST CONDITIONS TJ = -40°C to +125°C MIN TYP MAX MIN (Note 12) MAX (Note 12) UNITS -2.5 +2.1 +4.8 - 5% + 5% % LINEAR BIAS SUPPLIES (HIP2104 only) VDD Output Voltage Over Rated Line, Load, and Temperature VDD12 VDD Rated Output Current IDDR VDD Output Current Limit (brick wall) IDD12 5 Nominal VDD = 12V 75 83 151 237 mA 80 245 mA FN8276.0 November 27, 2013 HIP2103, HIP2104 DC Electrical Specifications VDD = VHB = 12V (for HIP2103), VSS = VHS = 0V, VBAT = 18V (for HIP2104), LI = HI = 0V. No load on HO and LO unless otherwise specified. Boldface limits apply over the operating junction temperature range, -40°C to +125°C. (Continued) TJ = +25°C PARAMETERS SYMBOL TEST CONDITIONS VDD Drop Output Voltage (Figure 7) VDdout Load = 75mA VCC Output Voltage Over Rated Line, Load, and Temperature VCC3.3 Nominal VCC = 3.3V VCC Rated Output Current ICDR VCC Output Current Limit (brick wall) ICC VCC Drop Output Voltage (Figure 8) VCdout MIN -3.9 TYP +1.8 TJ = -40°C to +125°C MAX MIN (Note 12) MAX (Note 12) UNITS 0.06 0.7 V - 5% + 5% % +4.3 75 83 149 Load = 75mA 237 mA 80 245 mA 0.5 0.9 V BIAS CURRENTS VDD Sleep Mode Current (HIP2103) IDDS HI = LI = 1, after 10 to 30µs delay 9.4 20 µA VBAT Shutdown Current (HIP2104) IDDSbatt VCen = VDen = 0, after 10 to 30µs delay, VBAT = 50V 4.8 15 µA VBAT (HIP2104) or VDD (HIP2103) Operating Current IDDO20 f = 20kHz, HI = LI = 50% square wave VDD = 12V for HIP2103 832 1040 µA IDDO10 f = 10kHz, HI = LI = 50% square wave VDD = 12V for HIP2103 661 825 µA HB to HS Quiescent Current IHBQ HI = 1, LO = 0, VHS = 0V, VHB = 12V 135 160 µA HB to HS Operating Current IHBS20K LI = 0, HI = 50% square wave 20kHz, VHS = 0V, VHB = 12V 206 245 µA IHBS10K LI = 0, HI = 50% square wave 10kHz, VHS = 0V, VHB = 12V 167 193 µA IHB20K LI = 0, HI = 50% square wave 20kHz, VHB = 60V, VHS = 50V 201 240 µA IHB10K LI = 0, HI = 50% square wave 10kHz, VHB = 60V, VHS = 50V 164 190 µA HB to VSS Operating Current HB to VSS Quiescent Current IHBQ LI = HI = 0V; VHB = 60V, VHS = 50V 120 145 µA HS to VSS Current, Sleep Mode IHBS LI = HI = 1; HB open, VHS = 50V 0.03 +1 µA INPUT PINS Low Level Input Voltage Threshold VIL High Level Input Voltage Threshold VIH Input Voltage Hysteresis VHys Low Level Input Voltage Threshold VIL High Level Input Voltage Threshold VIH Input Voltage Hysteresis Input Pull-Down 6 1.44 1.18 1.63 V 2.06 1.73 2.4 V 0.62 0.48 0.85 V 1.13 0.9 1.25 V 1.63 1.38 1.84 V VHys 0.50 0.36 0.63 V RI 100 80 130 kΩ VDD = 12V VDD = 5V FN8276.0 November 27, 2013 HIP2103, HIP2104 DC Electrical Specifications VDD = VHB = 12V (for HIP2103), VSS = VHS = 0V, VBAT = 18V (for HIP2104), LI = HI = 0V. No load on HO and LO unless otherwise specified. Boldface limits apply over the operating junction temperature range, -40°C to +125°C. (Continued) TJ = +25°C PARAMETERS TJ = -40°C to +125°C MIN (Note 12) MAX (Note 12) UNITS 4.2 3.98 4.36 V 0.34 0.267 0.37 V IVDD-HB = 75mA, HI = 0, LI = 1 8.2 2.42 15 Ω SYMBOL TEST CONDITIONS MIN TYP MAX UNDERVOLTAGE LOCKOUT (Note 13) VDD Falling Threshold VUVF4 VDD Threshold Hysteresis VUVH 4V option BOOT FET On Resistance RDon LO GATE DRIVER Sinking rDS(ON) RDSLOL ILO = 100mA, LI = 0 2.68 0.61 11 Ω Sourcing rDS(ON) RDSLOH ILO = -75mA, HI = 1 6.47 2.3 15 Ω ILOH12 HI = 1 VDD = 12V, Cload = 1000pF ILOH5 HI = 1 VDD = 5V, Cload = 1000pF (HIP2103 only) ILOL12 HI = 0 VDD = 12V, Cload = 1000pF ILOL5 HI = 0 VDD = 5V, Cload = 1000pF (HIP2103 only) Peak Pull-Up Current Peak Pull-Down Current 1 A A 2 A A HO GATE DRIVER Sinking rDS(ON) RDSHOL IHO = 100mA, HI = 0 6.1 4.4 11 Ω Sourcing rDS(ON) RDSHOH IHO = -100mA, HI = 1 11.9 9.7 15 Ω IHOH12 HI = 1 VDD = 12V, Cload = 1000pF 1 A IHOH5 HI = 1 VDD = 5V, Cload = 1000pF (HIP2103 only) 1 A IHOL12 HI = 0 VDD = 12V, Cload = 1000pF 2 A IHOL5 HI = 0 VDD = 5V, Cload = 1000pF (HIP2103 only) Peak Pull-Up Current Peak Pull-Down Current A NOTES: 12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 13. The UV lockout does not disable the VDD and VCC outputs. 7 FN8276.0 November 27, 2013 HIP2103, HIP2104 AC Electrical Specifications VDD = 12V, GND = 0V, No Load on OUTA or OUTB, Unless Otherwise Specified. VDD load = 1µF and VCC load = 1µF (HIP2104 only) Boldface limits apply over the operating junction temperature range, -40°C to +125°C. TJ = +25°C PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX TJ = -40°C to +125°C MIN MAX UNITS VDen and VCen Turn-On Delay (Figure 5) (HIP2104 only) tDen tCen VDen = VCen = 1, VCC = VDD = 10%, VBAT = 50V 1.69 1.0 2.5 ms VDen and VCen Turn-on Delay (Figure 5) (HIP2104 only) tDen tCen VDen = VCen = 1, VCC = VDD = 10%, VBAT = 18V 1.68 1.1 2.54 ms VDen and VCen Turn-on Delay Matching (Figure 5) (VDen - VCen) (HIP2104 only) tVenM VDen = VCen = 1, VCC = 10%, VDD = 10% VBAT = 50V 40 -290 340 ns VDen and VCen Turn-on Delay Matching (Figure 5) (VDen - VCen) (HIP2104 only) tVenM VDen = VCen = 1, VCC = 10%, VDD = 10% VBAT = 18V 40 -290 350 ns LO Turn-Off Propagation Delay (LI to LO falling) (Figure 6) tFL12 HI = 0, LI = 1 to 0 VDD = 12V 27 13 39 ns tFL5 HI = 0, LI = 1 to 0 VDD = 5V (HIP2103 only) 30 23 46 ns tFH12 LI = 0, HI = 1 to 0 VDD = 12V 23 10 35 ns tFH5 LI = 0, HI = 1 to 0 Vv = 5V (HIP2103 only) 27 19 38 ns tRL12 HI = 0, LI = 0 to 1 VDD = 12V 21 7 32 ns tRL5 HI = 0, LI = 0 to 1 VDD = 5V (HIP2103 only) 25 12 37 ns tRH12 LI = 0, HI = 0 to 1 VDD = 12V 23 9 35 ns tRH5 LI = 0, HI = 0 to 1 VDD = 5V (HIP2103 only) 28 15 40 ns HO Turn-Off Propagation Delay (HI to HO falling) (Figure 6) LO Turn-On Propagation Delay (LI to LO rising) (Figure 6) HO Turn-On Propagation Delay (HI to HO rising) (Figure 6) Turn-On/Off Propagation Mismatch (HO rising to LO falling) (Figure 6) tMONHL LI = 1 -> 0 HI = 0 -> 1 -2.5 -8 +3 ns Turn-On/Off Propagation Mismatch (LO rising to HO falling) (Figure 6) tMONLH HI = 1 -> 0 LI = 0 -> 1 -4.2 -9.0 +5.4 ns tR12 CL = 1nF VDD = 12V 20.5 7 35 ns tR5 CL = 1nF VDD = 5V (HIP2103 only) 19.5 6 32 ns tR12 CL = 1nF VDD = 12V 21 8 35 ns tR5 CL = 1nF VDD = 5V (HIP2103 only) 21 8 34 ns tF12 CL = 1nF VDD = 12V 17 3 30 ns tF5 CL = 1nF VDD = 5V (HIP2103 only) 17 3 30 ns tF12 CL = 1nF VDD = 12V 16 2 30 ns tF5 CL = 1nF VDD = 5V (HIP2103 only) 16 1.5 29 ns LO Output Rise Time (10% to 90% ) HO Output Rise Time (10% to 90%) LO Output Fall Time (90% to 10%) HO Output Fall Time (90% to 10%) 8 FN8276.0 November 27, 2013 HIP2103, HIP2104 AC Electrical Specifications VDD = 12V, GND = 0V, No Load on OUTA or OUTB, Unless Otherwise Specified. VDD load = 1µF and VCC load = 1µF (HIP2104 only) Boldface limits apply over the operating junction temperature range, -40°C to +125°C. (Continued) TJ = +25°C PARAMETERS SYMBOL TEST CONDITIONS MIN TYP TJ = -40°C to +125°C MAX MIN MAX UNITS Time Delay to Set Sleep Mode (Note 14, Figure 4) tSlpS HI = LI = 0 -> 1 17 9 27 µs Time Delay to Reset Sleep Mode (Note 14, Figure 4) tSlpR HI = 0, LI = 0 -> 1 17 9 27 µs NOTE: 14. When HI and LI are on simultaneously, HO and LO are never on simultaneously. This feature is intended to initiate sleep. This feature cannot be used to prevent shoot-through for normal alternating switching between LI and HI. Dead time must be provided when HI = 0 -> LI = 1, or LI = 0 -> HI = 1. See Timing Diagrams (Figure 4). Timing Diagrams (Vden and VCen apply to HIP2104 only) 2MΩ to HS HO = Logic inputs 2MΩ to HS HO LO 100Ω to LS LO = Logic inputs 100Ω to LS LO *SLEEP tSlpS tSlpR ~ ~ ~ ~ UVLO ~ ~ HO VDD UVLO VDD ~ ~ UV threshold *SLEEP VDen tVDen ~ ~ VDen VCC ~ ~ VCC VCen VCen tVCen *Sleep is an internal state. Minimal IDD or IBAT current results when active (high). FIGURE 3. VDD POWER-ON/OFF TIMING FOR SLEEP MODE 9 FN8276.0 November 27, 2013 HIP2103, HIP2104 Timing Diagrams (Continued) 2MΩ to HS HO 100Ω to LS LO ~ ~ LO HO dead time provided by controller SLEEP* ~ ~~ ~ SLEEP* HI ~ ~ HI LI LI 20µs 20µs * Sleep mode is enabled when HI=LI=1 for 20usecs. Sleep mode is cleared when HI=0 and LI = 1 for 20usecs. FIGURE 4. SLEEP MODE ENABLED OR CLEARED BY HI AND LI INPUTS 10% VDD VDD VDD 10% VCC VCC VCC tVDen VDen VDen VCen VCen tVCen tVenM FIGURE 5. VCEN AND VDEN DELAY MATCHING tFH tRH tMONHL tMONLH HO HO HI HI LO LO LI LI tRL tFL FIGURE 6. PROPAGATION DELAYS 10 FN8276.0 November 27, 2013 HIP2103, HIP2104 Typical Performance Curves 4 14 12 NO LOAD 3 160Ω (75mA @ 12V) VCC (OUTPUT) VDD (output) 10 8 6 NO LOAD 44Ω (75mA @ 3.3V) 2 1 4 2 0 0 20 18 16 14 12 10 8 6 4 2 6 2 1 FIGURE 8. VCC DROPOUT vs VBAT (HIP2104 ONLY) 5.5 275 5.0 270 265 IBAT (µA) 4.5 IBAT (µA) 3 VBAT (INPUT) FIGURE 7. VDD DROPOUT vs VBAT (HIP2104 ONLY) 4.0 3.5 3.0 260 255 250 245 2.5 2.0 4 5 0 240 10 20 30 235 50 40 10 20 30 VBAT (VDC) 50 40 VBAT (VDC) FIGURE 9. HIP2104 SHUTDOWN CURRENT (VCEN = VDEN = 0, HS = VBAT) FIGURE 10. HIP2104 QUIESCENT IBAT (VCEN = VDEN = LI = HI = 1) 900 4 IBAT, 20k 800 700 3 IBAT, 10kHz VCC (VDC) IBAT (µA) 600 500 400 2 300 1 0kHz, +25°C 200 100 0 0 10 20 30 40 50 VBAT (VDC) FIGURE 11. HIP2104 VDD OPERATING CURRENT LIMIT 11 60 0 0 25 50 75 100 125 150 ICC (mA) FIGURE 12. HIP2104 VCC CURRENT LIMIT FN8276.0 November 27, 2013 HIP2103, HIP2104 Typical Performance Curves (Continued) 10 14 9 12 8 7 IBAT (µA) VDD (VDC) 10 8 6 6 5 4 4 3 2 0 2 0 50 100 1 150 5 6 7 8 FIGURE 13. HIP2104 VDD CURRENT LIMIT, 0kHz IBAT, 20kHz UVLO (HO AND LO) (V) 600 IDD (µA) 12 13 14 4.3 700 IBAT, 10kHz 500 400 300 200 5 7 9 3.9 3.5 -40 15 13 11 4.1 3.7 IBAT, 0kHz 100 -20 0 VDD (VDC) 20 40 60 80 100 120 140 TEMPERATURE (°C) FIGURE 15. HIP2103 OPERATING CURRENT FIGURE 16. HIP2103, HIP2104 UNDERVOLTAGE LOCKOUT 20 9 18 8 16 7 SOURCING 14 6 Ohms 12 Ohms 11 4.5 800 10 8 5 4 SINKING 3 6 2 4 1 2 0 10 FIGURE 14. HIP2103 SLEEP CURRENT (HI = LI = 1) 900 0 9 VBAT (VDC) IDD (mA) -40 -20 0 20 40 60 80 TEMPERATURE (°C) FIGURE 17. BOOT FET RESISTANCE 12 100 120 140 0 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) FIGURE 18. HO OUTPUT RESISTANCE FN8276.0 November 27, 2013 HIP2103, HIP2104 Typical Performance Curves (Continued) 9 8 SOURCING 7 Ohms 6 5 4 3 SINKING 2 1 0 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) FIGURE 19. LO OUTPUT RESISTANCE Functional Description The following functional description references the “Block Diagram” on page 2. Overview The HIP2103 has independent control inputs, LI and HI, for each output, LO and HO. There is no logic inversion for these input/output pairs. To minimize the possibility of shoot-through failures of the bridge FETs caused by improper LI and HI signals from an external controller, internal logic in the driver prevents both outputs being high simultaneously. When either input is high, the high input must go low before a high on the other input propagates to its respective drive output. If both inputs are high simultaneously, both output are low. If one input is high, followed by the other input going high, the internal logic prevents any shoot through. Note that the internal logic does not prevent shoot-through if the dead-time provided by the external controller is not sufficiently long as required by the turn-on/off times of the bridge FETS. If both inputs are high simultaneously for longer than 30µs, the driver initiates a Sleep Mode to reduce the bias current to minimize the battery drain. When in Sleep Mode, the HO output is in a high-impedance state (2MΩ between HO and HS) and the LO output is held low with an active 100Ω pull-down resistor. The 100Ω pull-down prevents inadvertent shoot-through resulting from transients on the bridge voltage while both drivers are in the Sleep Mode. The undervoltage lockout (UVLO) on VDD drives HO and LO low when VDD is less that the UV threshold. Sleep Mode is initiated if UVLO is asserted for longer than 30µs. The high-side driver bias is established by the boot capacitor connected between HB and HS. The charge on the boot capacitor is provided by the internal boot FET that is connected between VDD and HB. The current path to charge the boot cap is enabled (boot FET is on) when the drain voltage on the low-side bridge FET (VHO) is <1V and when HO = 0. When the boot FET is on, the boot cap is charged to approximately VDD. 13 The boot FET turns off when H0 = 1. The boot capacitor provides the charge necessary to turn on the FET and maintains the bias voltage on the high side driver for the duration of the period while the FET is on. See the following for details on selecting the boot capacitor value. The peak charge current is limited in amplitude by the inherent resistance of the boot FET and by the delta voltage between VDD and the drain-source voltage of the low-side bridge FET (VHS) less the boot cap voltage. Assuming that the on time of the low-side FET is sufficiently long to fully charge the boot capacitor, the boot voltage charges very close to VDD (less the voltage across the drain-source of the low-side bridge FET). When the HI input transitions high, the high-side bridge FET is driven on. Because the HS node is connected to the source of the high-side FET, the HS node rises almost to the level of the bridge voltage, VBAT (less the conduction voltage across the bridge FET). Because the boot capacitor voltage is referenced to the source voltage of the high-side FET, the HB node is VDD volts above the HS node. Simultaneously with HI = 1, the boot FET is turned off preventing the boot capacitor from discharging back to VDD. Because the high-side driver circuit is referenced to the HS node, the HO output is now approximately VHB + VBAT above ground. During the low to high transition of the phase node (HS), the boot capacitor sources the necessary gate charge to fully enhance the high-side bridge FET gate. After the gate of the bridge FET is fully charged, the boot capacitor no longer sources charge to the gate but continues to provide bias current to the high-side driver through out the period while the high-side bride FET is on. To prevent the voltage on the boot capacitor from drooping excessively, the boot capacitor value must be sized appropriately. If the boot voltage droops to the UVLO threshold, the high-side FET is turned off to prevent damage due to insufficient gate voltage. FN8276.0 November 27, 2013 HIP2103, HIP2104 The boot capacitor value is chosen not only to supply the internal bias current of the high-side driver but also, and more significantly, to provide the gate charge of the driven FET without causing the boot voltage to sag excessively. In practice, the boot capacitor should have a total charge that is about 20 times the gate charge of the driven power FET for approximately a 5% drop in voltage after charge has been transferred from the boot capacitor to the gate capacitance. The following parameters are required to calculate the value of the boot capacitor for a specific amount of voltage droop when using the HIP2103, HIP2104. In the following example, some values used are specific to the HIP2103, HIP2104 and others are arbitrary. The values should be changed to comply with the actual application. VDD = 12V VHB = VDD = VHO Period = 100µs This is the nominal value of VDD for the HIP2104 High side driver bias voltage referenced to VHS This is the longest expected switching period IHB = IHBS20K + IHB20K = 295µA High side driver bias current at 20kHz RGS = 10kΩ Gate-source resistor Ripple = 5% Desired ripple voltage on the boot cap Igate_leak = 100nA Gate leakage current (from vendor datasheet) Qg40_12V = 45nC From Figure 20 The following equations calculates the total charge required for the Period: Qc = Qg40_12V + Period x (IHB + VHO/RGS + Igate_leak) Cboot = Qc/(Ripple * VDD) Cboot = 0.324µF If the gate to source resistor is removed (RGS is usually not needed or recommended), then: Cboot = 0.124µF 16 14 Vds = 80V Vgs, GATE VOLTAGE Selecting the Boot Capacitor Value 12 10 Vds = 40V 8 6 4 2 0 0 5 10 15 20 25 30 35 45 50 60 Qg, GATE CHARGE (nC) FIGURE 20. TYPICAL MOSFET GATE CHARGE vs GATE VOLTAGE Typical Applications Vbatt VBAT VDen VCen Vbatt VCC HB VDD HIP2104 HI uController HO DC MOTOR HS 50Vmax E P A D LO LI VSS FIGURE 21. HALF BRIDGE MOTOR DRIVE TOPOLOGY 14 FN8276.0 November 27, 2013 HIP2103, HIP2104 Typical Applications Vbatt Vbatt VBAT VDen VCen VCC HB VDD HB VDD VDD VDD HIP2104 HO HO HI HS LI uController DC MOTOR LO VSS HS HIP2103 HI LI LO VSS EPAD EPAD FIGURE 22. FULL BRIDGE MOTOR DRIVER TOPOLOGY 15 FN8276.0 November 27, 2013 HIP2103, HIP2104 Typical Applications VBATT VBATT HB VDD VDD VBAT VDen HO VCen HIP2103 HS VCC LI HB VDD HIP2104 BLDC Motor HO LO VSS HI EPAD HS LI uController HI LO HB VSS VDD HO HIP2103 EPAD HS HI LI LO VSS EPAD FIGURE 23. BLDC (3-PHASE) MOTOR DRIVE TOPOLOGY Application Examples Above are examples (Figures 21, 22, and 23) of how the HIP2103, HIP2104 can be configured for various motor drive application with the HIP2104 supplying the 12V bias for the other HIP2103s and the VCC (3.3V) bias for the controller. VCen and VDen are used to turn on and off the internal linear regulators of the HIP2104. Because of entire switching of the bias supplies is implemented with logic, a signal switch, instead of a power switch, can be used to turn on and off the driver and controller. A switch debouncing delay of 1ms is provided on VDen and VCen. The external diode on VBATT is used to hold up the voltage on the VBAT input in the presence of severe ripple as usually seen on LI-ON batteries. In the case of the HIP2104, when VDen is low, the driver sections enters the Sleep Mode. When VCen is low, the bias to the controller is removed resulting with the lowest possible idle current in both the controller and the driver minimizing the drain on the battery when the motor drive is off. Sleep mode can also 16 be initiated on the HIP2104 by driving HI and LI high simultaneously. In this case, the sleep mode current is substantially higher (~250µA) because the VDD and VCC outputs are still active. In the case of the HIP2103, Sleep Mode in the driver is initiated when HI and LI are both high simultaneously as previously described. If VDD is provided by an accompanying HIP2104, turning off the VDD output of the HIP2104 will also result with virtually no sleep current in the HIP2103 because there is no bias. For example, in the BLDC configuration, the sleep mode current will be ~5µA (in the HIP2104) and no current in both of the HIP2103s. Transients on the HS node An important operating condition that is frequently overlooked is the transient on the HS pin that occurs when the bridge FETs turn on or off. The Absolute Maximum negative transient (see page 5) allowed on the HS pin is -10V without any time restrictions on the duration of the transient. In most well designed PCBs, all that will be required is that the transient be less negative than -10V. FN8276.0 November 27, 2013 HIP2103, HIP2104 The negative transient on the HS pin is the result of the parasitic inductance of the low-side drain-source conductor path on the PCB. Even the parasitic inductance of the low-side FET body contributes to this transient. When the high-side bridge FET turns off (see Figure 24), as a consequence of the inductive characteristics of a motor load, the current that was flowing in the high-side FET (blue) must rapidly commutate through the low side FET (red). The amplitude of the negative transient impressed on the HS node is (L x di/dt) where L is the total parasitic inductance of the low-side FET drain-source path and di/dt is the rate at which the high-side FET is turned off. With the increasing current levels of new generation motor drives, appropriately clamping of this transient becomes more significant for the proper operation of bridge drivers. Fortunately, the HIP2103, HIP2104 can withstand greater amplitudes of negative transients than what is available in many other bridge drivers. The maximum negative voltage on the HS pin is rated for -10V with no time during limit. Another component of negative voltage is from the body diode of the low side FET during the dead time. When current is flowing from source to drain, the conduction voltage is approximately 1 to 1.5V negative impressed on the HS pin (possibly greater during fault load conditions). Because the HIP2103, HIP2104 is rated for -10V without any time constraints, this negative voltage component is of no consequence. HB HO Inductive Load CBOOT HS LO 1V + VSS FIGURE 25. TWO CLAMPING DIODES TO SUPPRESS NEGATIVE TRANSIENTS An alternative to the two series connected diodes is one diode and a resistor (Figure 26). In this case, it is necessary to limit the current in the diode with a small value resistor, RHS, connected between the phase node of the 1/2 bridge and the HS pin. Observe that RHS is effectively in series with the HO output and serves as a peak current limiting gate resistor on HO. HB HO Inductive Load CBOOT HB RHS HS HO Inductive Load CBOOT + LO HS + LO + VSS FIGURE 24. PARASITIC INDUCTANCE ON HS NODE In the unlikely event that the negative transient exceeds -10V, there are several ways of reducing the negative amplitude of this transient if necessary. If the bridge FETs are turned off more slowly to reduce di/dt, the amplitude will be reduced but at the expense of more switching losses in the FETs. Careful PCB design will also reduce the value of the parasitic inductance. However, in extreme cases, these two solutions by themselves may not be sufficient. Figure 25 illustrates a simple method for clamping the negative transient. Two series connected, fast 1 amp PN junction diodes are connected between HS and VSS as shown. It is important that these diodes be placed as close as possible to the HS and VSS pins to minimize the parasitic inductance of this current path between the two pins. Two diodes in series are required because they are in parallel with the body diode of the low side FET. If only one diode is used for the clamp, it will conduct some of the negative load current that is flowing in the body diode of the low side FET. 17 VSS + FIGURE 26. RESISTOR AND DIODE NEGATIVE TRANSIENT CLAMP The value of RHS is determined by how much average current in the clamping diode is acceptable. Current in the low side FET flows through the body diode during the dead time resulting with a negative voltage on HS that is typically about -1.5V. When the low-side FET is turned on, the current through the body diode is shunted away into the channel and the conduction voltage from source to drain is typically much less than the conduction voltage through the body diode. Consequently, significant current will flow in the clamping diode only during the dead time. Because the dead time is much less than the on time of the low side FET, the resulting average current in the clamping diode is very low. The value of RHS is then chosen to limit the peak current in the clamping diode and usually just a few ohms is necessary. The methods to clamp the negative transients with diodes can still result with high frequency oscillations on the HS node depending on the parasitics of the PCB design. An alternative to the clamping diode in Figure 26 is a small value capacitor instead of the diode. This capacitor and RHS is very effective for minimizing the negative spike amplitude and oscillations. FN8276.0 November 27, 2013 HIP2103, HIP2104 impedance, the boot capacitor can charge to a voltage greater than VDD (for example VDD + 1.5V). It may be necessary to either clamp the voltage as described in Figures 25 through 27 and/or keep the dead time as short as possible. HB CBOOT HO Inductive Load HS + RHS _ IBAT, 0kHz LO General PCB Layout Guidelines The AC performance of the HIP2103, HIP2104 depends significantly on the design of the PC board. The following layout design guidelines are recommended to achieve optimum performance: • Place the driver as close as possible to the driven power FET. Cfilter VSS FIGURE 27. RESISTOR AND CAPACITOR NEGATIVE TRANSIENT FILTER But this solution also has its limitations. Depending on the value of the filter capacitor and the PWM switching frequency, RHS may dissipate significant power because the voltage on the capacitor is switching between the bridge voltage and ground. Usually, the power dissipated by RHS is small because the switching frequency for most motor drives is <20kHz and the value used for Cfilter is typically about 1000pF. Another issue is that the charge on Cfilter will be partially transferred to the gate of the high-side FET when the low-side FET turns on. When the phase node goes low, a voltage is impressed across RHS as shown in Figure 27. Because HO is low, the voltage across RHS is also across the gate of the high side FET. If the filter cap is very large, the voltage on the gate will approach the bridge voltage turning on the high-side FET resulting with shoot-through. Fortunately, the voltage across RHS is much less than the bridge voltage for two reasons. First, the voltage across RHS is determined by the turn-on time of the low side FET. As the low-side FET is turning on, the charge on the filter cap is depleting lessening the voltage across RHS. Also, because the relatively large gate capacitance of the high-side FET is in parallel with RHS, the voltage impressed on the gate is further reduced. In a practical application using value of Cfilter = 4700pF and RHS = 1Ω, the voltage impressed on the bridge FET is less than 1V. The emphasis of suppressing transients on the HS pin has been with negative transients. Please note that a similar transients with a positive polarity occurs when the low-side FET turns off. This is usually not a problem unless the bridge voltage is close to the maximum rated operating voltage of 50V. Note that the maximum voltage ratings for the HS and HB nodes also must be observed when the positive transient occurs. The maximum rating for (VHB - VHS) must also not be overlooked. When a negative transient, Vneg, is present on the HS pin, the voltage differential across HB and HS will approach VDD + Vneg. If the transient duration is short compared to the charging time constant of the boot diode and boot capacitor, the voltage across HB and HS is not significantly affected. However, another source of negative voltage on the HS pin will more likely increase the boot capacitor voltage. While current is flowing from the source to drain of the low-side FET during the dead time, the current flows through body diode of the FET. Depending on the size of the FET and the amplitude of the reverse current, the voltage across the diode can be as high as -1.5V and much higher during a load fault. Because this negative voltage has little 18 • Understand where the switching power currents flow. The high amplitude di/dt currents of the driven power FET will induce significant voltage transients on the associated traces. • Keep power loops as short as possible by paralleling the source and return traces. • Use planes where practical; they are usually more effective than parallel traces. • Avoid paralleling high amplitude di/dt traces with low level signal lines. High di/dt will induce currents and consequently, noise voltages in the low level signal lines. • When practical, minimize impedances in low level signal circuits. Noise, magnetically induced on a 10kΩ resistor, is 10x larger than the noise on a 1kΩ resistor. • Be aware of magnetic fields emanating from motors and inductors. Gaps in the magnetic cores of these structures are especially bad for emitting flux. • If you must have traces close to magnetic devices, align the traces so that they are parallel to the flux lines to minimize coupling. • The use of low inductance components such as chip resistors and chip capacitors is highly recommended. • Use decoupling capacitors to reduce the influence of parasitic inductance in the VBAT, VDD and GND leads. To be effective, these caps must also have the shortest possible conduction paths. If vias are used, connect several paralleled vias to reduce the inductance of the vias. • It may be necessary to add resistance to dampen resonating parasitic circuits especially on LO and LO. If an external gate resistor is unacceptable, then the layout must be improved to minimize lead inductance. • Keep high dv/dt nodes away from low level circuits. Guard banding can be used to shunt away dv/dt injected currents from sensitive circuits. • Avoid having a signal ground plane under a high amplitude dv/dt circuit. The parasitic capacitance of a ground plane, Cp, relative to the high amplitude dv/dt circuit will result in injected (Cp x dv/dt) currents into the signal ground paths where C is the parasitic capacitance of the ground plane. • Do power dissipation and voltage drop calculations of the power traces. Many PCB/CAD programs have built in tools for calculation of trace resistance. The internet is also a good source for resistance calculators for PCB trace resistance. FN8276.0 November 27, 2013 HIP2103, HIP2104 • Large power components (Power FETs, Electrolytic caps, power resistors, etc.) have internal parasitic inductance which cannot be eliminated. This must be accounted for in the PCB layout and circuit design. vias and the size of the GND planes required for adequate heatsinking is determined by the power dissipated by the HIP2103, HIP2104, the air flow, and the maximum temperature of the air around the IC. • If you simulate your circuits, consider including parasitic components especially parasitic inductance. Note that a separate plane is added under the high side drive circuits and is connected to HS. In a manner similar to the ground plane, the HS plane provides the lowest possible parasitic inductance for the HO/HS gate drive current loop. General EPAD Heatsinking Considerations The EPAD of the HIP2103, HIP2104 is electrically connected to VSS through the IC substrate. The epad has two main functions: to provide a quiet signal ground and to provide heat sinking for the IC. The EPAD must be connected to a ground plane and switching currents from the driven FETs should not pass through the ground plane under the IC. Figure 28 is a PCB layout example of how to use vias to remove heat from the IC through the EPAD. For maximum heatsinking, it is recommended that a ground plane, connected to the EPAD, be added to both sides of the PCB. A via array, within the area of the EPAD, will conduct heat from the EPAD to the GND plane on the bottom layer. The number of See AN1899 “HIP2103, HIP2104 3-phase, Full, or Half Bridge Motor Driver” for an example of PCB layout of a real application. VDD EPAD GND PLANE EPAD GND PLANE HB VDD HI HO HI HO LI HS LI HS LO LS LS COMPONENT LAYER HB This plane is connected to HS and is under all high side driver circuits LO BOTTOM LAYER FIGURE 28. TYPICAL PCB PATTERN FOR THERMAL VIAS Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION November 27, 2013 FN8276.0 CHANGE Initial Release About Intersil Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/en/support/ask-an-expert.html. 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No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 19 FN8276.0 November 27, 2013 HIP2103, HIP2104 Package Outline Drawing L8.3x3A 8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 2/10 ( 2.30) 3.00 ( 1.95) A B 3.00 ( 8X 0.50) 6 PIN 1 INDEX AREA (4X) (1.50) ( 2.90 ) 0.15 PIN 1 TOP VIEW (6x 0.65) ( 8 X 0.30) TYPICAL RECOMMENDED LAND PATTERN SEE DETAIL "X" 2X 1.950 PIN #1 INDEX AREA 0.10 C 0.75 ±0.05 6X 0.65 C 0.08 C 1 SIDE VIEW 6 1.50 ±0.10 8 8X 0.30 ±0.05 8X 0.30 ± 0.10 2.30 ±0.10 C 4 0.10 M C A B 0 . 2 REF 5 0 . 02 NOM. 0 . 05 MAX. DETAIL "X" BOTTOM VIEW NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.20mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be 7. Compliant to JEDEC MO-229 WEEC-2 except for the foot length. either a mold or mark feature. 20 FN8276.0 November 27, 2013 HIP2103, HIP2104 Package Outline Drawing L12.4x4A 12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 6/12 2.5 REF 4.00 A PIN #1 INDEX AREA 10X 0.50 BSC 6 B 6 1 12X 0 . 45 6 PIN 1 INDEX AREA 4.00 1.58 0.15 (4X) 12 7 TOP VIEW 0.10 M C A B 0.05 M C 4 12 X 0.25 2.80 BOTTOM VIEW ( 2.80 ) SEE DETAIL "X" 1.00 MAX ( 12 X 0.65 ) 0.10 C BASE PLANE C SIDE VIEW ( 3.75) SEATING PLANE 0.08 C ( 1.58) 0 . 2 REF C ( 10X 0 . 5 ) 0 . 00 MIN. 0 . 05 MAX. ( 12X 0 . 25) DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Lead width applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 21 FN8276.0 November 27, 2013