HITACHI HM6216255HJP-12

HM6216255H Series
4M high Speed SRAM (256-kword × 16-bit)
ADE-203-763D (Z)
Rev. 1.0
Sep. 15, 1998
Description
The HM6216255H Series is a 4-Mbit high speed static RAM organized 256-k word × 16-bit. It has realized
high speed access time by employing CMOS process (4-transistor + 2-poly resistor memory cell) and high
speed circuit designing technology. It is most appropriate for the application which requires high speed, high
density memory and wide bit width configuration, such as cache and buffer memory in system. It is packaged
in 400-mil 44-pin plastic SOJ and 400-mil 44-pin plastic TSOPII.
Features
• Single 5.0 Vsupply : 5.0 V ± 10 %
• Access time: 10/12/15 ns (max)
• Completely static memory
 No clock or timing strobe required
• Equal access and cycle times
• Directly TTL compatible
 All inputs and outputs
• Operating current: 200/180/160 mA (max)
• TTL standby current: 70/60/50 mA (max)
• CMOS standby current: 5 mA (max)
: 1.2 mA (max) (L-version)
• Data retansion current: 0.8 mA (max) (L-version)
• Data retantion voltage: 2 V (min) (L-version)
• Center VCC and VSS type pinout
HM6216255H Series
Ordering Information
Type No.
Access time
Package
HM6216255HJP-10
HM6216255HJP-12
HM6216255HJP-15
10 ns
12 ns
15 ns
400-mil 44-pin plastic SOJ (CP-44D)
HM6216255HLJP-10
HM6216255HLJP-12
HM6216255HLJP-15
10 ns
12 ns
15 ns
HM6216255HTT-10
HM6216255HTT-12
HM6216255HTT-15
10 ns
12 ns
15 ns
HM6216255HLTT-10
HM6216255HLTT-12
HM6216255HLTT-15
10 ns
12 ns
15 ns
400-mil 44-pin plastic TSOPII (TTP-44DE)
Pin Arrangement
HM6216255HJP/HLJP Series
A0
A1
A2
A3
A4
CS
I/O1
I/O2
I/O3
I/O4
VCC
VSS
I/O5
I/O6
I/O7
I/O8
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
(Top View)
2
A17
A16
A15
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
VSS
VCC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
HM6216255HTT/HLTT Series
A0
A1
A2
A3
A4
CS
I/O1
I/O2
I/O3
I/O4
VCC
VSS
I/O5
I/O6
I/O7
I/O8
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
(Top View)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
VSS
VCC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
HM6216255H Series
Pin Description
Pin name
Function
Pin name
Function
A0 to A17
Address input
UB
Upper byte select
I/O1 to I/O16
Data input/output
LB
Lower byte select
CS
Chip select
VCC
Power supply
OE
Output enable
VSS
Ground
WE
Write enable
NC
No connection
Block Diagram
(LSB)
A1
A17
A7
A11
A16
A2
A6
A5
(MSB)
Row
decoder
Internal
voltage VCC
generater
VSS
Memory matrix
256 rows × 8 columns ×
128 blocks × 16 bit
(4,194,304 bits)
CS
I/O1
..
.
I/O8
Column I/O
Input
data
control
I/O9
..
.
I/O16
WE
CS
LB
Column decoder
CS
A10 A8 A9 A12 A13 A14 A0 A15 A3 A4
UB
OE
CS
3
HM6216255H Series
Operation Table
CS
OE
WE
LB
UB
Mode
VCC current
I/O1–I/O8
I/O9–I/O16
Ref. cycle
H
×
×
×
×
Standby
I SB , I SB1
High-Z
High-Z
—
L
H
H
×
×
Output disable
I CC
High-Z
High-Z
—
L
L
H
L
L
Read
I CC
Output
Output
Read cycle
L
L
H
L
H
Lower byte read I CC
Output
High-Z
Read cycle
L
L
H
H
L
Upper byte read I CC
High-Z
Output
Read cycle
L
L
H
H
H
—
I CC
High-Z
High-Z
—
L
×
L
L
L
Write
I CC
Input
Input
Write cycle
L
×
L
L
H
Lower byte write I CC
Input
High-Z
Write cycle
L
×
L
H
L
Upper byte write I CC
High-Z
Input
Write cycle
L
×
L
H
H
—
High-Z
High-Z
—
Note:
I CC
×: H or L
Absolute Maximum Ratings
Parameter
Symbol
Value
Supply voltage relative to VSS
VCC
–0.5 to +7.0
Voltage on any pin relative to V SS
VT
Unit
1
V
2
–0.5* to V CC + 0.5*
3
4
V
Power dissipation
PT
1.0* /1.3*
Operating temperature
Topr
0 to +70
°C
Storage temperature
Tstg
–55 to +125
°C
Storage temperature under bias
Tbias
–10 to +85
°C
Notes: 1.
2.
3.
4.
4
VT (min) = –2.0 V for pulse width (under shoot) ≤ 8 ns
VT (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 8 ns
At still air condition
At air flow ≥ 1.0 m/s
W
HM6216255H Series
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
Supply voltage
Input voltage
Min
Typ
Max
Unit
VCC*
2
4.5
5.0
5.5
V
VSS *
3
0
0
0
VIH
2.2
1
VIL
Notes: 1.
2.
3.
4.
–0.5*
V
2
—
VCC + 0.5*
V
—
0.8
V
VIL (min) = –2.0 V for pulse width (under shoot) ≤ 8 ns
VIH (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 8 ns
The supply voltage with all VCC pins must be on the same level.
The supply voltage with all VSS pins must be on the same level.
DC Characteristics (Ta = 0 to +70°C, VCC = 5.0 V ± 10 %, VSS = 0 V)
Parameter
Symbol Min
Typ*1
Max
Unit Test conditions
Input leakage current
|ILI|
—
—
2
µA
Vin = VSS to V CC
Output leakage
current* 1
|ILO |
—
—
2
µA
Vin = VSS to V CC
10 ns cycle I CC
—
—
200
mA
CS = VIL, Iout = 0 mA
Other inputs = VIH/VIL
12 ns cycle I CC
—
—
180
15 ns cycle I CC
—
—
160
10 ns cycle I SB
—
—
70
mA
CS = VIH,
Other inputs = VIH/VIL
12 ns cycle I SB
—
—
60
15 ns cycle I SB
—
—
50
—
0.1
5
mA
VCC ≥ CS ≥ VCC – 0.2 V,
(1) 0 V ≤ Vin ≤ 0.2 V or
(2) VCC ≥ Vin ≥ VCC – 0.2 V
—* 2
0.1*2
1.2 * 2
VOL
—
—
0.4
V
I OL = 8 mA
VOH
2.4
—
—
V
I OH = –4 mA
Operating power
supply current
Standby power supply
current
I SB1
Output voltage
Note:
1. Typical values are at VCC = 5.0 V, Ta = +25°C and not guaranteed.
2. This characteristics is guaranteed only for L-version.
5
HM6216255H Series
Capacitance (Ta = +25°C, f = 1.0 MHz)
Parameter
1
Input capacitance*
Input/output capacitance*
Note:
6
1
Symbol
Min
Typ
Max
Unit
Test conditions
Cin
—
—
6
pF
Vin = 0 V
CI/O
—
—
8
pF
VI/O = 0 V
1. This parameter is sampled and not 100% tested.
HM6216255H Series
AC Characteristics (Ta = 0 to +70°C, VCC = 5.0 V ± 10 %, unless otherwise noted.)
Test Conditions
•
•
•
•
Input pulse levels: 3.0 V/0.0 V
Input rise and fall time: 3 ns
Input and output timing reference levels: 1.5 V
Output load: See figures (Including scope and jig)
5V
480Ω
Dout Zo=50 Ω
Dout
RL=50 Ω
255Ω
1.5 V
Output load (A)
5 pF
Output load (B)
(for tCLZ, tOLZ, tLBLZ, tUBLZ, tCHZ, tOHZ,
tLBHZ, tUBHZ, tWHZ, and tOW)
Read Cycle
HM6216255H
-10
-12
-15
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Read cycle time
t RC
10
—
12
—
15
—
ns
Address access time
t AA
—
10
—
12
—
15
ns
Chip select access time
t ACS
—
10
—
12
—
15
ns
Output enable to output valid
t OE
—
5
—
6
—
7
ns
Byte select to output valid
t LB, t UB
—
5
—
6
—
7
ns
Output hold from address change
t OH
3
—
3
—
3
—
ns
Chip select to output in low-Z
t CLZ
3
—
3
—
3
—
ns
1
Output enable to output in low-Z
t OLZ
0
—
0
—
0
—
ns
1
Byte select to output in low-Z
t LBLZ, t UBLZ
0
—
0
—
0
—
ns
1
Chip deselect to output in high-Z
t CHZ
—
5
—
6
—
7
ns
1
Output disable to output in high-Z
t OHZ
—
5
—
6
—
7
ns
1
Byte deselect to output in high-Z
t LBHZ, t UBHZ
—
5
—
6
—
7
ns
1
7
HM6216255H Series
Write Cycle
HM6216255H
-10
-12
-15
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Write cycle time
t WC
10
—
12
—
15
—
ns
Address valid to end of write
t AW
7
—
8
—
10
—
ns
Chip select to end of write
t CW
7
—
8
—
10
—
ns
8
Write pulse width
t WP
7
—
8
—
10
—
ns
7
Byte select to end of write
t LBW, t UBW
7
—
8
—
10
—
ns
9, 10
Address setup time
t AS
0
—
0
—
0
—
ns
5
Write recovery time
t WR
0
—
0
—
0
—
ns
6
Data to write time overlap
t DW
5
—
6
—
7
—
ns
Data hold from write time
t DH
0
—
0
—
0
—
ns
Write disable to output in low-Z
t OW
3
—
3
—
3
—
ns
1
Output disable to output in high-Z
t OHZ
—
5
—
6
—
7
ns
1
Write enable to output in high-Z
t WHZ
—
5
—
6
—
7
ns
1
Notes: 1. Transition is measured ±200 mV from steady voltage with Load (B). This parameter is sampled
and not 100% tested.
2. If the CS or LB or UB low transition occurs simultaneously with the WE low transition or after the
WE transition, output remains a high impedance state.
3. WE and/or CS must be high during address transition time.
4. If CS, OE, LB and UB are low during this period, I/O pins are in the output state. Then the data
input signals of opposite phase to the outputs must not be applied to them.
5. t AS is measured from the latest address transition to the latest of CS, WE, LB or UB going low.
6. t WR is measured from the earliest of CS, WE, LB or UB going high to the first address transition.
7. A write occurs during the overlap of low CS, low WE and low LB or low UB.
8. t CW is measured from the later of CS going low to the end of write.
9. t LBW is measured from the later of LB going low to the end of write.
10. t UBW is measured from the later of UB going low to the end of write.
8
HM6216255H Series
Timing Waveforms
Read Timing Waveform (1) (WE = VIH)
t RC
Address
Valid address
tAA
tACS
CS
tCHZ *1
tOE
OE
tOHZ *1
tLB
LB
tLBHZ*1
tUB
UB
tUBHZ*1
tLBLZ *1
Dout
(Lower byte)
High Impedance *4
*4
Valid data
tUBLZ *1
tOH
tOLZ *1
tCLZ *1
Dout
(Upper byte)
High Impedance *4
Valid data
*4
9
HM6216255H Series
Read Timing Waveform (2) (WE = VIH, LB = VIL , UB, = VIL)
tRC
Address
Valid address
tOH
tAA
tACS
tCHZ*1
CS
tOE
tOHZ*1
OE
tOLZ*1
tCLZ *1
Dout
(Lower/Upper
byte)
10
High Impedance *4
Valid data
*4
HM6216255H Series
Write Timing Waveform (1) (LB, UB Controlled)
tWC
Valid address
Address
tAW
tWR
tAS
tWP
WE*3
tCW
CS*3
OE
tLBW
LB
tUBW
UB
tOLZ
tWHZ
tOHZ
tOW
Dout
(Lower byte)
High impedance
Dout
(Upper byte)
High impedance
tDW
Din
(Lower byte)
Valid data
tDW
Din
(Upper byte)
tDH
tDH
Valid data
11
HM6216255H Series
Write Timing Waveform (2) (WE Controlled)
tWC
Valid address
Address
tWR
tAW
tAS
tWP
WE*3
tCW
CS*3
OE
tLBW
tUBW
LB, UB
tOLZ
tWHZ
tOW
tOHZ
Dout
(Lower/Upper
byte)
Din
(Lower/Upper
byte)
12
High impedance
*2
tDW
tDH
Valid data
HM6216255H Series
Write Timing Waveform (3) (CS Controlled)
tWC
Valid address
Address
tWR
tAW
tAS
tWP
WE *3
tCW
CS *3
OE
tLBW
tUBW
LB, UB
tOLZ
tWHZ
tOW
tOHZ
Dout
(Lower/Upper
byte)
Din
(Lower/Upper
byte)
4
High impedance *
*2
tDW
tDH
Valid data
13
HM6216255H Series
Low VCC Data Retention Characteristics (Ta = 0 to +70°C)
This characteristics is guaranteed only for L-version.
Parameter
Symbol
Min
Typ*1 Max
Unit
Test conditions
VCC for data retention
VDR
2.0
—
—
V
VCC ≥ CS ≥ VCC – 0.2 V,
(1) 0 V ≤ Vin ≤ 0.2 V or
(2) VCC ≥ Vin ≥ VCC – 0.2 V
Data retention current
I CCDR
—
50
800
µA
VCC = 3 V
VCC ≥ CS ≥ VCC – 0.2 V,
(1) 0 V ≤ Vin ≤ 0.2 V or
(2) VCC ≥ Vin ≥ VCC – 0.2 V
Chip deselect to data retention time
t CDR
0
—
—
ns
See retention waveform
Operation recovery time
tR
5
—
—
ms
Note:
1. Typical values are at VCC = 3.0 V, Ta = +25˚C, and not guaranteed.
Low V CC Data Retention Timing Waveform
tCDR
Data retention mode
VCC
3.0 V
VDR
2.2 V
CS
0V
14
VCC ≥ CS ≥ VCC – 0.2 V
tR
HM6216255H Series
Package Dimensions
HM6216255HJP/HLJP Series (CP-44D)
Unit: mm
28.33
28.90 Max
0.43 ± 0.10
0.41 ± 0.08
1.27
0.10
Dimension including the plating thickness
Base material dimension
2.65 ± 0.12
1.30 Max
0.80 +0.25
–0.17
22
0.74
3.50 ± 0.26
1
11.18 ± 0.13
23
10.16 ± 0.13
44
9.40 ± 0.25
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
CP-44D
Conforms
—
1.8 g
15
HM6216255H Series
HM6216255HTT/HLTT Series (TTP-44DE)
Unit: mm
18.41
18.81 Max
23
10.16
44
0.80
0.27 ± 0.07
0.25 ± 0.05
22
0.80
0.13 M
11.76 ± 0.20
1.005 Max
Dimension including the plating thickness
Base material dimension
16
0.13 ± 0.05
0.10
0.145 ± 0.05
0.125 ± 0.04
1.20 Max
0° – 5°
0.50 ± 0.10
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
TTP-44DE
—
—
0.43 g
0.68
1
HM6216255H Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual
property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for
maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
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: http://www.hitachi.co.jp/Sicd/indx.htm
For further information write to:
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Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
17