HM628512 Series 524288-word × 8-bit High Speed CMOS Static RAM ADE-203-236F (Z) Rev. 6.0 Jun. 9, 1995 Description The Hitachi HM628512 is a 4-Mbit static RAM organized 512-kword × 8-bit. It realizes igher density, higher performance and low power consumption by employing 0.5 µm Hi-CMOS process technology. The device, packaged in a 525-mil SOP (foot print pitch width) or 400-mil TSOP TYPE II or 600-mil plastic DIP, is available for high density mounting. LP-version is suitable for battery backup system. Features • High speed: Fast access time: 55/65/70 ns (max) • Low power Standby: 10 µW (typ) (L/L-SL version) Operation: 75 mW (typ) (f = 1 MHz) • Single 5 V supply • Completely static memory No clock or timing strobe required • Equal access and cycle times • Common data input and output: Three state output • Directly TTL compatible: All inputs and outputs • Capability of battery backup operation (L/L-SL version) HM628512 Series Ordering Information Type No. Access Time Package HM628512P-5 HM628512P-7 55 ns 70 ns 600-mil 32-pin plastic DIP (DP-32) HM628512LP-5 HM628512LP-7A HM628512LP-7 55 ns 65 ns 70 ns HM628512LP-5SL HM628512LP-7SL 55 ns 70 ns HM628512FP-5 HM628512FP-7 55 ns 70 ns HM628512LFP-5 HM628512LFP-7A HM628512LFP-7 55 ns 65 ns 70 ns HM628512LFP-5SL HM628512LFP-7SL 55 ns 70 ns HM628512LTT-5 HM628512LTT-7A HM628512LTT-7 55 ns 65 ns 70 ns HM628512LTT-5SL HM628512LTT-7SL 55 ns 70 ns HM628512LRR-5 HM628512LRR-7A HM628512LRR-7 55 ns 65 ns 70 ns HM628512LRR-5SL HM628512LRR-7SL 55 ns 70 ns 2 525-mil 32-pin plastic SOP (FP-32D) 400-mil 32-pin plastic TSOP II (TTP-32D) 400-mil 32-pin plastic TSOP II reverse (TTP-32DR) HM628512 Series Pin Arrangement HM628512P/LP Series HM628512FP/LFP Series HM628512LTT Series A18 1 32 VCC A16 2 31 A15 A14 3 30 A17 A12 4 29 WE A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 OE A2 10 23 A10 A1 11 22 CS A0 12 21 I/O7 I/O0 13 20 I/O6 I/O1 14 19 I/O5 I/O2 15 18 I/O4 VSS 16 17 I/O3 (Top View) A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A17 WE A13 A8 A9 A11 OE A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS (Top View) HM628512LRR Series VCC A15 A17 WE A13 A8 A9 A11 OE A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 (Top View) Pin Description Pin name Function A0 – A18 Address I/O0 – I/O7 Input/output CS Chip select OE Output enable WE Write enable VCC Power supply VSS Ground 3 HM628512 Series Block Diagram A5 V CC A6 V SS A0 A1 A2 A3 Row Decoder • • • • • Memory Matrix 1,024 × 4,096 A4 A7 A12 A14 I/O0 Column I/O • • Input Data Control Column Decoder I/O7 A13 A17 A15 A10 A11 A9 A8 A16 A18 • • CS WE OE 4 Timing Pulse Generator Read/Write Control • • HM628512 Series Function Table WE CS OE Mode VCC Current Dout Pin Ref. Cycle X H X Not selected I SB , I SB1 High-Z — H L H Output disable I CC High-Z — H L L Read I CC Dout Read cycle L L H Write I CC Din Write cycle (1) L L L Write I CC Din Write cycle (2) Note: X: H or L Absolute Maximum Ratings Parameter Symbol *1 Value Unit *2 VT –0.5 to +7.0 V Power dissipation PT 1.0 W Operating temperature Topr 0 to +70 °C Storage temperature Tstg –55 to +125 °C Storage temperature under bias Tbias –10 to +85 °C Voltage on any pin relative to V SS Notes: 1. Relative to VSS . 2. –3.0 V for pulse half-width ≤ 30 ns Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Symbol Min Typ Max Unit Supply voltage VCC 4.5 5.0 5.5 V VSS 0 0 0 V VIH 2.2 — 6.0 V — 0.8 V Input high (logic 1) voltage Input low (logic 0) voltage Note: VIL –0.3 *1 1. –3.0 V for pulse half-width ≤ 30 ns 5 HM628512 Series DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ±10% , VSS = 0 V) Parameter Symbol Min Typ*1 Max Unit Test Conditions Input leakage current |ILI| — — 1 µA Vin = VSS to V CC Output leakage current |ILO | — — 1 µA CS = VIH or OE = VIH or WE = VIL, VI/O = VSS to V CC Operating power supply current: DC I CC READ — 15 25 mA CS = VIL, WE = VIH others = VIH/V IL, I I/O = 0 mA I CC WRITE — 20 45 mA CS = VIL, WE = VIL others = VIH/V IL, I I/O = 0 mA -5/7A I CC1 — 70 100 mA Min cycle, duty = 100% -7 I CC1 — 60 90 mA CS = VIL, others = VIH/V IL I I/O = 0 mA Operating power supply current I CC2 — 15 30 mA Cycle time = 1 µs, duty = 100% I I/O = 0 mA, CS ≤ 0.2 V VIH ≥ V CC – 0.2 V, VIL ≤ 0.2 V Standby power supply current: DC I SB — 1 3 mA CS = VIH Standby power supply current (1): DC I SB1 — 0.02 2 mA Vin ≥ 0 V, CS ≥ V CC – 0.2 V Operating power supply current 2 100 µA — 2 *3 50 µA — *2 Output low voltage VOL — — 0.4 V I OL = 2.1 mA Output high voltage VOH 2.4 — — V I OH = –1.0 mA Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and specified loading, and not guaranteed. 2. This characteristics is guaranteed only for L version. 3. This characteristics is guaranteed only for L-SL version. Capacitance (Ta = 25°C, f = 1 MHz) Parameter Input capacitance *1 *1 Input/output capacitance Note: 6 Symbol Typ Max Unit Test Conditions Cin — 8 pF Vin = 0 V CI/O — 10 pF VI/O = 0 V 1. This parameter is sampled and not 100% tested. HM628512 Series AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, unless otherwise noted.) Test Conditions • • • • Input pulse levels: 0.8 V to 2.4 V Input rise and fall time: 5 ns Input and output timing reference levels: 1.5 V Output load: 1 TTL Gate + C L (100 pF) (HM628512-7A/7) 1 TTL Gate + C L (50 pF) (HM628512-5) (Including scope & jig) Read Cycle HM628512 -5 -7A -7 Parameter Symbol Min Max Min Max Min Max Unit Notes Read cycle time t RC 55 — 65 — 70 — ns Address access time t AA — 55 — 60 — 70 ns Chip select access time t CO — 55 — 65 — 70 ns Output enable to output valid t OE — 25 — 30 — 35 ns Chip selection to output in low-Z t LZ 10 — 10 — 10 — ns 2 Output enable to output in low-Z t OLZ 5 — 5 — 5 — ns 2 Chip deselection to output in high-Z t HZ 0 20 0 20 0 25 ns 1, 2 Output disable to output in high-Z t OHZ 0 20 0 20 0 25 ns 1, 2 Output hold from address change t OH 10 — 10 — 10 — ns Notes: 1. t HZ and t OHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 7 HM628512 Series Read Timing Waveform*1 t RC Address t AA t CO CS t LZ t HZ t OE t OLZ OE t OHZ Dout Valid Data t OH Note: 1. WE is high for read cycle. 8 HM628512 Series Write Cycle HM628512 -5 -7A -7 Parameter Symbol Min Max Min Max Min Max Unit Notes Write cycle time t WC 55 — 55 — 70 — ns Chip selection to end of write t CW 50 — 50 — 60 — ns 2 Address setup time t AS 0 — 0 — 0 — ns 3 Address valid to end of write t AW 50 — 50 — 60 — ns Write pulse width t WP 40 — 40 — 50 — ns 1, 8 Write recovery time t WR 5 — 5 — 5 — ns 4 WE to output in high-Z t WHZ 0 20 0 20 0 25 ns 5, 6, 7 Data to write time overlap t DW 25 — 25 — 30 — ns Data hold from write time t DH 0 — 0 — 0 — ns Output active from output in high-Z t OW 5 — 5 — 5 — ns 6 Output disable to output in high-Z t OHZ 0 20 0 20 0 25 ns 5, 6 Notes: 1. A write occurs during the overlap (tWP) of a low CS and a low WE. A write begins at the later transition of CS going low or WE going low. A write ends at the earlier transition of CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 2. t CW is measured from CS going low to the end of write. 3. t AS is measured from the address valid to the beginning of write. 4. t WR is measured from the earlier of WE or CS going high to the end of write cycle. 5. During this period, I/O pins are in the output state so that the input signals of the opposite phase to the outputs must not be applied. 6. This parameter is sampled and not 100% tested. 7. t WHZ is defined as the time at which the outputs acheive the open circuit conditons and is not referred to output voltage levels. 8. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of data bus contention. t WP ≥ tDW min + tWHZ max 9 HM628512 Series Write Timing Waveform (1) (OE Clock) t WC Address t AW t WR OE t CW CS *1 t WP t AS WE t OHZ Dout t DW Din t DH Valid Data Note: 1. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output remain in a high impedance state. 10 HM628512 Series Write Timing Waveform (2) (OE Low Fixed) t WC Address t CW t WR CS *1 t AW t WP WE t OH t AS t OW t WHZ *2 *3 Dout t DW t DH *4 Din Valid Data Notes: 1. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output remain in a high impedance state. 2. Dout is the same phase of the write data of this write cycle. 3. Dout is the read data of next address. 4. If CS is low during this period, I/O pins are in the output state. Therefore, the input signals of the opposite phase to the outputs must not be applied to them. 11 HM628512 Series Low VCC Data Retention Characteristics (Ta = 0 to +70°C) This characteristics is guaranteed only for L/L-SL version. Parameter Symbol Min Typ Max Unit Test Conditions*3 VCC for data retention VDR 2 — — Data retention current I CCDR V CS ≥ V CC – 0.2 V, Vin ≥ 0 V *1 µA VCC = 3.0 V, Vin ≥ 0 V *2 1 *4 — 1 *4 15 µA CS ≥ V CC – 0.2 V See retention waveform — 50 Chip deselect to data retention time t CDR 0 — — ns Operation recovery time tR 5 — — ms Notes: 1. For L-version and 20 µA (max.) at Ta = 0 to 40°C. 2. For SL-version and 3 µA (max.) at Ta = 0 to 40°C. 3. CS controls address buffer, WE buffer, OE buffer, and Din buffer. In data retention mode, Vin levels (address, WE, OE, I/O) can be in the high impedance state. 4. Typical values are at VCC = 3.0 V, Ta = 25°C and specified loading, and not guaranteed. Low V CC Data Retention Timing Waveform (CS Controlled) t CDR Data retention mode V CC 4.5 V 2.4 V V DR CS 0V 12 CS ≥ VCC – 0.2 V tR HM628512 Series Package Dimensions HM62851P/LP Series (DP-32) Unit: mm 41.9 42.5 Max 17 13.4 13.7 Max 32 16 5.08 Max 1.2 2.3 Max 2.54 ± 0.25 0.48 ± 0.10 0.51 Min 2.54 Min 1 15.24 + 0.11 0.25 – 0.05 0° – 15° 13 HM628512 Series HM628512FP/LFP Series (FP-32D) Unit: mm 20.45 20.95 Max 17 11.7 Max 32 14.14 ± 0.30 1 0.10 1.27 0.10 0.40 +– 0.05 + 0.13 – 0.07 1.42 0–8° 0.05 Min 1.0 Max 0.22 3.0 Max 16 0.8 0.15 M HM628512LTT Series (TTP-32D) Unit: mm 20.95 21.35 Max 17 10.16 32 0.21 0.10 16 M 1.15 Max 11.76 ± 0.2 0.08 Min 0.18 Max 1.20 Max 0.40 ± 0.10 1.27 0.17 ± 0.05 1 0.50 ± 0.10 14 0 – 5° HM628512 Series HM628512LRR Series (TTP-32DR) Unit: mm 20.95 21.35 Max 16 10.16 1 0.21 0.10 17 M 1.15 Max 11.76 ± 0.2 0.08 Min 0.18 Max 1.20 Max 0.40 ± 0.10 1.27 0.17 ± 0.05 32 0 – 5° 0.50 ± 0.10 15