HM62W1664HB Series 1 M High Speed SRAM (64-kword × 16-bit) ADE-203-415B (Z) Rev. 2.0 Nov. 1997 Description The HM62W1664HB is an asynchronous high speed static RAM organized as 64-kword × 16-bit. It realize high speed access time (25/30 ns) with employing 0.8 µm CMOS process and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. The HM62W1664HB is packaged in 400-mil 44-pin SOJ for high density surface mounting. Features • Single 3.3 V supply (3.3 V ± 0.3V) • Access time: 25/30 ns (max) • Completely static memory No clock or timing strobe required • Equal access and cycle times • Directly LV-TTL compatible All inputs and outputs • 400-mil 44-pin SOJ package • Center VCC and VSS type pinout Ordering Information Type No. Access time Package HM62W1664HBJP-25 HM62W1664HBJP-30 25 ns 30 ns 400-mil 44-pin plastic SOJ (CP-44D) HM62W1664HBLJP-25 HM62W1664HBLJP-30 25 ns 30 ns HM62W1664HB Series Pin Arrangement HM62W1664HBJP/HBLJP Series A4 A3 A2 A1 A0 CS I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 (Top View) Pin Description Pin name Function A0 – A15 Address input I/O1 – I/O16 Data input/output CS Chip select OE Output enable WE Write enable UB Upper byte select LB Lower byte select VCC Power supply VSS Ground NC No connection 2 A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC HM62W1664HB Series Block Diagram (LSB) A3 A2 A1 A0 A7 A6 A5 A4 (MSB) VCC Row decoder Memory matrix 256 rows × 256 columns × 16 bit (1,048,576 bits) VSS CS I/O1 . . . I/O8 Column I/O Input data control I/O9 . . . I/O16 WE CS LB Column decoder CS (LSB) A12 A11 A10 A15 A14 A13 A9 A8 (MSB) UB OE CS Function Table CS OE WE LB UB Mode VCC current I/O1–I/O8 I/O9–I/O16 Ref. cycle H × × × × Standby I SB , I SB1 High-Z High-Z — L H H × × Output disable I CC High-Z High-Z — L L H L L Read I CC Output Output Read cycle L L H L H Lower byte read I CC Output High-Z Read cycle L L H H L Upper byte read I CC High-Z Output Read cycle L L H H H — I CC High-Z High-Z — L × L L L Write I CC Input Input Write cycle L × L L H Lower byte write I CC Input High-Z Write cycle L × L H L Upper byte write I CC High-Z Input Write cycle L × L H H — High-Z High-Z — Note: I CC ×: H or L 3 HM62W1664HB Series Absolute Maximum Ratings Parameter Symbol Value Unit Supply voltage relative to VSS VCC –0.5 to +4.6 V 1 Voltage on any pin relative to V SS VT –0.5* to V CC + 0.5 V Power dissipation PT 1.0 W Operating temperature Topr 0 to +70 °C Storage temperature Tstg –55 to +125 °C Storage temperature under bias Tbias –10 to +85 °C Notes: 1. VT (min) = –2.5 V for pulse width (under shoot) ≤ 10 ns Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Supply voltage Input voltage Symbol Min Typ Max Unit VCC* 2 3.0 3.3 3.6 V VSS * 3 0 0 0 V — VCC + 0.3 V — 0.8 V VIH VIL 2.0 1 –0.3* Notes: 1. –2.0 V for pulse width (under shoot) ≤ 10 ns 2. The supply voltage with all VCC pins must be on the same level. 3. The supply voltage with all VSS pins must be on the same level. 4 HM62W1664HB Series DC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) Parameter Symbol Min Typ*1 Max Unit Test conditions Input leakage current |ILI| — — 2 µA Vin = VSS to V CC Output leakage current* 1 |ILO | — — 2 µA Vin = VSS to V CC 25 ns cycle I CC — — 100 mA CS = VIL, Iout = 0 mA Other inputs = VIH/V IL 30 ns cycle I CC — — 90 25 ns cycle I SB — — 40 mA CS = VIH, Other inputs = VIH/V IL 30 ns cycle I SB — — 35 — — 1 mA VCC ≥ CS ≥ VCC – 0.2 V, (1) 0 V ≤ Vin ≤ 0.2 V or (2) VCC ≥ Vin ≥ VCC – 0.2 V —* 2 —* 2 0.15*2 — — 0.2 V I OL = 0.1 mA — — 0.4 V I OL = 2 mA VCC – 0.2 — — V I OH = –0.1 mA 2.4 — V I OH = –2 mA Operating power supply current Standby power supply current I SB1 Output voltage VOL VOH Note: — 1. Typical values are at VCC = 3.3 V, Ta = +25°C and not guaranteed. 2. This characteristics is guaranteed only for L-version. Capacitance (Ta = 25°C, f = 1.0 MHz) Parameter 1 Input capacitance* Input/output capacitance* Note: 1 Symbol Min Typ Max Unit Test conditions Cin — — 6 pF Vin = 0 V CI/O — — 8 pF VI/O = 0 V 1. This parameter is sampled and not 100% tested. 5 HM62W1664HB Series AC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, unless otherwise noted.) Test Conditions • • • • Input pulse levels: 2.4 V/0.4 V Input rise and fall time: 3 ns Input and output timing reference levels: 1.4 V Output load: See figures (Including scope and jig) Dout Dout 500 Ω 30 pF 5 pF 1.4V Output load (A) 500 Ω 1.4V Output load (B) (for tCLZ, tOLZ, tLBLZ, tUBLZ, tCHZ, tOHZ, tLBHZ, tUBHZ, tWHZ, and tOW) Read Cycle HM62W1664HB -25 HM62W1664HB -30 Parameter Symbol Min Max Min Max Unit Read cycle time t RC 25 — 30 — ns Address access time t AA — 25 — 30 ns Chip select access time t ACS — 25 — 30 ns Output enable to output valid t OE — 15 — 15 ns Byte select to output valid t LB, t UB — 15 — 15 ns Output hold from address change t OH 5 — 5 — ns Chip select to output in low-Z t CLZ 5 — 5 — ns 1 Output enable to output in low-Z t OLZ 1 — 1 — ns 1 Byte select to output in low-Z t LBLZ, t UBLZ 1 — 1 — ns 1 Chip deselect to output in high-Z t CHZ — 12 — 12 ns 1 Output disable to output in high-Z t OHZ — 12 — 12 ns 1 Byte deselect to output in high-Z t LBHZ, t UBHZ — 12 — 12 ns 1 6 Notes HM62W1664HB Series Write Cycle HM62W1664HB -25 HM62W1664HB -30 Parameter Symbol Min Max Min Max Unit Notes Write cycle time t WC 25 — 30 — ns Address valid to end of write t AW 20 — 20 — ns Chip select to end of write t CW 20 — 20 — ns 8 Write pulse width t WP 20 — 20 — ns 7 Byte select to end of write t LBW, t UBW 20 — 20 — ns 9, 10 Address setup time t AS 0 — 0 — ns 5 Write recovery time t WR 0 — 0 — ns 6 Data to write time overlap t DW 15 — 15 — ns Data hold from write time t DH 0 — 0 — ns Write disable to output in low-Z t OW 5 — 5 — ns 1 Output disable to output in high-Z t OHZ — 12 — 12 ns 1 Write enable to output in high-Z t WHZ — 12 — 12 ns 1 Notes: 1. Transition is measured ±200 mV from steady voltage with Load (B). This parameter is sampled and not 100% tested. 2. If the CS or LB or UB low transition occurs simultaneously with the WE low transition or after the WE transition, output remains a high impedance state. 3. WE and/or CS must be high during address transition time. 4. If CS, OE, LB and UB are low during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 5. t AS is measured from the latest address transition to the latest of CS, WE, LB or UB going low. 6. t WR is measured from the earliest of CS, WE, LB or UB going high to the first address transition. 7. A write occurs during the overlap of low CS, low WE and low LB or low UB. 8. t CW is measured from the later of CS going low to the end of write. 9. t LBW is measured from the later of LB going low to the end of write. 10. t UBW is measured from the later of UB going low to the end of write. 7 HM62W1664HB Series Timing Waveforms Read Timing Waveform (1) (WE = VIH) t RC Address Valid address tAA tACS CS tCHZ *1 tOE OE tOHZ *1 tLB LB tLBHZ*1 tUB UB tUBHZ*1 tLBLZ *1 Dout (Lower byte) High Impedance *4 *4 Valid data tUBLZ *1 tOH tOLZ *1 tCLZ *1 Dout (Upper byte) 8 High Impedance *4 Valid data *4 HM62W1664HB Series Read Timing Waveform (2) (WE = VIH, LB = VIL , UB, = VIL) tRC Address Valid address tOH tAA tACS tCHZ*1 CS tOE tOHZ*1 OE tOLZ*1 tCLZ *1 Dout (Lower/Upper byte) High Impedance *4 Valid data *4 9 HM62W1664HB Series Write Timing Waveform (1) (LB, UB Controlled) tWC Valid address Address tAW tWR tAS tWP WE*3 tCW CS*3 OE tLBW LB tUBW UB tOLZ tWHZ tOHZ tOW Dout (Lower byte) High impedance Dout (Upper byte) High impedance tDW Din (Lower byte) Valid data tDW Din (Upper byte) 10 tDH tDH Valid data HM62W1664HB Series Write Timing Waveform (2) (WE Controlled) tWC Valid address Address tWR tAW tAS tWP WE*3 tCW CS*3 OE tLBW tUBW LB, UB tOLZ tWHZ tOW tOHZ Dout (Lower/Upper byte) Din (Lower/Upper byte) High impedance *2 tDW tDH Valid data 11 HM62W1664HB Series Write Timing Waveform (3) (CS Controlled) tWC Valid address Address tWR tAW tAS tWP WE *3 tCW CS *3 OE tLBW tUBW LB, UB tOLZ tWHZ tOW tOHZ Dout (Lower/Upper byte) Din (Lower/Upper byte) 12 4 High impedance * *2 tDW tDH Valid data HM62W1664HB Series Low VCC Data Retention Characteristics (Ta = 0 to +70°C) This characteristics is guaranteed only for L-version. Parameter Symbol Min Typ*1 Max Unit Test conditions VCC for data retention VDR 2.0 — — V VCC ≥ CS ≥ VCC – 0.2 V, (1) 0 V ≤ Vin ≤ 0.2 V or (2) VCC ≥ Vin ≥ VCC – 0.2 V Data retention current I CCDR — 2 80 µA VCC = 3 V VCC ≥ CS ≥ VCC – 0.2 V, (1) 0 V ≤ Vin ≤ 0.2 V or (2) VCC ≥ Vin ≥ VCC – 0.2 V Chip deselect to data retention time t CDR 0 — — ns See retention waveform Operation recovery time tR 5 — — ms Note: 1. Typical values are at VCC = 3.0 V, Ta = 25°C, and not guaranteed. Low V CC Data Retention Timing Waveform t CDR Data retention mode tR VCC 3.0 V V DR 2.0 V CS 0V VCC ≥ CS ≥ VCC – 0.2 V 13 HM62W1664HB Series Package Dimensions HM62W1664HBJP/HBLJP Series (CP-44D) Unit: mm 28.33 28.90 Max 0.43 ± 0.10 0.41 ± 0.08 1.27 0.10 Dimension including the plating thickness Base material dimension 14 2.65 ± 0.12 1.30 Max 0.80 +0.25 –0.17 22 0.74 3.50 ± 0.26 1 11.18 ± 0.13 23 10.16 ± 0.13 44 9.40 ± 0.25 Hitachi Code JEDEC EIAJ Weight (reference value) CP-44D Conforms — 1.8 g HM62W1664HB Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 Hitachi Europe GmbH Continental Europe Dornacher Straße 3 D-85622 Feldkirchen München Tel: 089-9 91 80-0 Fax: 089-9 29 30-00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 01628-585000 Fax: 01628-585160 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan. 15 HM62W1664HB Series Revision Record Rev. Date Contents of Modification Drawn by Approved by 0.0 Aug. 3, 1995 Initial issue T. Nojiri K. Yoshizaki 0.1 Jul. 18, 1996 Change of format Change of Block Diagram Function Table Addition of Mode Parameter Recommended DC Operating Conditions Change of note 2. Addition of note 3. DC Characteristics Addition of note 2 AC Characteristics Change order of notes t OE (max) : 12/15 ns to 15/15 ns t AW (min) : 15/20 ns to 20/20 ns t CW (min) : 15/20 ns to 20/20 ns t WP (min) : 15/20 ns to 20/20 ns t LBW, t UBW (min) : 15/20 ns to 20/20 ns t DW (min) : 12/15 ns to 15/15 ns t WHZ (max) : 10/10 ns to 12/12 ns Addition of t OE (Write Cycle) Change of Timing Waveform Addition of Read Timing Waveform (2) Y. Saito A. Ide 1.0 Dec. 25, 1996 Deletion of Preliminary Y. Saitoh A. Ide 2.0 Nov. 1997 Change of Subtitle 16