HM62W4100HC Series 4M High Speed SRAM (1-Mword × 4-bit) ADE-203-1202C (Z) Rev. 2.0 Nov. 9, 2001 Description The HM62W4100HC is a 4-Mbit high speed static RAM organized 1-Mword × 4-bit. It has realized high speed access time by employing CMOS process (6-transistor memory cell) and high speed circuit designing technology. It is most appropriate for the application which requires high speed and high density memory, such as cache and buffer memory in system. The HM62W4100HC is packaged in 400-mil 32-pin SOJ for high density surface mounting. Features • Single supply : 3.3 V ± 0.3 V • Access time : 10/12 ns (max) • Completely static memory No clock or timing strobe required • Equal access and cycle times • Directly TTL compatible All inputs and outputs • Operating current : 115/100 mA (max) • TTL standby current : 40 mA (max) • CMOS standby current: 5 mA (max) : 1 mA (max) (L-version) • Data retention current : 0.6 mA (max) (L-version) • Data retention voltage: 2 V (min) (L-version) • Center VCC and VSS type pin out HM62W4100HC Series Ordering Information Type No. Access time Device marking Package HM62W4100HCJP-10 HM62W4100HCJP-12 10 ns 12 ns HM62W4100CJP10 HM62W4100CJP12 400-mil 32-pin plastic SOJ (CP-32DB) HM62W4100HCLJP-10 HM62W4100HCLJP-12 10 ns 12 ns HM62W4100CLJP10 HM62W4100CLJP12 Pin Arrangement 32-pin SOJ A0 A1 A2 A3 A4 I/O1 VCC VSS I/O2 A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 (Top view) Pin Description Pin name Function A0 to A19 Address input I/O1 to I/O4 Data input/output CS Chip select OE Output enable WE Write enable VCC Power supply VSS Ground NC No connection Rev. 2, Nov. 2001, page 2 of 13 A19 A18 A17 A16 A15 I/O4 VSS VCC I/O3 A14 A13 A12 A11 A10 NC HM62W4100HC Series Block Diagram (LSB) A14 A13 A12 A5 A6 A7 A11 A10 A3 A1 VCC Row decoder (MSB) 1024-row × 64-column × 16-block × 4-bit (4,194,304 bits) VSS CS Column I/O I/O1 . Input data control . . Column decoder CS I/O4 A8 A9 A19 A17 A18 A15 A0 A2 A4 A16 (LSB) (MSB) CS Rev. 2, Nov. 2001, page 3 of 13 HM62W4100HC Series Operation Table CS OE WE Mode VCC current I/O Ref. cycle H × × Standby ISB, ISB1 High-Z — L H H Output disable ICC High-Z — L L H Read ICC Dout Read cycle (1) to (3) L H L Write ICC Din Write cycle (1) L L L Write ICC Din Write cycle (2) Parameter Symbol Value Supply voltage relative to VSS VCC –0.5 to +4.6 Voltage on any pin relative to VSS VT –0.5* to VCC+0.5* V Power dissipation PT 1.0 W Operating temperature Topr 0 to +70 °C Storage temperature Tstg –55 to +125 °C Storage temperature under bias Tbias –10 to +85 °C Note: H: VIH, L: VIL, ×: VIH or VIL Absolute Maximum Ratings Unit V 1 2 Notes: 1. VT (min) = –2.0 V for pulse width (under shoot) ≤ 6 ns. 2. VT (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns. Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Symbol Supply voltage Input voltage Min Typ Max Unit 3 3.0 3.3 3.6 V 4 VSS* 0 0 0 VIH 2.0 — VCC + 0.5* V — 0.8 V VCC* VIL Notes: 1. 2. 3. 4. 1 –0.5* VIL (min) = –2.0 V for pulse width (under shoot) ≤ 6 ns. VIH (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. Rev. 2, Nov. 2001, page 4 of 13 V 2 HM62W4100HC Series DC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0V) 1 Parameter Symbol Min Typ* Max Unit Test conditions Input leakage current IILII — — 2 µA Vin = VSS to VCC Output leakage current IILOI — — 2 µA Vin = VSS to VCC 10 ns cycle ICC — — 115 mA Min cycle CS = VIL, lout = 0 mA Other inputs = VIH/VIL 12 ns cycle ICC — — 100 mA ISB — — 40 mA Min cycle, CS = VIH, Other inputs = VIH/VIL ISB1 — 2.5 5 mA f = 0 MHz VCC ≥ CS ≥ VCC - 0.2 V, (1) 0 V ≤ Vin≤ 0.2 V or (2) VCC ≥ Vin ≥ VCC - 0.2 V Operation power supply current Standby power supply current 2 Output voltage 2 2 —* 0.5* 1* VOL — — 0.4 V IOL = 8 mA VOH 2.4 — — V IOH = –4 mA Notes: 1. Typical values are at VCC = 3.3 V, Ta = +25°C and not guaranteed. 2. This characteristics is guaranteed only for L-version. Capacitance (Ta = +25°C, f = 1.0 MHz) Parameter Input capacitance* 1 1 Input/output capacitance* Note: Symbol Min Typ Max Unit Test conditions Cin — — 6 pF Vin = 0 V CI/O — — 8 pF VI/O = 0 V 1. This parameter is sampled and not 100% tested. Rev. 2, Nov. 2001, page 5 of 13 HM62W4100HC Series AC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, unless otherwise noted.) Test Conditions • Input pulse levels: 3.0 V/0.0 V • Input rise and fall time: 3 ns • Input and output timing reference levels: 1.5 V • Output load: See figures (Including scope and jig) 1.5 V Dout Zo=50 Ω 3.3 V RL=50 Ω 319Ω Dout 353Ω 30 pF Output load (A) 5 pF Output load (B) (for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, and tOW) Read Cycle HM62W4100HC -10 Parameter Symbol Min Read cycle time tRC Address access time tAA Chip select access time -12 Max Min Max Unit 10 — 12 — ns — 10 — 12 ns tACS — 10 — 12 ns Output enable to output valid tOE — 5 — 6 ns Output hold from address change tOH 3 — 3 — ns Chip select to output in low-Z tCLZ 3 — 3 — ns 1 Output enable to output in low-Z tOLZ 0 — 0 — ns 1 Chip deselect to output in high-Z tCHZ — 5 — 6 ns 1 Output disable to output in high-Z tOHZ — 5 — 6 ns 1 Rev. 2, Nov. 2001, page 6 of 13 Notes HM62W4100HC Series Write Cycle HM62W4100HC -10 Parameter -12 Symbol Min Write cycle time tWC 10 — 12 — ns Address valid to end of write tAW 7 — 8 — ns Chip select to end of write tCW 7 — 8 — ns 9 Write pulse width tWP 7 — 8 — ns 8 Address setup time tAS 0 — 0 — ns 6 Write recovery time tWR 0 — 0 — ns 7 Data to write time overlap tDW 5 — 6 — ns Data hold from write time tDH 0 — 0 — ns Write disable to output in low-Z tOW 3 — 3 — ns 1 Output disable to output in high-Z tOHZ — 5 — 6 ns 1 Write enable to output in high-Z tWHZ — 5 — 6 ns 1 Note: Max Min Max Unit Notes 1. Transition is measured ±200 mV from steady voltage with output load (B). This parameter is sampled and not 100% tested. 2. Address should be valid prior to or coincident with CS transition low. 3. WE and/or CS must be high during address transition time. 4. If CS and OE are low during this period, I/O pins are in the output state. Then, the data input signals of opposite phase to the outputs must not be applied to them. 5. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, output remains a high impedance state. 6. tAS is measured from the latest address transition to the later of CS or WE going low. 7. tWR is measured from the earlier of CS or WE going high to the first address transition. 8. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going low and WE going low. A write ends at the earliest transition among CS going high and WE going high. tWP is measured from the beginning of write to the end of write. 9. tCW is measured from the later of CS going low to the end of write. Rev. 2, Nov. 2001, page 7 of 13 HM62W4100HC Series Timing Waveforms Read Timing Waveform (1) (WE = VIH) tRC Address Valid address tOH tAA tACS CS tOE tCHZ tOHZ OE tOLZ tCLZ Dout High impedance Valid data Read Timing Waveform (2) (WE = VIH, CS = VIL, OE = VIL) tRC Address Valid address tAA tOH tOH Dout Rev. 2, Nov. 2001, page 8 of 13 Valid data HM62W4100HC Series Read Timing Waveform (3) (WE = VIH, CS = VIL, OE = VIL)* 2 tRC CS tACS tCHZ tCLZ Dout High impedance Valid data High impedance Write Timing Waveform (1) (WE Controlled) tWC Valid address Address tWR tAW tCW *3 tAS tWP *3 tOHZ High impedance*5 Dout tDW Din *4 tDH Valid data *4 Rev. 2, Nov. 2001, page 9 of 13 HM62W4100HC Series Write Timing Waveform (2) (CS Controlled) tWC Valid address Address tWR tCW *3 tAW tWP *3 tAS tWHZ tOW High impedance*5 Dout tDW Din Rev. 2, Nov. 2001, page 10 of 13 *4 tDH Valid data *4 HM62W4100HC Series Low VCC Data Retention Characteristics (Ta = 0 to +70°C) This characteristics is guaranteed only for L-version. 1 Parameter Symbol Min Typ* Max Unit Test conditions VCC for data retention VDR 2.0 — — V VCC ≥ CS ≥ VCC – 0.2 V (1) 0 V ≤ Vin ≤ 0.2 V or (2) VCC ≥ Vin ≥ VCC – 0.2 V Data retention current ICCDR — 300 600 µA VCC = 3 V, VCC ≥ CS ≥ VCC – 0.2 V (1) 0 V ≤ Vin ≤ 0.2 V or (2) VCC ≥ Vin ≥ VCC – 0.2 V Chip deselect to data retention time tCDR 0 — — ns See retention waveform Operation recovery time tR 5 — — ms Note: 1. Typical values are at VCC = 3.0 V, Ta = +25°C, and not guaranteed. Low VCC Data Retention Timing Waveform t CDR Data retention mode tR V CC 3.0 V V DR 2.0 V 0V VCC ≥ ≥ VCC – 0.2 V Rev. 2, Nov. 2001, page 11 of 13 HM62W4100HC Series Package Dimensions HM62W4100HCJP/HCLJP Series (CP-32DB) As of January, 2001 Unit: mm 17 10.16 ± 0.13 16 3.50 ± 0.26 0.74 1.30 Max *0.43 ± 0.10 0.41 ± 0.08 1.27 2.85 ± 0.12 1 0.80 +0.25 –0.17 32 11.18 ± 0.13 20.71 21.08 Max 9.40 ± 0.25 0.10 *Dimension including the plating thickness Base material dimension Rev. 2, Nov. 2001, page 12 of 13 Hitachi Code JEDEC EIAJ Mass (reference value) CP-32DB Conforms Conforms 1.2 g HM62W4100HC Series Disclaimer 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Sales Offices Hitachi, Ltd. Semiconductor & Integrated Circuits Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: (03) 3270-2111 Fax: (03) 3270-5109 URL http://www.hitachisemiconductor.com/ For further information write to: Hitachi Semiconductor (America) Inc. 179 East Tasman Drive San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe Ltd. Electronic Components Group Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 585200 Hitachi Asia Ltd. Hitachi Tower 16 Collyer Quay #20-00 Singapore 049318 Tel : <65>-538-6533/538-8577 Fax : <65>-538-6933/538-3877 URL : http://semiconductor.hitachi.com.sg Hitachi Europe GmbH Electronic Components Group Dornacher Straße 3 D-85622 Feldkirchen Postfach 201, D-85619 Feldkirchen Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Asia Ltd. (Taipei Branch Office) 4/F, No. 167, Tun Hwa North Road Hung-Kuo Building Taipei (105), Taiwan Tel : <886>-(2)-2718-3666 Fax : <886>-(2)-2718-8180 Telex : 23222 HAS-TP URL : http://www.hitachi.com.tw Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel : <852>-(2)-735-9218 Fax : <852>-(2)-730-0281 URL : http://semiconductor.hitachi.com.hk Copyright © Hitachi, Ltd., 2001. All rights reserved. Printed in Japan. Colophon 5.0 Rev. 2, Nov. 2001, page 13 of 13