HANBIT HMS1M32Z8S

HANBit
HMS1M32M8S
HAN
High-Speed SRAM MODULE 4Mbyte(1M x 32-Bit)
BIT
Part No.
HMS1M32M8S, HMS1M32Z8S
GENERAL DESCRIPTION
The HMS1M32M8S is a high-speed static random access memory (SRAM) module containing 1,048,576 words
organized in a x32-bit configuration. The module consists of eight 512K x 8 SRAMs mounted on a 72-pin, doublesided, FR4-printed circuit board.
The HMS1M32M8S also support low data retention voltage for battery back-up operations with low data retention
current. Eight chip enable inputs, (/CE_UU1, /CE_UM1, /CE_LM1, /CE_LL1, /CE_UU2, /CE_UM2, /CE_LM2,
/CE_LL2) are used to enable the module’s 4 bytes independently. Output enable (/OE) and write enable(/WE) can
set the memory input and output.
Data is written into the SRAM memory when write enable (/WE) and chip enable (/CE) inputs are both LOW.
Reading is accomplished when /WE remains HIGH and /CE and output enable (/OE) are LOW.
For reliability, this SRAM module is designed as multiple power and ground pin. All module components may be
powered from a single +5V DC power supply and all inputs and outputs are fully TTL-compatible
PIN ASSIGNMENT
FEATURES
Š Part identification
Vss
A3
A2
A1
A0
Vcc
A11
/OE
A10
Vcc
/CE_LL2
/CE_LL1
DQ7
DQ0
DQ1
DQ2
DQ6
DQ5
DQ4
DQ3
A15
A17
/WE
A13
Vcc
DQ8
DQ9
DQ10
/CE_LM2
Vcc
/CE_LM1
DQ15
DQ14
DQ13
DQ12
DQ11
- HMS1M32M8S : SIMM design
- HMS1M32Z8S : ZIP design
Pin-Compatible with the HMS1M32M8S
Š Access times : 10, 12, 15, 17 and 20ns
Š High-density 4MByte design
Š High-reliability, high-speed design
Š Single + 5V ±0.5V power supply
Š All inputs and outputs are TTL-compatible
Š FR4-PCB design
Š 72-Pin SIMM Design
OPTIONS
MARKING
Š Timing
10ns access
-10
12ns access
-12
15ns access
-15
17ns access
-17
20ns access
-20
Š Packages
72-pin SIMM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
A18
A16
Vss
A6
Vcc
A5
A4
Vcc
/CE_UM2
/CE_UM1
DQ23
DQ16
DQ17
DQ18
DQ22
DQ21
DQ20
DQ19
Vcc
A14
A12
A7
Vcc
A8
A9
DQ24
DQ25
DQ26
/CE_UU2
/CE_UU1
DQ31
DQ30
DQ29
DQ28
DQ27
Vss
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
SIMM
TOP VIEW
M
1
HANBit Electronics Co.,Ltd.
HANBit
HMS1M32M8S
FUNCTIONAL BLOCK DIAGRAM
DQDQ
0-DQ31
0-31
A0-A19
A0-18
DQ 32
A20
A0-19
A0-19
DQ24-31
/WE
U1
/OE
DQ24-31
/WE
U5
/OE
/CE
/CE
/CE-UU2
/CE-UU1
A0-19
A0-19
DQ16-23
/WE
DQ16-23
/WE
U2
/OE
/CE
/CE
/CE-UM1
/CE-UM2
A0-19
A0-19
DQ 8-15
DQ 8-15
/WE
/WE
U3
/OE
/CE
/CE
/CE-LM2
A0-19
A0-19
/OE
U7
/OE
/CE-LM1
/WE
U6
/OE
DQ 0-7
/WE
/OE
DQ 0-7
/WE
U4
/WE
/OE
/OE
U8
/CE
/CE
/CE-LL1
/CE-LL2
TRUTH TABLE
MODE
/OE
/CE
/WE
DQ
POWER
STANDBY
X
H
X
HIGH-Z
STANDBY
NOT SELECTED
H
L
H
HIGH-Z
ACTIVE
READ
L
L
H
Q
ACTIVE
WRITE or ERASE
X
L
L
D
ACTIVE
2
HANBit Electronics Co.,Ltd.
HANBit
HMS1M32M8S
NOTE: X means don’t care
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
VIN,OUT
-0.5V to +7.0V
Voltage on Vcc Supply Relative to Vss
VCC
-0.5V to +7.0V
Power Dissipation
PD
8W
TSTG
-55oC to +125oC
Voltage on Any Pin Relative to Vss
Storage Temperature
Operating Temperature
TA
0oC to +70oC
Š Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated
in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
*
( TA=0 to 70 o C )
SYMBOL
MIN
TYP.
MAX
Supply Voltage
VCC
4.5V
5.0V
5.5V
Ground
VSS
0
0
0
Input High Voltage
VIH
2.2
-
Vcc+0.5V**
Input Low Voltage
VIL
-0.5*
-
0.8V
VIL(Min.) = -2.0V (Pulse Width ≤ 10ns) for I ≤ 20 mA
** VIH(Max.) = Vcc+2.0V (Pulse Width ≤ 10ns) for I ≤ 20 mA
DC AND OPERATING CHARACTERISTICS (1)
(0oC ≤ TA ≤ 70 oC ; Vcc = 5V ± 0.5V )
PARAMETER
Input Leakage Current
Output Leakage Current
TEST CONDITIONS
VIN = Vss to Vcc
/CE=VIH or /OE =VIH or /WE=VIL
VOUT=Vss to VCC
SYMBO
L
MIN
MAX
UNITS
ILI
-2
2
µA
IL0
-2
2
µA
2.4
-
V
0.4
V
Output High Voltage
IOH = -4.0mA
VOH
Output Low Voltage
IOL = 8.0mA
VOL
* Vcc=5.0V, Temp=25 oC
3
HANBit Electronics Co.,Ltd.
HANBit
HMS1M32M8S
DC AND OPERATING CHARACTERISTICS (2)
MAX
DESCRIPTION
TEST CONDITIONS
Min. Cycle, 100% Duty
/CE=VIL, VIN=VIH or VIL,
IOUT=0mA
Power Supply
Current: Operating
Power Supply
Current: Standby
SYMBOL
-15
-17
-20
UNIT
lCC
170
165
160
mA
Min. Cycle, /CE=VIH
lSB
50
50
50
mA
f=0MHZ, /CE≥VCC-0.2V,
VIN≥ VCC-0.2V or VIN≤0.2V
lSB1
10
10
10
mA
CAPACITANCE
DESCRIPTION
TEST CONDITIONS
SYMBOL
MAX
UNIT
Input /Output Capacitance
VI/O=0V
CI/O
8
pF
Input Capacitance
VIN=0V
CIN
7
pF
* NOTE : Capacitance is sampled and not 100% tested
AC CHARACTERISTICS (0oC ≤ TA ≤ 70 oC ; Vcc = 5V ± 0.5V, unless otherwise specified)
TEST CONDITIONS
PARAMETER
VALUE
Input Pulse Level
0.V to 3V
Input Rise and Fall Time
3ns
Input and Output Timing Reference Levels
1.5V
Output Load
See below
Output
Load
Output Load (B)
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
+5V
+5V
480Ω
DOUT
255Ω
30pF*
480Ω
DOUT
255Ω
5pF*
* Including scope and jig capacitance
4
HANBit Electronics Co.,Ltd.
HANBit
HMS1M32M8S
READ CYCLE
-15
PARAMETER
-17
-20
SYMBOL
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
Read Cycle Time
tRC
15
-
17
-
20
-
ns
Address Access Time
tAA
-
15
-
17
-
20
ns
Chip Select to Output
tCO
-
15
-
17
-
20
ns
Output Enable to Output
tOE
-
7
-
8
-
9
ns
Output Enable to Low-Z Output
tOLZ
0
-
0
-
0
-
ns
Chip Enable to Low-Z Output
tLZ
3
-
3
-
3
-
ns
Output Disable to High-Z Output
tOHZ
0
7
0
8
0
9
ns
Chip Disable to High-Z Output
tHZ
0
7
0
8
0
9
ns
Output Hold from Address Change
tOH
3
-
3
-
3
-
ns
Chip Select to Power Up Time
tPU
0
-
0
-
0
-
ns
Chip Select to Power Down Time
tPD
-
15
-
17
-
20
ns
WRITE CYCLE
-15
PARAMETER
-17
-20
SYMBOL
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
Write Cycle Time
tWC
15
-
17
-
20
-
ns
Chip Select to End of Write
tCW
12
-
13
-
14
-
ns
Address Set-up Time
tAS
0
-
0
-
0
-
ns
Address Valid to End of Write
tAW
12
-
13
-
14
-
ns
Write Pulse Width (/OE=High)
tWP
12
-
13
-
14
-
ns
Write Recovery Time (/OE=Low)
tWR
0
-
0
-
0
-
ns
Write to Output High-Z
tWZ
0
7
0
8
0
9
ns
Data to Write Time Overlap
tDW
8
-
9
-
10
-
ns
Data Hold from Write Time
tDH
0
-
0
-
0
-
ns
End of Write to Output Low-Z
tOW
3
-
3
-
3
-
ns
5
HANBit Electronics Co.,Ltd.
HANBit
HMS1M32M8S
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE (Address Controlled) ( /CE = /OE = VIL , /WE = VIH)
tRC
Address
tAA
tOH
Data out
Previous Data Valid
Data Valid
TIMING WAVEFORM OF READ CYCLE (/WE = VIH )
tRC
Address
tHZ(3,4)
tAA
tCO
/CE
tLZ(4)
tOHZ
tOE
/OE
tOH
tOLZ
Data Out
High-Z
Data Valid
Notes (Read Cycle)
1. /WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH
or VOL levels.
4. At any given temperature and voltage condition, tHZ (max.) is less than tLZ (min.) both for a given device and from device
to device.
6
HANBit Electronics Co.,Ltd.
HANBit
HMS1M32M8S
TIMING WAVEFORM OF WRITE CYCLE ( /WE Controlled )
tWC
Address
tAW
tWR(5)
/OE
tCW(3)
/CE
tAS(4)
tWP(2)
/WE
tDW
tDH
High-Z
Data In
Data Valid
tOHZ
Data Out
High-Z
TIMING WAVEFORM OF WRITE CYCLE ( /OE Low Fixed )
tWC
Address
tAW
tWR(5)
tCW(3)
/CE
tAS(4)
tOH
/WE
tWP(2)
tDW
Data In
tDH
High-Z
Data Valid
tWHZ(6,7)
tOW
(10)
(9)
High-Z(8)
Data Out
Notes( Write Cycle)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low /CE and a low /WE. A write begins at the latest transition among
/CE going low and /WE going low: A write ends at the earliest transition among /CE going high and /WE going high.
tWP is measured from the beginning of write to the end of write.
3. tCW is measured from the later of /CE going low to the end of write.
7
HANBit Electronics Co.,Ltd.
HANBit
HMS1M32M8S
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CE, or /WE going high.
6. If /OE,/CE and /WE are in the read mode during this period, the I/O pins are in the output low-Z state. Inputs of
opposite phase of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and
write cycle.
8. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain high impedance state.
9. DOUT is the read data of the new address.
10. When /CE is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output
should not be applied.
FUNCTIONAL DESCRIPTION
/CE
/WE
/OE
MODE
I/O PIN
SUPPLY CURRENT
H
X*
X
Not Select
High-Z
I SB, I SB1
L
H
H
Output Disable
High-Z
ICC
L
H
L
Read
DOUT
ICC
L
L
X
Write
DIN
ICC
Note: X means Don't Care
8
HANBit Electronics Co.,Ltd.
HANBit
HMS1M32M8S
PACKAGING DIMMENSIONS
SIMM Design
108.20 mm
3.18 mm
TYP(2x)
16 mm
6.35 mm
1
72
2.03 mm
1.02 mm
6.35 mm
1.27 mm
3.34 mm
95.25 mm
2.54 mm
0.25 mm MAX
MIN
Gold : 1.04±0.10 mm
1.27
1.29±0.08 mm
Solder : 0.914±0.10 mm
(Solder & Gold Plating Lead)
9
HANBit Electronics Co.,Ltd.
HANBit
HMS1M32M8S
ORDERING INFORMATION
1
2
3
HMS
4
5
6
7
8
1M 32 M8S-15
15ns Access Time
HANBit
Component, Customer
Memory
Modules
SIMM
x32bit
SRAM
1M
1. - Product Line Identifier
HANBit Technology --------------------------------------- H
2. - Memory Modules
3. - SRAM
4. - Depth : 1M
5. - Width : x 32bit
6. - Package Code
SIMM ------------------------------------------------------- M
ZIP
------------------------------------------------------- Z
7. - Number of Memory Components---8, Customer-----S
8. - Access time
10 ----------------------------------------------------------- 10ns
12 ----------------------------------------------------------- 12ns
15 ----------------------------------------------------------- 15ns
17 ----------------------------------------------------------- 17ns
20 ----------------------------------------------------------- 20ns
10
HANBit Electronics Co.,Ltd.