1.5 – 2.5 GHz LNA Switch PA Technical Data HPMX-3003 Features Plastic SSOP-28 Hewlett-Packard’s HPMX-3003 combines a Low Noise Amplifier, GaAs MMIC switch, and 27.5 dBm power amp in a single miniature 28 lead surface mount plastic package. This RFIC would typically serve as the “front end” and power stage of a battery operated wireless transceiver for PCS or ISM band use. Each section of the RFIC can also be used independently. H 30PMX YY 03 WW • GaAs MMIC LNA-SwitchPower Amp for 1.5 – 2.5 GHz Transceiver Use Description • LNA: 2.2 dB NF, 13 dB Ga @ 1.9 GHz 15 Antenna 17 Gnd 16 C2 18 SW2 19 Gnd 20 Gnd 22 PA out 21 PA out 23 Gnd 25 PA out 24 Gnd 26 Gnd • JEDEC Standard SSOP-28 Surface Mount Package Package Pin Configuration 27 VG2 • 3 or 5 V Operation 28 Gn • Power Amp: +4 dBm in, +27.5 dBm out, 23.5 dB Gain, 35% ηadd @ 1.9 GHz The single-supply LNA makes use of the low noise characteristics of GaAs to create a matched, broadband amplifier with target performance of 13 dB gain and 2.2 dB noise figure. The switch provides +55 dBm IP3 for linear operation. The power amplifier produces up to 820␣ mW with 35% power added efficiency. C1 14 • Switch: 55 dBm OIP @ 1.9␣ GHz The HPMX-3003 is fabricated with Hewlett-Packard’s GaAs MMIC process, and features a nominal 0.5 micron recessed Schottkybarrier-gate, gold metallization, and silicon nitride passivation to produce MMICs with superior performance, uniformity and reliability. Applications • Personal Communications Systems (PCS) Functional Block Diagram LNA in LNA out SW1 C1 Antenna C2 PA in (VG1) 5965-1403E SW2 PA out VD1 VG2 VD2 7-82 Gnd 12 SW1 13 LNA in 11 Gnd 6 VD1 7 LNA out 8 PA in 4 Gnd 5 Gnd 3 Gnd 2 Gnd 1 • 2400 MHz Wireless LANs and ISM Band Spread Spectrum Applications Gnd 9 • Cordless Telephone Systems Gnd 10 HPMX 3003 YYWW HPMX-3003 Absolute Maximum Ratings[1] Symbol Pdiss Pin Vd Vcont Tch TSTG Parameter Power Dissipation[2,3] CW RF Input Power Device Voltage Control Voltage Channel Temperature Storage Temperature Absolute Maximum[1] LNA 250[2,3] +20 8 — 175 -65 to 150 Units mW dBm V V °C °C Notes: 1. Operation of this device above any of these limits may cause permanent damage. 2. Tcase = 25°C 3. Derate at 18.2 mW/°C for TC > 78°C Absolute Maximum[1] Switch +33 — -6 175 -65 to 150 Absolute Maximum[1] Power Amp 1500[2,3] +20 8 — 175 -65 to 150 Thermal Resistance [2]: θjc = 55°C/W Recommended operating range of Vcc = 2.7 to 5.5 V, Ta = -40 to + 85 °C HPMX-3003 Standard Test Conditions Unless otherwise stated, all test data was taken on packaged parts under the following conditions: Ta= 25 °C, Zo = 50 Ω Vcc = +3.0 V DC, Vcontrol = -3.0 V DC, VD1 = +3.6 V DC LNA Pin = -20 dBm, PA Pin = +4 dBm, frequency = 1.9 GHz Perfomance cited is performance in test circuit shown in Figure 17. HPMX-3003 Guaranteed Electrical Specifications Standard test conditions apply unless otherwise noted. Symbol Parameters and Test Conditions Units Min. Typ. Max. Gtest Pout I d LNA LNA gain through switch Output power through switch LNA bias current dB dBm mA 9.0 24.0 11 25.5 6.5 9.5 7-83 HPMX-3003 Summary Characterization Information Standard test conditions apply unless otherwise noted. All information tested in 1900 MHz Test Circuit, and reflects performance of test circuit at 1900 MHz. Symbol LNA NF |S21|2 IRL ORL IIP3 Switch P1dB Parameters and Test Conditions Noise Figure 50 Ω Gain Input Return Loss Output Return Loss Input Third Order Intercept Output Power ∆C1 to C2 = 3 V where insertion loss is increased by 1 dB P1dB Output Power ∆C1 to C2 = 5 V where insertion loss is increased by 1 dB[1] IP3 Third Order Intercept S21 on Insertion Loss, on channel S21 off Isolation, off channel IRLon Return Loss, on channel IRLoff Return Loss, off channel Power amp (Vg = -.8 V required) GP Gain VD1 = 3.6 V, Pin = +4 dBm η PAadd Power Added Efficiency VD1 = 3.6 V Pout Id PA Output Power Transmit Current VD1 = 3.6 V, Pin = +4 dBm VD1 = 3.6 V, Pin = +4 dBm Units Typ dB dB dB dBm 2.2 13 15 12 -1 dBm +23 dBm +29 dBm dB dB dB dB +55 0.8 15 26 0.5 dB % 23.5 35 dBm mA +27.5 450 Note: 1. The P 1dB of the switch can be improved by increasing the difference between the values of C1 and C2 from the normal 3 V (+23 dB P1dB) to 5 V (+29 dB P1dB). HPMX-3003 Pin Description Gnd 1 28 Gn Gnd 2 27 VG2 Gnd 3 26 Gnd PA in 4 25 PA out Gnd 5 24 Gnd Gnd 6 23 Gnd VD1 7 22 PA out LNA out 8 21 PA out Gnd 9 20 Gnd Gnd 10 19 Gnd LNA in 11 18 SW2 Gnd 12 17 Gnd SW1 13 16 C2 C1 14 Figure 1. HPMX-3003 Pin Outs and Schematic. 15 Antenna 7-84 HPMX-3003 Pin Description Table No. Mnemonic Description Typical Signal Description 1 2 3 4 Gnd Gnd Gnd PA in ground ground ground input to Power Amplifier 0V 0V 0V DC: -0.75 V RF: +4 dBm Short path with minimal parasitics. Ground pins are also the primary thermal path for heatsinking the device. 5 6 Gnd Gnd ground ground 0V 0V Short path with minimal parasitics. Ground pins are also the primary thermal path for heatsinking the device. 7 VD1 Drain bias of PA stage 1 +3 V, 100 mA Set drain bias to 3 V (can be tied to same rail as PA out). Bypass with 100 pF capacitor at pin. 8 LNA out output of LNA DC: +3 V, 5 mA RF: -7 dBm 9 10 Gnd Gnd ground ground 0V 0V 11 LNA in input of LNA DC: 0 V RF: -20 dBm 12 Gnd ground 0V 13 SW1 switch terminal 1 DC: 0 V RF: -20 dBm 14 C1 switch control 1 15 Antenna 16 C2 switch center pole switch control 2 17 Gnd ground closed: 0 V open: -3 to -5 V DC: 0 V RF: +26 dBm closed: 0 V open: -3 to -5 V 0V 18 SW2 switch terminal 2 DC: 0 V RF: +4 dBm 19 20 Gnd Gnd ground ground 0V 0V 21 22 PA out PA out output of PA output of PA DC: 3 V, 350 mA RF: +27 dBm 23 24 Gnd Gnd ground ground 0V 0V 25 PA out output of PA DC: 3 V, 350 mA RF: +27 dBm 26 Gnd ground 0V 27 VG2 Gate bias on PA stage 2 -0.75 V 28 Gnd ground 0V Bias through 500 Ω resistor and 100 pF capacitor. 50 Ω transmission line with DC blocking capacitor (>24 pF) to input. Shunt 2.7 pF used on test board to match input at 1.9 GHz. Bias through 5 nH choke (printed on PC board) and 100 pF bypass capacitor to 10 Ω resistor and 1000 pF bypass capacitor. Can be operated from 3 to 5 V supply line. 50 Ω transmission line with DC block (>24 pF) to receiver. Short path with minimal parasitics. Ground pins are also the primary thermal path for heatsinking the device. 50 Ω transmission line from switch. Input blocking capacitor (24 pF) and shunt 5 nH inductor to ground (noise match at 1.9 GHz) required. Typically a filter is employed between the LNA input and the switch. Short path with minimal parasitics. Ground pins are also the primary thermal path for heatsinking the device. Switch input or output. Symmetrical with SW2. 50 Ω transmission line to LNA (or PA). Line should not carry DC voltage. High impedance line to control switch, used in conjunction with C2. C2 should be open when C1 is closed. 50 Ω transmisson line to/from antenna. Line should not carry DC voltage. High impedance line to control switch, used in conjunction with C1. C1 should be open when C2 is closed. Short path with minimal parasitics. Ground pins are also the primary thermal path for heatsinking the device. Switch input or output. Symmetrical with SW1. 50 Ω transmission line to PA (or LNA). Line should not carry DC voltage. Short path with minimal parasitics. Ground pins are also the primary thermal path for heatsinking the device. 2.7 pF chip capacitor to ground provides 1.9 GHz output match for PA. 50 Ω transmission line to switch. LC choke and blocking C used. Typically a filter is employed between the PA output and the switch input. Short path with minimal parasitics. Ground pins are also the primary thermal path for heatsinking the device. Leave unconnected; use pins 21 & 22 for PA out. Short path with minimal parasitics. Ground pins are also the primary thermal path for heatsinking the device. Provide bias through 10 Ω resistor. Bypass to ground at pin with 10 pF capacitor, and on power supply side of resistor with 1000␣ pF capacitor. Short path with minimal parasitics. Ground pins are also the primary thermal path for heatsinking the device. 7-85 HPMX-3003 Typical Performance Standard test conditions apply unless otherwise noted. 2.4 GHz performance is performance in test circuit shown in Figure 18. Some aspects of performance are determined by the test circuit impedances. 10 20 5 9 5 4 NOISE FIGURE (dB) 6 4 2400 MHz 15 7 1900 MHz GAIN (dB) CURRENT (mA) 8 10 3 5 2 3 2400 MHz 2 1900 MHz 1 1 0 2.5 3 3.5 4 4.5 5 5.5 0 2.5 6 3 3.5 4 4.5 5 5.5 0 2.5 6 3 3.5 VOLTAGE (V) VOLTAGE (V) Figure 2. LNA Current vs. Device Voltage at 1900 MHz. Figure 3. LNA Gain vs. Device Voltage and Frequency. 4.5 5 5.5 6 Figure 4. LNA Noise Figure vs. Device Voltage and Frequency. 20 8 4 VOLTAGE (V) 5 7 4 5 4 3 NOISE FIGURE (dB) 15 GAIN (dB) CURRENT (mA) 6 10 5 2 3 2 1 1 0 -60 -40 -20 0 20 40 60 0 -60 -40 -20 80 100 TEMPERATURE (°C) 0 20 40 60 0 -60 -40 -20 80 100 TEMPERATURE (°C) Figure 5. LNA Current vs. Temperature at 1900 MHz. Figure 6. LNA Gain vs. Temperature at 1900 MHz. 20 40 60 80 100 Figure 7. LNA Noise Figure vs. Temperature at 1900 MHz. 35 12 0 TEMPERATURE (°C) 50 1900 MHz 30 40 Stg 2 25 8 6 1900 MHz 2400 MHz PAE (%) Pout (dBm) CURRENT (mA) 10 20 15 30 20 10 2400 MHz 4 10 5 Stg 1 2 2.5 3 3.5 4 4.5 5 5.5 VOLTAGE (V) Figure 8. PA Current vs. Device Voltage at 1900 MHz. 6 0 2.5 3 3.5 4 4.5 5 5.5 6 VOLTAGE (V) Figure 9. PA Output Power vs. Supply Voltage and Frequency. 7-86 0 2.5 3 3.5 4 4.5 5 5.5 6 VOLTAGE (V) Figure 10. PA Power Added Efficiency vs. Supply Voltage and Frequency. HPMX-3003 Typical Performance, continued Standard test conditions apply unless otherwise noted. 2.4 GHz performance is performance in test circuit shown in Figure 18. Some aspects of performance are determined by the test circuit impedances. 400 35 30 Stg 2 40 250 200 150 25 PAE (%) 300 POWER (dBm) CURRENT (mA) 350 50 20 15 30 20 10 10 100 5 Stg 1 50 -60 -40 -20 0 20 40 60 0 -60 -40 -20 80 100 TEMPERATURE (°C) 20 40 60 0 -60 -40 -20 80 100 Figure 12. PA Output Power vs. Temperature at 1900 MHz and VD1 = 3.6V. 0 0 20 40 60 80 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 11. PA Current vs. Temperature at 1900 MHz and VD1 = 3.6 V. Figure 13. PA Power Added Efficiency vs. Temperature at 1900 MHz and VD1 = 3.6V. 0 0 -1 -1 -2 -2 -20 I.L. (dB) -10 R.L. (dB) ISOLATION/R.L. (dB) 0 -3 -3 -30 -4 -40 1.4 1.6 1.8 2.0 2.2 2.4 2.6 -5 1.4 -4 1.6 FREQUENCY (GHz) 1.8 2.0 2.2 2.4 -5 1.4 2.6 FREQUENCY (GHZ) Figure 14. Switch Isolation and “ON” State Return Loss vs. Frequency. 1.6 1.8 2.0 2.2 2.4 FREQUENCY (GHZ) Figure 15. Switch “OFF” State Return Loss vs. Frequency. Figure 16. Switch “ON” State Insertion Loss vs. Frequency. HPMX-3003 Typical Scattering Parameters for the LNA, Common Source, ZO = 50 Ω, VD = 3 V, ID = 5 mA Frequency S11 S21 S12 S22 GHz Mag Ang Mag Ang Mag Ang Mag Ang 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 0.97 0.96 0.95 0.94 0.92 0.90 0.88 0.85 0.82 0.78 0.75 -27 -33 -40 -47 -54 -62 -70 -79 -89 -99 -110 2.00 2.06 2.13 2.20 2.28 2.36 2.45 2.54 2.63 2.71 2.79 158 150 142 134 125 117 109 100 90 81 71 0.035 0.036 0.037 0.038 0.038 0.039 0.039 0.040 0.042 0.045 0.050 -12 -17 -23 -30 -39 -49 -62 -77 -95 -115 -135 0.91 0.91 0.90 0.88 0.87 0.86 0.84 0.83 0.81 0.79 0.78 -22 -27 -31 -36 -41 -46 -50 -55 -60 -65 -71 7-87 2.6 30 pF 10 PA in VG2 ~ – 0.75V 100 pF 10 pF 2.7 pF 1000 pF 30 pF VG1 ~ – 0.75V 500 VD1 = 3.6V VD2 = 3.6V 2.7 pF 100 pF 18 nH PA out 30 pF 30 pF LNA out 3.0V 1000 pF 5 nH 10 100 pF SW2 LNA in C2 5 nH Antenna SW1 C1 Figure 17. HPMX-3003 Test Circuit (1900 MHz). 30 pF 10 PA in VG2 ~ – 0.75V 100 pF 10 pF 1.5 pF 1000 pF 30 pF VG1 ~ – 0.75V 500 VD1 = 3.6V VD2 = 3.6V 1.5 pF 100 pF 18 nH PA out 30 pF 30 pF LNA out 3.0V 1000 pF 10 2.5 nH 100 pF SW2 LNA in C2 2.5 nH Antenna SW1 C1 Figure 18. HPMX-3003 Test Circuit (2400 MHz). 7-88 JEDEC Standard SSOP-28 Package Outline Drawing 8.255 (0.325) 6.000 (0.236) TYPICAL DIMENSIONS ARE IN MILLIMETERS (INCHES) 3.850 (0.152) MEETS JEDEC OUTLINE DIMENSIONS 10.000 (0.394) 1.400 (0.055) 0.635 (0.025) 0.185 (0.007) 0.600 (0.024) 0.250 (0.010) Part Number Ordering Information Part Number HPMX-3003-TR1 HPMX-3003-BLK No. of Devices 1000 25 Container Tape and Reel Tape 7-89