AGILENT HPMX-5001-TY1

1.5 – 2.5 GHz Upconverter/
Downconverter
Technical Data
HPMX-5001
Plastic TQFP-32 Package
Features
• 2.7 V Single Supply Voltage
• Low Power Consumption
(60␣ mA in Transmit Mode,
39 mA in Receive Mode
Typical)
• 2 dBm Typical Transmit
Power at 1900 MHz
• Half-Frequency VCO with
Frequency Doubler
• 32/33 Dual-Modulus
Prescaler
• Flexible Chip Biasing,
Including Standby Mode
• TQFP-32 Surface Mount
Package
• Operation to 2.5 GHz
H
-5001
HPMX
W
W
YY
ZZZ
XXXX
Pin Configuration
32
25
1
24
H
HPMX-5001
YYWW
• Use with Companion
HPMX-5002 IF chip
XXXX
Applications
ZZZ
8
• DECT, UPCS and ISM Band
Handsets and Basestations
17
9
16
Functional Block Diagram
POWER DOWN
CONTROL
RX IF OUT
RX RF IN
EXT.
VCO
TANK
X2
TX RF OUT
RATIO
SELECT
32/33
TX IF IN
5965-9105E
PRESCALER
OUT
7-90
General Description
The HPMX-5001 Upconverter/
Downconverter provides RF
system designers with all of the
necessary features to perform an
RF-to-IF downconversion for a
receive path, as well as an IF-toRF upconversion for transmit
mode.
Designed to meet the unique
needs of portable applications,
the HPMX-5001 combines the
qualities of flexible chip biasing,
low power consumption, and true
2.7 V minimum supply voltage
operation to provide superior
performance and battery life. By
incorporating the active elements
of the VCO on-chip, as well as a
32/33 dual-modulus prescaler,
overall system component count
and costs are decreased. The
32-TQFP package insures that
this high level of integration
occupies a small amount of
printed circuit board space.
The HPMX-5001 can be used in
either dual-conversion systems
(with the HPMX-5002 IF
Demodulator/Modulator) or
single-conversion systems. The
HPMX-5001 is manufactured
using Hewlett-Packard’s HP-25
Silicon Bipolar Process with
25␣ GHz f T and 30 GHz fMax.
HPMX-5001 Absolute Maximum Ratings[1]
Parameter
VCC Supply Voltage
Voltage at Any Pin[4]
Power Dissipation[2,3]
RF Input Power
Junction Temperature
Storage Temperature
Min.
-0.2 V
-0.2 V
-55°C
Max.
8V
VCC + 0.2 V
600 mW
15 dBm
+150°C
+125°C
Thermal Resistance[2]:
θjc = 100°C/W
Notes:
1. Operation of this device in excess of
any of these parameters may cause
permanent damage.
2. TCASE = 25°C.
3. Derate at 10 mW/°C for TCASE > 90°C.
4. Except CMOS logic inputs – see
Summary Characterization Information
table.
HPMX-5001 Guaranteed Electrical Specifications
Unless otherwise noted, all parameters are guaranteed under the following conditions: VCC = 3.0 V. Test
results are based upon use of networks shown in test board schematic diagram (see Figure 28). Typical
values are for VCC = 3.0 V, TA = 25°C.
Symbol
GC
Pout
ICC
VDIV
Parameters and Test Conditions
Receive Conversion Gain[1]
Transmitter Power Output
Input[2]
2:1 output VSWR
Device Supply Current
Transmit Mode
Receive Mode
Synth Mode
Standby Mode (with DIVMC Set High)
DIV Single-Ended Swing[3]
Units
dB
Min.
12
Typ.
14
dBm
mA
mA
mA
µA
VPP
0
2
64
43
15
1
1
0.7
Max.
80
54
19
50
Notes:
1. 50 Ω RF source, 100 MHz < IF < 300 MHz, 1.89 GHz RF. There is a 750 Ω resistor on chip between RXIF and RXIFB (pins 3 and 4). A
matching network from 750 Ω to 50 Ω is used for this measurement. Insertion loss of the matching network is included in the net
conversion gain figure. See Figure 28.
2. Signal injected into P3 in Figure 28 is -12.5 dBm.
3. DIV output AC coupled into a 2 kΩ || 10 pF load. See test board schematic diagram, Figure 28.
7-91
HPMX-5001 Summary Characterization Information
Typical values measured on test board shown in Figure 28 at VCC = 3.0 V, TA = 25°C, RXIF = 110.592 MHz,
TXRF = 1.89 GHz, unless otherwise noted.
Symbol
VIH
VIL
IIH
IIL
ts
th
tpd
Receive Mode
Gc
NF
IIP3
IP1dB
Parameters and Test Conditions
CMOS Input High Voltage (Can Be Pulled
up as High as VCC + 7 V)[1]
CMOS Input Low Voltage
CMOS Input High Current
CMOS Input Low Current
DIVMC Setup Time[2,8]
DIVMC Hold Time[2,8]
DIV Propagation Delay[2,8]
Mode Switching Time[3]
Units
V
Receive Conversion Gain [9]
Noise Figure[4]
Input Third Order Intercept Point
Input 1 dB Gain Compression Point
LO Leakage (2 x fVCO) at IF Port
Input VSWR[5]
dB
dB
dBm
dBm
dBm
VSWRin
Transmit Mode[6]
PIM 3
Power Output Level for >35 dB IM3 Suppression[10]
OP1dB
Output 1 dB Gain Compression Point
VSWRout
Output VSWR
LO Suppression (2 x fVCO)
F3dBIF
IF 3 dB Bandwidth
Transmitter C/N @ 2 x fVCO + 4 MHz[11]
Synth Mode
1LO Frequency Range[7]
V
µA
µA
ns
ns
ns
µs
dBm
dBm
Typical
≥ VCC - 0.8
≤ VCC - 1.9
<10
>-300
4
0
<7
<1
1.89 GHz 2.45 GHz
14
13.5
10
10
-8
-9
-18
-18
-57
—
1.3:1
1.3:1
dBc
MHz
dBc/Hz
—
0
1.8:1
25
500
+137
MHz
750-1200
-5
0
1.8:1
30
500
+134
Notes:
1. All CMOS logic inputs are internally pulled up to logic high level.
2. See Figure 2 for detailed timing diagram.
3. Between any two different biasing modes. This switching time does not include PLL lock-up time.
4. Single sideband noise figure.
5. In modes other than receive, the VSWR may be as high as 10:1.
6. Single-ended 50 Ω RF load, 300 Ω series IF terminations (600 Ω differential), 100 MHz < IF < 300 MHz, 1.89 GHz RF.
7. The LO is followed by a frequency doubler which raises the LO range to 1500-2400 MHz.
8. DIV output AC coupled into a 2 kΩ || 10 pF load. See test diagram, Figure 28.
9. 50 Ω RF source, 110 MHz < IF < 300 MHz, 1.89 GHz or 2.45 GHz RF. There is a 750 Ω resistor on chip between RXIF and RXIFB
(pins 3 and 4). A matching network from 750 Ω to 50␣ Ω is used for this measurement. Insertion loss of the matching network is
included in the net conversion gain figure.
10. PIM3 is the maximum SSB output power for at least 35 dB IM3 spur suppression.
11. Measured at saturated output power for 1.89 GHz. Measured at -5 dBm SSB output power for 2.45␣ GHz.
7-92
Table 1 - HPMX-5001 Pin Description
No.
1
3
Mnemonic
TXCTRL
RXIFB
I/O Type
CMOS I/P
Analog O/P
4
RXIF
Analog O/P
5
6
7
8
10
11, 15
12
TXIF
TXIFB
LNAREF
RXRF
TXRXVCC
TXRXGND
TXRFB
Analog I/P
Analog I/P
Analog DC I/P
Analog I/P
DC Supply
Ground
Analog O/P
14
TXRF
Analog O/P
16
17
20
21
22
23
26
27
28
30
31
32
2, 9, 13,
18,19,24,
25, 29
DBLVCC
DBLGND
VCOTNKS
VCOTNKF
VCOVCC
VCOGND
DIVVCC
DIVGND
DIV
DIVMC
LOCTRL
RXCTRL
VSUB
DC Supply
Ground
Analog I/P
Analog O/P
DC Supply
Ground
DC Supply
Ground
Analog O/P
CMOS I/P
CMOS I/P
CMOS I/P
Ground
Description
Controls biasing of transmit mixer, amplifiers, and doubler
Inverted single-ended downconverted receiver output,
normally tied to VCC (internal 750 Ω resistor connects to RXIF)
Single-ended downconverted receiver output, drives SAW
filter (internal 750 Ω resistor connects to RXIFB)
Transmit non-inverting IF input
Transmit inverting IF input
Reference input for receive input amplifier
Receive RF input
Supply voltage for transmit path, receive front-end and mixer
Ground for transmit path, receive front-end and mixer
Inverting output of transmit path (see test diagram for
matching network)
Non-inverting output of transmit path (see test diagram for
matching network)
Supply voltage for LO frequency doubler
Ground for LO frequency doubler
Sense line from external tank circuit to on-chip VCO amplifier
Force line from on-chip VCO amplifier to external tank circuit
Supply voltage for on-chip VCO amplifier
Ground for on-chip VCO amplifier
Supply voltage for 32/33 dual-modulus prescaler
Ground for 32/33 dual-modulus prescaler
Output from 32/33 dual-modulus prescaler
Modulus control signal for 32/33 dual-modulus prescaler
Controls biasing for VCO and 32/33 dual modulus prescaler
Controls biasing for receive mixer, amplifiers, and doubler
Substrate bias voltage
Table 2 - HPMX-5001 Mode Control
(CMOS Logic Levels - all pins internally pulled up to high level)
Mode
Transmit
Receive
Synth
Standby
TXCTRL
0
1
1
1
RXCTRL
1
0
1
1
LOCTRL
0
0
0
1
7-93
31
32
1
2
16
17
18
19
32
33
1
2
19
32
1
2
3
VCO
DIV
DIVMC
DIVIDE BY 33 (DIVMC = 0)
31
33
1
2
16
17
18
VCO
tpd
DIV
DIVMC
ts
th
DIVIDE BY 32 (DIVMC = 1)
Figure 2. HPMX-5001 Prescaler Timing Diagram.
TX PA
CERAMIC
TX
FILTER
TX IF INPUT
LO1
X2
T/R
TANK
FRONT-END
RF FILTER
RX LNA
32/33
CERAMIC
IMAGE
FILTER
HPMX-5001
RX IF FILTER
RX IF OUTPUT
Figure 3. HPMX-5001 Block Diagram/Typical Application.
7-94
˜ 30 MHz
SYNTHESIZER
REFERENCE
OSCILLATOR
TX PA
CERAMIC
TX.
FILTER
10.368 MHz
REFERENCE
OSCILLATOR
LO1 ˜ 900 MHz
X2
T/R
TANK
FRONT-END
RF FILTER
RX LNA
˜ 30 MHz
SYNTHESIZER
32/33
CERAMIC
IMAGE
FILTER
HPMX-5001
IF1 = 110.592 MHz
SAW CHANNEL FILTER
IF2 = 6.912 MHz
LC FILTER
LC FILTER
DATA
FILTER
CHARGE
PUMP
DATA
SLICER
RX DATA
RSSI
ø FREQ.
DET.
90/216
CHARGE
PUMP
TANK
9/12/16
LOCK
DET.
RC FILTER
LO2 = 103.68 MHz
TX DATA
LC FILTER
Figure 4. Typical HPMX-5001 Application with HPMX-5002 IF Chip. All Other Connections Go to Burst Mode Controller,
Power Source, or Ground.
VCC = 5.5 V
8
6
VCC = 3.0 V
4
2
VCC = 2.7 V
-15
5
25
45
65
TEMPERATURE (°C)
Figure 5. ICC in Standby Mode vs.
Temperature and VCC.
85
46
ICC SYNTHESIZER MODE (mA)
10
0
-55 -35
17
48
ICC RECEIVE MODE (mA)
ICC STANDBY MODE (µA)
12
VCC = 5.5 V
44
VCC = 3.0 V
42
VCC = 2.7 V
40
38
36
-55 -35
-15
5
25
45
65
TEMPERATURE (°C)
Figure 6. ICC in Receive Mode vs.
Temperature and VCC.
7-95
85
16
VCC = 5.5 V
VCC = 3.0 V
15
VCC = 2.7 V
14
13
-55 -35
-15
5
25
45
65
85
TEMPERATURE (°C)
Figure 7. ICC in Synthesizer Mode vs.
Temperature and VCC.
65
VCC = 3.0 V
VCC = 2.7 V
60
2.0
2.0
1.8
1.8
1.6
1.4
VCC = 2.7 V
1.2
1.4
VCC = 2.7 V
1.2
5
25
45
65
85
45
65
85
0
RECEIVE MIXER (dBm)
VCC = 5.5 V
VCC = 2.7 V
8
6
4
2
-15
5
25
45
65
-5
-10
P1dB
-20
0
-10
-20
-30
-40
VCC = 5.5 V
-50
VCC = 2.7 V
-60
25
45
25
5
45
65
85
65
85
TEMPERATURE (°C)
Figure 14. 2 x fLO Leakage at Receive
Downconverter Output vs.
Temperature and VCC.
45
65
85
14.5
VCC = 2.7 V
14.0
13.5
VCC = 5.5 V
13.0
12.5
12.0
-55 -35
-15
5
25
45
65
85
TEMPERATURE (°C)
Figure 12. Receive Downconverter
Input Third Order Intercept Point
and Output 1 dB Compression Point
vs. Temperature and VCC.
TRANSMIT 2 x fLO SUPPRESSION (dBc)
Figure 11. Receive Downconverter
SSB Noise Figure vs. Temperature
and VCC.
5
-15
25
15.0
TEMPERATURE (°C)
TEMPERATURE (°C)
-15
VCC = 5.5 V
-15
-25
-55 -35
85
VCC = 2.7 V
INPUT IP3
5
Figure 10. Receive Downconverter
Output VSWR vs. Temperature and
VCC.
Figure 13. Receive Downconverter
Conversion Gain vs. Temperature and
VCC.
3.0
40
35
30
VCC = 2.7 V
25
TXRF VSWR (OUTPUT)
10
-15
TEMPERATURE (°C)
Figure 9. Receive Downconverter
Input VSWR vs. Temperature and VCC.
12
-70
-55 -35
25
TEMPERATURE (°C)
Figure 8. ICC in Transmit Mode vs.
Temperature and VCC.
0
-55 -35
5
-15
VCC = 5.5 V
1.0
-55 -35
RECEIVE MIXER CONVERSION GAIN (dB)
-15
1.0
-55 -35
TEMPERATURE (°C)
RECEIVE MIXER SSB NOISE FIGURE (dB)
1.6
VCC = 5.5 V
55
-55 -35
2 x fLO LEAKAGE (dBm)
RXRF VSWR (OUTPUT)
VCC = 5.5 V
RXRF VSWR (INPUT)
ICC TRANSMIT MODE (mA)
70
VCC = 5.5 V
20
15
10
2.6
2.2
VCC = 2.7 V
1.8
VCC = 5.5 V
1.4
5
0
-55 -35
-15
5
25
45
65
TEMPERATURE (°C)
Figure 15. 2 x fLO Suppression at
Transmit Upconverter Output vs.
Temperature and VCC.
7-96
85
1.0
-55 -35
-15
5
25
45
65
TEMPERATURE (°C)
Figure 16. Transmit Upconverter
Output VSWR vs. Temperature and
VCC.
85
VCC = 5.5 V
137.0
VCC = 2.7 V
136.5
136.0
135.5
135.0
-55 -35
-15
5
25
45
65
VCC = 5.5 V
2.0
1.0
0
P1dB
VCC = 2.7 V
-1.0
TEMPERATURE (°C)
-15
5
25
45
65
TEMPERATURE (°C)
Figure 17. Carrier to Noise Ratio at
Transmit Upconverter Output vs.
Temperature and VCC.
Figure 18. Transmit Upconverter
Power Output and Output 1 dB
Compression Point vs. Temperature
and VCC.
DIVVCC
PIN 26
RECOMMENDED
OUTPUT CIRCUIT
C = 2.2 nF, R = 51
PIN 28
DIV o/p
C
1.00
VCC = 5.5 V
VCC = 2.7 V
0.95
0.90
-2.0
-3.0
-55 -35
85
VCC = 3.0 V
POUT
DIV OUTPUT (Vp-p)
137.5
TRANSMIT MIXER (dBm)
TRANSMIT CARRIER TO NOISE RATIO (dB)
1.05
3.0
138.0
R
MAX. LOAD
C = 10 pf, R = 2k
PIN 27
DIVGND
Figure 20. Equivalent Circuit and Recommended Output and Load Circuits for
the HPMX-5001 Prescaler Output.
7-97
85
0.85
-55 -35
-15
5
25
45
65
85
TEMPERATURE (°C)
Figure 19. Prescaler Output Voltage
vs. Temperature and VCC.
DIVVCC
PIN 26
PIN 30
DIVMC i/p
LOW = 1/33
OPEN OR VCC = 1/32
PIN 27
DIVGND
Figure 21. Equivalent Circuit for the Divider Modulus Control.
VCOVCC , PIN 22
TO USE WITH INJECTED LO SIGNAL,
DRIVE PIN 20 (VCOTNKS) WITH
630 m Vp-p.
LEAVE PIN 21 (VCOTNKF) FLOATING
AS SHOWN BELOW.
C = 22 p MAX. FOR MINIMAL
TURN ON DELAYS.
7k
PIN 20
20
PIN 21
OPTIONAL
FOR SWR
21
VCOGND, PIN 23
Figure 22. Equivalent Circuit for VCO Tank Connection and Recommended
Tank Circuit.
VCC
ALL LOGIC CONTROL
PINS ARE ACTIVE LOW.
OPEN OR VCC =
NOT ACTIVE.
TXCTRL, PIN 1
LOCTRL, PIN 31
RXCTRL, PIN 32
GND
Figure 23. Equivalent Circuit for Logic Control Pin 1, 31, and 32.
7-98
TXRX VCC
10
BIAS
TO MIXER
RXRF
50 Ω i/p
2.7 pF
BIAS
8
LNAREF
7
11
3.3 pF
LNA STAGE
PCB GND
15
EXTERNAL COMPONENTS
ARE FOR TYPICAL i/p SWR
OF 1.3:1 OVER 1.85
TO 2.55 GHz
TXRX GND
Figure 24. Equivalent Circuit for RXRF Input.
TXRX VCC
10
RECOMMENDED DRIVE
LEVEL IS 300 mV pk-pk.
10 k
TXIF IN
10 k
TXIF 5
TXIFB 6
USE d.c. BLOCKING Cs TO
AVOID CHANGING d.c. BIAS
CONDITIONS. 22 pF MAX. FOR
QUICK TURN ON.
TX i/p STAGE
11/15
TXRX GND
Figure 25. Equivalent Circuit for TXIF Input.
VCC
3 RXIFB
120 nH
750
4 RXIF
6.8 pF
8.2 pF
50 Ω o/p
LO
EXTERNAL COMPONENTS
SHOWN ARE FOR 110.592 MHz
I.F. AND TYPICAL 50 Ω o/p
SWR OF 1.3:1
RF
11/15
TXRX GND
Figure 26. Equivalent Circuit for the RXIF Output and Recommended Matching
Circuit for 110.592 MHz IF.
7-99
VCC
3.3 nH
12
50
TXRFB
300
3.3 nH
14
50 Ω o/p
TXRF
22 pF
EXAMPLE o/p NETWORK FOR
1.88–1.90 GHz.
OTHER SYMMETRIC NETWORKS
WILL ENABLE OPERATION
UP TO 2.50 GHz.
11/15
TXRX GND
TX o/p STAGE
Figure 27. Equivalent Circuit for TXRF Output and Matching Network for
DECT Phone Operation.
P9
P8
R8
R7
C11
R9
P7
R5
C10
C9
P10
C12
32
25
24
1
R10
P1
C13
C1
+ 32/33
L1
C2
RXIF
R4
C3
X2
TXIF
R6
VCOTNKS
T1
C4
C8
R1
C5
RXRF
C6
8
17
16
9
VCC
Ground
X3
R2
L2
C7
TXRF
L3
Figure 28. Test Board Schematic Diagram. All I/O Labels Correspond to Those on the Test board. See Table 3 for
Component Values.
7-100
Table 3. Test Board Components Shown in Figure 28.
Functional Description
Note: Required VCC decoupling capacitors are not shown on the
schematic. Detailed schematic and board layout are available in
Application Note 1081.
A typical DECT application of the
HPMX-5001 in a dual-conversion
superheterodyne radio transceiver is shown in Figure 3. The
HPMX-5001 is designed to
provide four different modes of
operation:
Component Label
R1
R2, R4, R5
X3
R6
R7, R8, R9, R10
C1
C2
C3, C4, C10, C11, C12, C13
C5
C6
C7
C8
C9
L1
L2, L3
T1
Value (Size)
270 (0805)
51.1 (0805)
R = 300 (0805) for 1.89 GHz,
L = 3.3 nH for 2.45 GHz
20 (0805)
1100 (0805)
see Table 4
see Table 4
1 nF (0805 or 0504)
3.3 pF (0504 or 0603)
2.7 pF (0805)
22 pF (0805) for 1.89 GHz,
3.3 pF for 2.45 GHz
12 pF (0805 or 0504)
2.2 nF (0805)
see Table 4
3.3 nH (0805)
1:4 Balun T4-1-X65
Table 4. Component changes for dfferent IF frequencies.
IF Frequency
110 MHz
200 MHz
250 MHz
300 MHz
350 MHz
C1, pF
6.8
1.0
1.2
1.2
2.7
C2, pF
8.2
3.9
3.9
3.9
2.7
L1, nH
120
100
56
39
27
7-101
VSWR
1.3:1
1.3:1
1.3:1
1.3:1
1.3:1
• Transmit, where the VCO,
doubler, upconverting mixer,
associated buffers, and
prescaler are enabled
• Receive, where the VCO,
doubler, downconverting
mixer, associated buffers, and
prescaler are enabled
• Synthesizer, where only the
VCO and prescaler are active
• Standby, where all circuits are
disabled
These four modes are controlled
via a three wire interface,
TXCTRL, RXCTRL, and LOCTRL.
Figure 1 shows the programming
logic states for all four modes.
The detailed description of the
three active modes is given
below.
Transmit Mode
For transmit upconversion, a
differential narrow-band
modulated signal is AC-coupled
into the TXIF and TXIFB inputs.
The differential signal may be
generated by the HPMX-5002 IF
Demodulator/Modulator. Once
on-chip, the signal is buffered and
applied to a double-balanced
Gilbert cell mixer. The
upconverted RF signal is then
amplified to generate a -0.6 dBm
single-ended, single-sideband
power signal at the 1 dB
compression point. The RF
outputs, TXRF and TXRFB, are
open-collector outputs (see test
diagram Figure 28 for recommended matching network). The
TXRF output is AC-coupled into a
50 Ω transmit filter. This signal is
then filtered and amplified offchip by an external power amplifier before it is switched into the
antenna. The HPMX-5001 may
also be used in DECT systems
which utilize direct modulation of
the 1LO for data transmission. In
this case, either the TXIF or
TXIFB input, but not both, must
be tied to VCC to cause the
upconverting mixer to act as a
buffer stage.
Receive Mode
In receive mode, a preamplified
RF signal is passed through an
image filter and applied as a
single-ended signal to the 50 Ω
RXRF input. Use of a 2.7 pF
blocking capacitor is recommended. RXRF is the noninverting input of the RF input
amplifier. The inverting input of
this amplifier, LNAREF, is selfbiased and requires only an
external capacitor (recommended
value of 3.3 pF) to ground. The
receive downconversion mixer
also employs a double-balanced
Gilbert cell configuration. The
production version of the
HPMX-5001 will have two
equivalent open collector outputs.
The HPMX-5001 can operate at IF
frequencies up to 300 MHz (see
Figure 28 for recommended
matching network).
Synthesizer Mode
The on-chip 32/33 dual-modulus
prescaler, in conjunction with the
VCO, external tank circuit, and
CMOS synthesizer, form a phaselocked loop (PLL). The prescaler
divider output and modulus
control input are designed to be
compatible with positive-edge
7-102
triggered CMOS synthesizers
from a variety of vendors. The
timing requirements for the
prescaler are shown in Figure 2.
It is important to note that the
prescaler divides the VCO signal,
and not the frequency doubler
output. Local oscillator (LO)
signal generation on the
HPMX-5001 is accomplished
through the combination of a
VCO and frequency doubler. The
VCO is a simple Clapp oscillator
for the best possible noise
performance. The VCO force and
sense pins (VCOTNKF,
VCOTNKS) are self-biased, so
that the connections to the tank
(minimum Q of 20) are through
AC-coupling capacitors.
VCOTNKS can also be used with
an injected LO. VCOTNKF would
then be left floating. The doubler
circuit multiplies the VCO
frequency by two. This enables
the VCO to have lower sensitivity
to both package parasitics and LO
re-radiation. Separate bias pins
and buffering are utilized to
minimize pulling of the VCO
when the chip is switched from
synthesizer to transmit or receive
mode.
Part Number Ordering Information
Part Number
HPMX-5001-STR
HPMX-5001-TR1
HPMX-5001-TY1
No. of Devices
10
1000
250
Container
Strip
Tape and Reel
Tray
Package Dimensions 32 Pin Thin Quad Flat Package
All dimensions shown in mm.
9.0 ± 0.25
7.0 ± 0.1
9.0 ± 0.25
HPMX-5001
YYWW
XXXX
0.35
TYP.
7.0 ± 0.1
ZZZ
0.8
1.4 ± 0.05
0.6
+ 0.15
- 0.10
0.05 MIN., 0.1 MAX.
7-103
Tape Dimensions and Product Orientation for Outline TQFP-32
REEL
CARRIER
TAPE
USER
FEED
DIRECTION
COVER TAPE
2.0 (See Note 7)
0.30 ± 0.05
1.5+0.1/-0.0 DIA
4.0 (See Note 2)
1.75
R 0.5 (2)
HPMX-5001
1.6 (2)
BO
5.0
K1
KO
7.5 (See Note 7)
6.4 (2)
AO
12.0
1.5 Min.
Cover tape width = 13.3 ± 0.1 mm
Cover tape thickness = 0.051 mm (0.002 inch)
AO = 9.3 mm
BO = 9.3 mm
KO = 2.2 mm
K1 = 1.6 mm
NOTES:
1. Dimensions are in millimeters
2. 10 sprocket hole pitch cumulative tolerance ±0.2
3. Chamber not to exceed 1 mm in 100 mm
4. Material: black conductive Advantek™ polystyrene
5. AO and BO measured on a plane 0.3 mm above the bottom of the pocket.
6. KO measured from a plane on the inside bottom of the pocket to the top surface of the carrier.
7. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole.
7-104
16.0 ± 0.3