HANBit HSD16M32F4VP Synchronous DRAM Module, 64Mbyte ( 16M x 32-Bit ) SMM based on 2Mx16Bitx4Banks, 4K Ref., 3.3V Part No. HSD16M32F4VP GENERAL DESCRIPTION The HSD16M32F4VP is a 16M x 32 bit Synchronous Dynamic RAM high density memory module. The module consists of four CMOS 2M x 16 bit with 4banks Synchronous DRAMs in TSOP-II packages is mounted on a 80-pin, single-sided, FR-4-printed circuit board., Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD16M32F4VP is a SMM (Stackable Memory Module) designed and is intended for mounting into two 40pin connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible. PIN ASSIGNMENT FEATURES • Part Identification HSD16M32F4VP-10L 40-PIN P1 Connector 40-PIN P2 Connector PIN Symbol PIN Symbol PIN Symbol PIN Symbol 1 Vcc 21 Vcc 1 Vcc 21 Vcc 2 /RAS 22 DQ0 2 DQ31 22 BA0 • LVTTL compatible inputs and outputs 3 /CAS 23 DQ1 3 DQ30 23 BA1 • Single 3.3V ±0.3V power supply 4 NC 24 DQ2 4 DQ29 24 NC 5 CLKA 25 DQ3 5 DQ28 25 NC 6 NC 26 DQ4 6 DQ27 26 A11 7 Vss 27 Vss 7 Vss 27 Vss 8 NC 28 DQ5 8 DQ26 28 A10 9 CKE0 29 DQ6 9 DQ25 29 A9 10 /CS0 30 DQ7 10 DQ24 30 A8 11 /CS1 31 DQ8 11 DQ23 31 A7 - HSD8M32F4VP 12 NC 32 DQ9 12 DQ22 32 A6 - HSD16M32F4VP 13 NC 33 DQ10 13 DQ21 33 A5 14 Vss 34 Vss 14 Vss 34 Vss 15 /WE 35 DQ11 15 DQ20 35 A4 16 DQM0 36 DQ12 16 DQ19 36 A3 17 DQM1 37 DQ13 17 DQ18 37 A2 18 DQM2 38 DQ14 18 DQ17 38 A1 19 DQM3 39 DQ15 19 DQ16 39 A0 20 Vcc 40 Vcc 20 Vcc 40 Vcc • Burst mode operation • Auto & self refresh capability (4096 Cycles/64ms) • MRS cycle with address key programs - Latency (Access from column address) - Burst length (1, 2, 4, 8 & Full page) - Data scramble (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock • 80pin-SMM type FR4-PCB design • The used device is 2Mx16Bitx4Bankst SDRAM • Pin assignment is compatible with - HSD32M32F4VP Stackable Memory Module TOP VIEW URL: www.hbe.co.kr REV 1.0 (August.2002) HANBit Electronics Co.,Ltd. 9 HANBit HSD16M32F4VP FUNCTIONAL BLOCK DIAGRAM DQ0-31 CKE CAS 15 CKE0 /CA /RAS S U1 RAS /CS0 CE WE CKE CAS U2 RAS CE WE CKE CAS CE A0-A11 U3 RAS /CS A0-A11 WE A0-A11 CLK DQ0LDQM UDQ CLKA DQM0 DQM1 BA0-1 M CLK DQ16-31 LDQM UDQ BA0-1 M CLK DQ0-15 LDQM UDQM BA0-1 DQM2 DQM 3 DQM0 DQM 1 1 CKE CAS U4 RAS CE WE /WE A0 - A11 BA0-1 Vcc A0-A11 CLK DQ16-31 LDQ UDQ BA0-1 M M DQM2 DQM3 Two 0.1uF Capacitors per each SDRAM Vss URL: www.hbe.co.kr REV 1.0 (August.2002) HANBit Electronics Co.,Ltd. 9 HANBit HSD16M32F4VP PIN FUNCTION DESCRIPTION Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs. /CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. A0 ~ A11 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA9 BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. /RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. /CAS /WE Column address Latches column addresses on the positive going edge of the CLK with CAS low. strobe Enables column access. Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQM0 ~3 Data input/output Makes data output Hi-Z, tSHZ after the clock and masks the output. mask Blocks data input when DQM active. (Byte masking) DQ0 ~ 31 Data input/output Data inputs/outputs are multiplexed on the same pins. VCC/VSS Power Power and ground for the input buffers and the core logic. supply/ground ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING VIN ,OUT -1V to 4.6V Voltage on Vcc Supply Relative to Vss Vcc -1V to 4.6V Power Dissipation PD 4W TSTG -55oC to 150oC Voltage on Any Pin Relative to Vss Storage Temperature Short Circuit Output Current IOS 50mA Notes: Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. URL: www.hbe.co.kr REV 1.0 (August.2002) HANBit Electronics Co.,Ltd. 9 HANBit HSD16M32F4VP DC OPERATING CONDITIONS (Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70° C) ) PARAMETER SYMBOL MIN TYP. MAX UNIT NOTE Supply Voltage Vcc 3.0 3.3 3.6 V Input High Voltage VIH 2.0 3.0 Vcc+0.3 V 1 Input Low Voltage VIL -0.3 0 0.8 V 2 Output High Voltage VOH 2.4 - - V IOH = -2mA Output Low Voltage VOL - - 0.4 V IOL = 2mA Input leakage current I LI -10 10 uA Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. 3 CAPACITANCE (VCC = 3.3V, TA = 23° C, f = 1MHz, VREF =1.4V ± 200 mV) DESCRIPTION SYMBOL MIN MAX UNITS Clock CCLK 2.5 4.0 pF /RAS, /CAS,/WE,/CS, CKE, DQM CIN 2.5 5.0 pF Address CADD 2.5 5.0 pF DQ (DQ0 ~ DQ7) COUT 4.0 6.5 pF HSD16M32F4VP-10L UNIT DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70° C) TEST PARAMETER NOT SYMBOL CONDITION E Burst length = 1 Operating current ICC1 (One bank active) tRC ≥ tRC(min) 300 mA 4 mA 4 mA 80 mA 1 IO = 0mA Precharge standby ICC2P CKE ≤ VIL(max) tCC=10ns current in power-down mode ICC2PS CKE & CLK ≤ VIL(max) tCC=∞ Precharge CKE ≥ VIH(min) standby current in ICC2N CS* ≥ VIH(min), tCC=10ns Input signals are changed non power-down mode one time during 20ns URL: www.hbe.co.kr REV 1.0 (August.2002) HANBit Electronics Co.,Ltd. 9 HANBit HSD16M32F4VP CKE ≥ VIH(min) ICC2NS CLK ≤ VIL(max), tCC=∞ 28 Input signals are stable ICC3P Active standby current in power-down mode ICC3PS CKE ≤ VIL(max), tCC=10ns 20 CKE&CLK ≤ VIL(max) mA 20 tCC=∞ CKE≥VIH(min), CS*≥VIH(min), tCC=10ns 120 ICC3N Active standby current in Input signals are changed non power-down mode one time during 20ns (One bank active) CKE≥VIH(min) ICC3NS mA CLK ≤VIL(max), tCC=∞ 80 Input signals are stable IO = 0 mA Operating current Page burst ICC4 (Burst mode) 350 mA 1 840 mA 2 1.5 mA 4Banks Activated tCCD = 2CLKs Refresh current ICC5 tRC ≥ tRC(min) Self refresh current ICC6 Notes: 1. Measured with outputs open. 2. Refresh period is 64ms. CKE ≤ 0.2V 3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ). AC OPERATING TEST CONDITIONS (vcc = 3.3V ± 0.3V, TA = 0 to 70° C) PARAMETER AC Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition URL: www.hbe.co.kr REV 1.0 (August.2002) Value UNIT 2.4/0.4 V 1.4 V tr/tf = 1/1 ns 1.4 V See Fig. 2 HANBit Electronics Co.,Ltd. 9 HANBit HSD16M32F4VP +3.3V Vtt=1.4V 1200Ω 50Ω DOUT 870Ω DOUT Z0=50Ω 50pF* 50pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA (Fig. 2) AC output load circuit (Fig. 1) DC output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) PARAMETER SYMBOL HSD16M32F4VP-10L UNIT NOTE Row active to row active delay tRRD(min) 20 ns 1 RAS to CAS delay tRP(min) 20 ns 1 Row precharge time tRP(min) 20 ns 1 tRAS(min) 50 ns 1 tRAS(max) 100 ns tRC(min) 70 ns 1 Last data in to row precharge tRDL(min) 2 CLK 2 Last data in to Active delay tDAL(min) 2 CLK + 20 ns - Last data in to new col. address delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. address to col. address delay tCCD(min) 1 CLK 3 2 ea 4 Row active time Row cycle time Number of valid output data CAS latency=3 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. URL: www.hbe.co.kr REV 1.0 (August.2002) HANBit Electronics Co.,Ltd. 9 HANBit HSD16M32F4VP AC CHARACTERISTICS (AC operating conditions unless otherwise noted) HSD16M34F4VP-10L PARAMETER CLK cycle time SYMBOL UNIT NOTE 1000 ns 1 6 ns 1,2 MIN MAX 10 CAS tCC latency=3 CLK to valid CAS output delay latency=3 Output data CAS hold time latency=3 tSAC tOH 3 ns 2 CLK high pulse width tCH 3 ns 3 CLK low pulse width tCL 3 ns 3 Input setup time tSS 2 ns 3 Input hold time tSH 1 ns 3 CLK to output in Low-Z tSLZ 1 ns 3 ns 2 CLK to output CAS in Hi-Z latency=3 tSHZ 6 Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered ie., [(tr + tf)/2-1]ns should be added to the parameter. SIMPLIFIED TRUTH TABLE CKE n-1 COMMAND Register Mode register set Auto refresh Refresh Entry Self refres Exit h Bank active & row addr. Read & column address Write & column address Auto H /C S /R A S /C A S /W E D Q M X L L L L X OP code L L L H X X L H H H X X H L BA 0,1 L H H X X X H X L L H H X V H X L H L H X V precharge disable Auto H CKE n precharge Auto H X L H L L X precharge URL: www.hbe.co.kr REV 1.0 (August.2002) 1,2 3 3 3 3 4 Column Address H (A0 ~ A8) L Address V 4,5 H X L L H L X 4 (A0 ~ A8) H disable Burst Stop NOTE Column precharge disable A11 A9~A0 Row address L disable Auto A10/ AP 4,5 X HANBit Electronics Co.,Ltd. 9 6 HANBit HSD16M32F4VP Precharg Bank selection e All banks Clock suspend or active power down Precharge power down mode H X Entry H L Exit L H Entry H L Exit L H DQM H No operation command H L L H L H X X X L V V V X X X X H X X X L H H H H X X X V V V L X X H X X X L H H H X X V L X H X X X X X X V X X X (V=Valid, X=Don't care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) TIMING DIAGRAMS Please refer to attached timing diagram chart (II) PACKAGING INFORMATION Unit : mm URL: www.hbe.co.kr REV 1.0 (August.2002) HANBit Electronics Co.,Ltd. 9 7 HANBit HSD16M32F4VP HSD16M32F4VP Connector Configuration - Module PCB Bottom: AXN440530, 0.8mm Free Height Plugs,40pins - Board top, Module PCB Top: AXN340130 ,0.8mm Free Height Receptacles , 40pins ORDERING INFORMATION Part Number Density Org. HSD16M32F4VP-10L 64MByte 16Mx 32 URL: www.hbe.co.kr REV 1.0 (August.2002) Package 80 Pin SMM Ref. Vcc Interface 4K 3.3V LVTTL MAX.frq 100MHz (CL=3) HANBit Electronics Co.,Ltd. 9