HOLTEK HT82J97E

HT82J97E
USB Joystick Encoder 8-Bit OTP MCU
Features
· Flexible total solution for applications that combine
· Two 8-bit indirect addressing registers
PS/2 and low-speed USB interface, such as mice,
joysticks, and many others
· One 16-bit programmable timer counter with over-
flow interrupt (shared with PA7, vector 0CH)
· USB Specification Compliance
· One USB interrupt input (vector 04H)
- Conforms to USB specification V1.1
- Conforms to USB HID specification V1.1
· HALT function and wake-up feature reduce power
consumption
· Supports 1 Low-speed USB control endpoint and 1
· PA0~PA7 support wake-up function
interrupt endpoint
· Internal Power-On reset (POR)
· Each endpoint has 8´8 bytes FIFO
· Watchdog Timer (WDT)
· Integrated USB transceiver
· 20 I/O ports (including 2-PWM output, PC2, PC3)
· 3.3V regulator output
· 2 PWM output (PC2, PC3)
· External 6MHz or 12MHz ceramic resonator or crys-
· Can produce PWM frequency range from 23Hz to
tal
23kHz
· 8-bit RISC microcontroller, with 2K´14 EPROM
· Built-in 8-bit Analog-to-Digital Converter, (6-channel
(000H~7FFH)
for internal mode (PB0~PB5), 6-channel for external
mode with VHL (PB7) and VRL (PB6))
· 96 bytes RAM (20H~7FH)
· 6MHz/12MHz internal CPU clock
· 20/28-pin SOP package
· 4-level stacks
General Description
The USB MCU OTP body is suitable for USB mouse
and USB joystick devices. It consists of a Holtek high
performance 8-bit MCU core for control unit, built-in
USB SIE, 2K´14 EPROM and 96 bytes data RAM.
Block Diagram
U S B D + /C L K
U S B D -/D A T A
V 3 3 O
U S B 1 .1
P S 2
B P
In te rru p t
C ir c u it
S T A C K
P ro g ra m
R O M
P ro g ra m
C o u n te r
M
T M R 0
U
fS
/4
Y S
P A 7 /T M R
X
T M R 0 C
IN T C
E N /D IS
W D T S
In s tr u c tio n
R e g is te r
M
M P
U
X
W D T P r e s c a le r
D A T A
M e m o ry
P A C
M U X
In s tr u c tio n
D e c o d e r
P B C
T im in g
G e n e ra to r
O S C 2
Rev. 1.30
O S
R
V
V
C 1
E S
D D
S S
A L U
P O R T A
P A
S T A T U S
P O R T B
P B
S h ifte r
A /D
P C C
P C
A C C
W D T
M
U
S Y S C L K /4
X
W D T O S C
P A 0 ~ P A 6
P A 7 /T M R
P B 0 /A N 0 ~ P B 5 /A N 5
P B 6 /V R L
P B 7 /V R H
C o n v e rte r
P O R T C
P C 0 ~ P C 1
P C 2 /P W M 1
P C 3 /P W M 2
P W M
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May 10, 2004
HT82J97E
Pin Assignment
V S S
1
2 8
O S C I
V 3 3 O
2
2 7
O S C O
U S B D + /C L K
3
2 6
V D D
U S B D -/D A T A
4
P C 3 /P W M 2
5
2 5
2 4
P C 2 /P W M 1
2 3
P A 7
2 2
P A 6
2 1
P A 5
2 0
P A 4
1 9
P A 3
1 8
P A 2
1 7
P B 7 /V R H
1 6
P B 6 /V R L
1 5
P B 5 /A N 5
V S S
1
2 0
O S C I
R E S
V 3 3 O
2
1 9
O S C O
P A 0
U S B D + /C L K
3
1 8
V D D
P A 1
U S B D -/D A T A
4
1 7
P A 7
P C 0
R E S
5
1 6
P A 6
P C 1
P A 0
6
1 5
P A 5
P B 0 /A N 0
P A 1
7
1 4
P A 4
P B 1 /A N 1
P B 2
8
1 3
P A 3
P B 2 /A N 2
P B 3
9
1 2
P A 2
P B 3 /A N 3
P B 4
1 0
1 1
P B 7
P B 4 /A N 4
H T 8 2 J 9 7 E
2 0 S O P -A
6
7
8
9
1 0
1 1
1 2
1 3
1 4
H T 8 2 J 9 7 E
2 8 S O P -A
Pin Description
Pin Name
I/O
ROM Code
Option
Description
PA0~PA7
Bidirectional 8-bit input/output port. Each bit can be configured as a
wake-up input by ROM code option. The input or output mode is conPull-low
trolled by PAC (PA control register).
Pull-high
Pull-high resistor options: PA0~PA7
I/O
Wake-up
Pull-low resistor options: PA0~PA3
CMOS/NMOS/PMOS
CMOS/NMOS/PMOS options: PA0~PA7
Wake-up options: PA0~PA7
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB5/AN5
PB6/VRL
Pull-high
Analog input
Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output or Schmitt trigger input with pull-high resistor (determined
by pull-high options).
The PB can be used as analog input of the analog to digital converter
(determined by options).
Pull-low resistor for options: PB2, PB3
Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output or Schmitt trigger input with pull-high resistor (determined
by pull-high options).
The PB can be used as analog input of the analog to digital converter
(determined by options).
Wake-up options: PB4, PB7
I/O
PB4/AN4
PB7/VRH
I/O
Pull-high
Analog input
Wake-up
VSS
¾
¾
PC0~PC3
Negative power supply, ground
Bidirectional I/O lines. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by
pull-high options).
PC2 can be used as PWM1 output
PC3 can be used as PWM2 output
I/O
Pull-high
RES
I
¾
Schmitt trigger reset input. Active low.
VDD
¾
¾
Positive power supply
V33O
O
¾
3.3V regulator output
USBD+/CLK
I/O
¾
USBD+ or PS2 CLK I/O line
USB or PS2 function is controlled by software control register
USBD-/DATA
I/O
¾
USBD- or PS2 DATA I/O line
USB or PS2 function is controlled by software control register
OSCI
OSCO
I
O
¾
OSCI, OSCO are connected to a 6MHz or 12MHz crystal/resonator (determined by software instructions) for the internal system clock.
Rev. 1.30
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May 10, 2004
HT82J97E
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
Operating Temperature...............................0°C to 70°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol
Ta=25°C
Parameter
Test Conditions
VDD
Conditions
¾
Min.
Typ.
Max.
Unit
4
¾
5.5
V
VDD
Operating Voltage
¾
IDD
Operating Current (6MHz Crystal)
5V
No load, fSYS=6MHz
¾
7
9
mA
ISTB
Standby Current
5V
No load, system HALT
¾
300
500
mA
VIL1
Input Low Voltage for I/O Ports
5V
¾
0
¾
0.8
V
VIH1
Input High Voltage for I/O Ports
5V
¾
2
¾
5
V
VIL2
Input Low Voltage (RES)
5V
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
5V
¾
0.9VDD
¾
VDD
V
IOL
Output Sink Current for Other Ports
5V
PA0~PA7, PB0~PB7 and PC0~PC3
VOL=0.4V
2
4
¾
mA
IOH
Output Port Source Current
VOL=3.4V
-2.5
-4
¾
mA
RPD
Pull-down Resistance for PA0~PA3, PB2
5V
and PB3
¾
10
30
50
kW
RPH1
Pull-high Resistance for CLK and DATA
¾
¾
2
4.7
6
kW
RPH2
Pull-high Resistance for PA0~PA7,
¾
PB0~PB7 and PC0~PC3
¾
30
50
70
kW
VLVR
Low Voltage Reset
¾
2.4
2.7
3
V
5V
5V
A.C. Characteristics
Symbol
Ta=25°C
Parameter
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
fSYS
System Clock (Crystal OSC)
5V
¾
6
¾
12
MHz
fRCSYS
RC Clock with 8-bit Prescaler Register
5V
¾
0
32
¾
kHz
tWDT
Watchdog Time-out Period (System Clock)
¾
¾
¾
tRCSYS
tRF
USBD+, USBD- Rising & falling Time
¾
75
¾
300
ns
tSST
System Start-up Timer Period
¾
¾
1024
¾
tSYS
tOSC
Crystal Setup
¾
¾
5
10
ms
fPWM
PWM Cycle Frequency
¾
23
¾
2300
Hz
Without WDT prescaler 1024
¾
Wake-up from HALT
¾
6MHz or 12MHz
Note: Power-on period=tWDT+tSST+tOSC
WDT Time-out in normal mode=1/fRCSYS´256´WDTS+tWDT
WDT Time-out in HALT mode=1/fRCSYS´256´WDTS+tSST+tOSC
Rev. 1.30
3
May 10, 2004
HT82J97E
Functional Description
Execution Flow
After accessing a program memory word to fetch an instruction code, the contents of the program counter are
incremented by one. The program counter then points to
the memory word containing the next instruction code.
The system clock for the microcontroller is derived from
either 6MHz or 12MHz crystal oscillator, which used a
frequency that is determined by the SCLKSEL bit of the
SCC Register. The default system frequency is 12MHz.
The system clock is internally divided into four nonoverlapping clocks. One instruction cycle consists of
four system clock cycles.
When executing a jump instruction, conditional skip execution, loading to the PCL register, performing a subroutine call or return from subroutine, initial reset,
internal interrupt, external interrupt or return from interrupts, the PC manipulates the program transfer by loading the address corresponding to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruction to be effectively executed in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed with the next instruction.
The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within the current program ROM page.
Program Counter - PC
The program counter (PC) controls the sequence in
which the instructions stored in the program ROM are
executed and its contents specify a full range of program memory.
S y s te m
C lo c k
T 1
T 2
T 3
T 4
T 1
When a control transfer takes place, an additional
dummy cycle is required.
T 2
T 3
T 4
T 1
T 2
T 3
T 4
O S C 2 ( R C o n ly )
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
USB Interrupt
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter Overflow
0
0
0
0
0
0
0
1
1
0
0
@4
@3
@2
@1
@0
Skip
PC+2
Loading PCL
*10
*9
*8
@7
@6
@5
Jump, Call Branch
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note: *10~*0: Program counter bits
S10~S0: Stack register bits
#10~#0: Instruction code bits
Rev. 1.30
@7~@0: PCL bits
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May 10, 2004
HT82J97E
ROM data by two table read instructions: ²TABRDC²
and ²TABRDL², transfer the contents of the
lower-order byte to the specified data memory, and
the higher-order byte to TBLH (08H).
The three methods are shown as follows:
Program Memory - ROM
The program memory is used to store the program instructions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
2048´14 bits, addressed by the program counter and table pointer.
¨
The instructions ²TABRDC [m]² (the current page,
one page=256words), where the table locations is
defined by TBLP (07H) in the current page. And the
ROM code option TBHP is disabled (default).
¨
The instructions ²TABRDC [m]², where the table locations is defined by registers TBLP (07H) and
TBHP (01FH). And the ROM code option TBHP is
enabled.
¨
The instructions ²TABRDL [m]², where the table locations is defined by Registers TBLP (07H) in the
last page (0700H~07FFH).
Certain locations in the program memory are reserved
for special usage:
· Location 000H
This area is reserved for program initialization. After a
chip reset, the program always begins execution at location 000H.
· Location 004H
This area is reserved for the USB interrupt service
program. If the USB interrupt is activated, the interrupt
is enabled and the stack is not full, the program begins
execution at location 004H.
Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are
transferred to the lower portion of TBLH, and the remaining 1-bit words are read as ²0². The Table
Higher-order byte register (TBLH) is read only. The table pointer (TBLP, TBHP) is a read/write register (07H,
1FH), which indicates the table location. Before accessing the table, the location must be placed in the
TBLP and TBHP (If the OTP option TBHP is disabled,
the value in TBHP has no effect). The TBLH is read
only and cannot be restored. If the main routine and
the ISR (Interrupt Service Routine) both employ the
table read instruction, the contents of the TBLH in the
main routine are likely to be changed by the table read
instruction used in the ISR. Errors can occur. In other
words, using the table read instruction in the main routine and the ISR simultaneously should be avoided.
However, if the table read instruction has to be applied
in both the main routine and the ISR, the interrupt
should be disabled prior to the table read instruction. It
will not be enabled until the TBLH has been backed
up. All table related instructions require two cycles to
complete the operation. These areas may function as
normal program memory depending on the requirements.
Once TBHP is enabled, the instruction ²TABRDC [m]²
reads the ROM data as defined by TBLP and TBHP
value. Otherwise, the ROM code option TBHP is disabled, the instruction ²TABRDC [m]² reads the ROM
data as defined by TBLP and the current program
counter bits.
· Location 00CH
This location is reserved for the Timer/Event Counter
interrupt service program. If a timer interrupt results
from a Timer/Event Counter overflow, and the interrupt is enabled and the stack is not full, the program
begins execution at location 00CH.
· Table location
Any location in the program memory can be used as
look-up tables. There are three method to read the
0 0 0 H
D e v ic e In itia liz a tio n P r o g r a m
0 0 4 H
U S B In te r r u p t S u b r o u tin e
0 0 C H
T im e r /E v e n t C o u n te r
In te r r u p t S u b r o u tin e
P ro g ra m
M e m o ry
n 0 0 H
L o o k - u p T a b le ( 2 5 6 W o r d s )
n F F H
L o o k - u p T a b le ( 2 5 6 W o r d s )
7 F F H
1 4 B its
N o te : n ra n g e s fro m
0 to 7
Program Memory
Instruction
Table Location
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note: *10~*0: Table location bits
P10~P8: Current program counter bits when TBHP is disabled
@7~@0: TBLP bits
Rev. 1.30
TBHP register bit2~bit0 when TBHP is enabled
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May 10, 2004
HT82J97E
B a n k 0
Stack Register - STACK
0 0 H
This is a special part of the memory which is used to
save the contents of the program counter (PC) only. The
stack is organized into 8 levels and is neither part of the
data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledge signal, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the
stack. After a chip reset, the SP will point to the top of the
stack.
0 1 H
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
0 4 H
B P
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
W D T S
0 A H
S T A T U S
0 B H
IN T C
0 C H
P W M 1 D u ty R e g is te r
0 D H
P W M 2 D u ty R e g is te r
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledge signal will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is subsequently executed, stack overflow occurs and the first
entry will be lost (only the most recent 8 return addresses are stored).
0 E H
Data Memory - RAM for Bank 0
1 9 H
T M R H
0 F H
1 0 H
T M R L
1 1 H
T M R C
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 6 H
P C
1 7 H
P C C
1 8 H
The data memory is designed with 96´8 bits. The data
memory is divided into two functional groups: special
function registers and general purpose data memory
(96´8). Most are read/write, but some are read only.
The special function registers include the indirect addressing registers (R0;00H, R1;02H), Bank register (BP,
04H), PWM1 duty register (0DH), PWM2 duty register(0EH), Timer/Event Counter higher order byte register (TMRH;0FH), Timer/Event Counter lower order byte
register (TMRL;10H), Timer/Event Counter control register (TMRC;11H), program counter lower-order byte
register (PCL;06H), memory pointer registers
(MP0;01H, MP1;03H), accumulator (ACC;05H), table
pointers (TBLP;07H, TBHP;1FH), table higher-order
b y t e r egi s t er ( TB LH ; 08H ) , s t at us r e g i st e r
(STATUS;0AH), interrupt control register (INTC;0BH),
Watchdog Timer option setting register (WDTS;09H),
I/O registers (PA;12H, PB;14H, PC;16H), PWM Base
Period Register (18H), I/O control registers (PAC;13H,
PBC;15H, PCC;17H). USB/PS2 status and control register (USC;1AH), USB endpoint interrupt status register
(USR;1BH), system clock control register (SCC;1CH).
A/D converter status and control register (ADSC;1DH)
and A/D converter result register (ADR;1EH). The remaining space before the 20H is reserved for future ex-
Rev. 1.30
In d ir e c t A d d r e s s in g R e g is te r 0
P W M
B a s e P e r io d R e g is te r ( P D )
1 A H
U S C
1 B H
U S R
1 C H
S C C
1 D H
A D S C
1 E H
A D R
1 F H
2 0 H
T B H P
G e n e ra l P u rp o s e
D A T A M E M O R Y
(9 6 B y te s )
7 F H
Bank 0 RAM Mapping
panded usage and reading these locations will get
²00H². The general purpose data memory, addressed
from 20H to 7FH, is used for data and control information under instruction commands.
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the
data memory can be set and reset by ²SET [m].i² and
²CLR [m].i². They are also indirectly accessible through
memory pointer registers (MP0 or MP1).
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May 10, 2004
HT82J97E
Data Memory - RAM for Bank 1
Indirect Addressing Register
The special function registers used in the USB interface
are located in RAM Bank1. In order to access Bank1
register, only the Indirect addressing pointer MP1 can
be used and the Bank register BP should be set to 1.
The RAM bank 1 mapping is as shown.
Locations 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write
operation on [00H] ([02H]) will access the data memory
pointed to by MP0 (MP1). Reading location 00H (02H)
indirectly will return the result 00H. Writing indirectly results in no operation.
B a n k 1
0 0 H
In d ir e c t A d d r e s s in g R e g is te r 0
0 1 H
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
0 4 H
B P
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
The indirect addressing pointer (MP0) always points to
Bank0 RAM addresses no matter the value of Bank
Register (BP).
The indirect addressing pointer (MP1) can access
Bank0 or Bank1 RAM data according to the value of BP
which is set to 0 or 1 respectively.
The memory pointer registers (MP0 and MP1) are 8-bit
registers.
0 9 H
W D T S
0 A H
S T A T U S
0 B H
IN T C
0 C H
P W M 1 D u ty R e g is te r
0 D H
P W M 2 D u ty R e g is te r
Accumulator
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
0 E H
T M R H
0 F H
1 0 H
T M R L
1 1 H
T M R C
1 2 H
P A
1 3 H
P A C
1 4 H
P B
This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:
1 5 H
P B C
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
1 6 H
P C
1 7 H
P C C
1 8 H
P W M
Arithmetic and Logic Unit - ALU
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
B a s e P e r io d R e g is te r ( P D )
· Increment and Decrement (INC, DEC)
1 9 H
1 A H
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
U S C
1 B H
U S R
1 C H
S C C
1 D H
A D S C
The ALU not only saves the results of a data operation
but also changes the status register.
1 E H
A D R
Status Register - STATUS
1 F H
2 0 H
T B H P
4 1 H
P ip e _ c tr l
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF), and watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.
4 2 H
A W R
4 3 H
S T A L L
4 4 H
4 5 H
P IP E
4 6 H
4 7 H
M IS C
4 8 H
4 9 H
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition, operations related to the status register may give different results from those intended.
S IE S
F IF O
0
F IF O
1
RAM Bank 1
Address 00~1FH in RAM Bank0 and Bank1 are located
in the same Registers
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HT82J97E
Labels
Bits
Function
C
0
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
AC
1
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the
high nibble into the low nibble in subtraction; otherwise AC is cleared.
Z
2
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
OV
3
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
PDF
4
PDF is cleared by a system power-up or executing the ²CLR WDT² instruction. PDF is set by
executing the ²HALT² instruction.
TO
5
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is
set by a WDT time-out.
¾
6
Unused bit, read as ²0²
¾
7
Unused bit, read as ²0²
Status Register
Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the
EMI bit and the corresponding bit of the INTC may be
set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If
immediate service is desired, the stack must be prevented from becoming full.
The TO flag can be affected only by a system power-up,
a WDT time-out or executing the ²CLR WDT² or ²HALT²
instruction. The PDF flag can be affected only by executing the ²HALT² or ²CLR WDT² instruction or during a
system power-up.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, upon entering the interrupt sequence or executing a subroutine call, the status register will not be
automatically pushed onto the stack. If the contents of
the status are important and if the subroutine can corrupt the status register, precautions must be taken to
save it properly.
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at a specified location in the
program memory. Only the program counter is pushed
onto the stack. If the contents of the register or status
register (STATUS) are altered by the interrupt service
program which corrupts the desired control sequence,
the contents should be saved in advance.
Interrupt
The device provides an external interrupt and internal
timer/event counter interrupts. The Interrupt Control
Register (INTC;0BH) contains the interrupt control bits
to set the enable/disable and the interrupt request flags.
Register
INTC
(0BH)
Bit No.
Label
Function
0
EMI
Controls the master (global) interrupt (1=enable; 0=disable)
1
EUI
Controls the USB interrupt (1=enable; 0= disable)
2
¾
Unused bit, read as ²0²
3
ETI
Controls the Timer/Event Counter interrupt (1=enable; 0=disable)
4
USBF
5
¾
Unused bit, read as ²0²
6
TF
Internal timer/event counter request flag (1:active; 0:inactive)
7
¾
Unused bit, read as ²0²
USB interrupt request flag (1=active; 0=inactive)
INTC Register
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HT82J97E
enable master interrupt bit (EMI) constitute an interrupt
control register (INTC) which is located at 0BH in the
data memory. EMI, EUI and ETI are used to control the
enabling/disabling of interrupts. These bits prevent the
requested interrupt from being serviced. Once the interrupt request flags (TF, USBF) are set, they will remain in
the INTC register until the interrupts are serviced or
cleared by a software instruction.
The USB interrupts are triggered by the following USB
events and the related interrupt request flag (USBF; bit
4 of the INTC) will be set.
· Access of the corresponding USB FIFO from PC
· suspend signal from PC
· resume signal from PC
· USB Reset signal
When the interrupt is enabled, the stack is not full and
the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (USBF)
and EMI bits will be cleared to disable other interrupts.
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only
one stack is left and enabling the interrupt is not well
controlled, the original control sequence will be damaged once the ²CALL² operates in the interrupt subroutine.
When the PC Host access the FIFO of the HT82J97E,
the corresponding request bit of the USR is set, and a
USB interrupt is triggered. So user can easily decide
which FIFO is accessed. When the interrupt has been
served, the corresponding bit should be cleared by firmware. When the HT82J97E receives a USB Suspend
signal from the Host PC, the suspend line (bit0 of the
USC) of the HT82J97E is set and a USB interrupt is also
triggered.
Oscillator Configuration
There is an oscillator circuit in the microcontroller.
O S C 1
When the HT82J97E receives a Resume signal from the
Host PC, the resume line (bit3 of the USC) of the
HT82J97E is set and a USB interrupt is triggered.
O S C 2
C r y s ta l O s c illa to r
Whenever a USB reset signal is detected, the USB interrupt is triggered and URST_Flag bit of the USC register is set. When the interrupt has been served, the bit
should be cleared by firmware.
System Oscillator
This oscillator is designed for system clocks. The HALT
mode stops the system oscillator and ignores an external signal to conserve power.
The internal timer/even counter interrupt is initialized by
setting the timer/event counter interrupt request flag (;bit
6 of the INTC), caused by a timer overflow. When the interrupt is enabled, the stack is not full and the TF is set, a
subroutine call to location 0CH will occur. The related interrupt request flag (TF) will be reset and the EMI bit
cleared to disable further interrupts.
A crystal across OSC1 and OSC2 is needed to provide
the feedback and phase shift required for the oscillator.
No other external components are required. In stead of
a crystal, a resonator can also be connected between
OSC1 and OSC2 to get a frequency reference, but two
external capacitors in OSC1 and OSC2 are required.
The HT82J97E can operate in 6MHz or 12MHz system
clocks. In order to make sure that the USB SIE functions
properly, user should correctly configure the SCLKSEL
bit of the SCC Register. The default system clock is
12MHz.
During the execution of an interrupt subroutine, other interrupt acknowledge signals are held until the ²RETI² instruction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, ²RET² or ²RETI²
may be invoked. RETI will set the EMI bit to enable an
interrupt service, but RET will not.
The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDT oscillator still works within
a period of approximately 31ms. The WDT oscillator can
be disabled by ROM code option to conserve power.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
No.
Interrupt Source
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator), or instruction clock (system clock divided by 4), determine by ROM code option.
This timer is designed to prevent a software malfunction
or sequence from jumping to an unknown location with
unpredictable results. The Watchdog Timer can be disabled by ROM code option. If the Watchdog Timer is dis-
Priority Vector
a
USB interrupt
1
04H
b
Timer/Event Counter overflow
2
0CH
The timer/event counter interrupt request flag (TF), USB
interrupt request flag (USBF), enable timer/event counter interrupt bit (ETI), enable USB interrupt bit (EUI) and
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HT82J97E
S y s te m
C lo c k /4
R O M
C o d e
O p tio n
S e le c t
W D T
O S C
W D T P r e s c a le r
8 - b it C o u n te r
7 - b it C o u n te r
8 -to -1 M U X
W S 0 ~ W S 2
W D T T im e - o u t
Watchdog Timer
tion option². If the ²CLR WDT² is selected (i.e. CLRWDT
times is equal to one), any execution of the ²CLR WDT²
instruction will clear the WDT. In the case that ²CLR
WDT² and ²CLR WDT² are chosen (i.e. CLRWDT times
is equal to two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset
the chip as a result of time-out.
abled, all the executions related to the WDT result in no
operation.
Once the internal WDT oscillator (RC oscillator with a
period of 31ms/5V normally) is selected, it is first divided
by 256 (8-stage) to get the nominal time-out period of
8ms/5V. This time-out period may vary with temperatures, VDD and process variations. By invoking the
WDT prescaler, longer time-out periods can be realized.
Writing data to WS2, WS1, WS0 (bits 2, 1, 0 of the
WDTS) can give different time-out periods. If WS2,
WS1, and WS0 are all equal to 1, the division ratio is up
to 1:128, and the maximum time-out period is 1s/5V. If
the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operates in the
same manner except that in the HALT state the WDT
may stop counting and lose its protecting purpose. In
this situation the logic can only be restarted by external
logic. The high nibble and bit 3 of the WDTS are reserved for user defined flags, which can only be set to
²10000² (WDTS.7~WDTS.3).
Power Down Operation - HALT
The HALT mode is initialized by the ²HALT² instruction
and results in the following:
· The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is selected).
· The contents of the on-chip RAM and registers remain
unchanged.
· The WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT oscillator).
· All of the I/O ports remain in their original status.
· The PDF flag is set and the TO flag is cleared.
If the device operates in a noisy environment, using the
on-chip 32kHz RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock.
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow performs a ²warm reset². After the TO and PDF flags are
examined, the cause for chip reset can be determined.
The PDF flag is cleared by a system power-up or executing the ²CLR WDT² instruction and is set when executing the ²HALT² instruction. The TO flag is set if the
WDT time-out occurs, and causes a wake-up that only
resets the PC and SP; the others remain in their original
status.
The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit
in port A can be independently selected to wake-up the
device by mask option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it awakens from an interrupt, two sequence
may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is
enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is set to
²1² before entering the HALT mode, the wake-up function of the related interrupt will be disabled. Once a
WDTS Register
The WDT overflow under normal operation will initialize
a ²chip reset² and set the status bit ²TO². But in the
HALT mode, the overflow will initialize a ²warm reset²
and only the PC and SP are reset to zero. To clear the
contents of the WDT (including the WDT prescaler),
three methods are adopted; external reset (a low level to
RES), software instruction and a ²HALT² instruction.
The software instruction include ²CLR WDT² and the
other set - ²CLR WDT1² and ²CLR WDT2². Of these
two types of instruction, only one can be active depending on the ROM code option - ²CLR WDT times selecRev. 1.30
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HT82J97E
V D D
wake-up event occurs, it takes 1024 tSYS (system clock
period) to resume normal operation. In other words, a
dummy period will be inserted after a wake-up. If the
wake-up results from an interrupt acknowledge signal,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
R E S
tS
S T
S S T T im e - o u t
C h ip
R e s e t
Reset Timing Chart
V
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
D D
Reset
R E S
There are four ways in which a reset can occur:
· RES reset during normal operation
· RES reset during HALT
· WDT time-out reset during normal operation
Reset Circuit
· USB reset
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re set² that resets only the PC and SP, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions. Most registers
are reset to the ²initial condition² when the reset conditions are met. By examining the PDF and TO flags, the
program can distinguish between different ²chip resets².
TO PDF
H A L T
W a rm
R e s e t
W D T
R E S
C o ld
R e s e t
S S T
1 0 - b it R ip p le
C o u n te r
O S C 1
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
S y s te m
R e s e t
Reset Configuration
The functional unit chip reset status are shown below.
PC
000H
Note: ²u² stands for ²unchanged²
Interrupt
Disable
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra delay of 1024 system clock pulses when the system resets (power-up, WDT time-out or RES reset) or
the system awakes from the HALT state.
Prescaler
Clear
WDT
Clear. After master reset, WDT
begins counting
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will enable the SST delay.
Input/output Ports
Input mode
Stack Pointer
Points to the top of the stack
Rev. 1.30
Timer/event Counter Off
11
May 10, 2004
HT82J97E
The registers status are summarized in the following table.
Reset
(Power On)
WDT
Time-out
(Normal
Operation)
RES Reset
(Normal
Operation)
RES Reset
(HALT)
WDT
Time-Out
(HALT)*
USB-Reset
(Normal)
USB-Reset
(HALT)
TMRH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMRL
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMRC
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
00-0 1---
00-0 1---
000H
000H
000H
000H
000H
000H
000H
MP0
1xxx xxxx
1uuu uuuu
1uuu uuuu
1uuu uuuu
1uuu uuuu
1uuu uuuu
1uuu uuuu
MP1
1xxx xxxx
1uuu uuuu
1uuu uuuu
1uuu uuuu
1uuu uuuu
1uuu uuuu
1uuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
--uu uuuu
--01 uuuu
Register
Program
Counter
INTC
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
-000 0000
-000 0000
WDTS
1000 0111
1000 0111
1000 0111
1000 0111
uuuu uuuu
1000 0111
1000 0111
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PCC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PD
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
AWR
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
PIPE
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
STALL
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
SIES
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
MISC
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
FIFO0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
FIFO1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
USC
11xx 0000
uuxx uuuu
11xx 0000
11xx 0000
uuxx uuuu
1100 0u00
1100 0u00
USR
0100 0000
uuuu uuuu
0100 0000
0100 0000
uuuu uuuu
u1uu 0000
u1uu 0000
SCC
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
uu00 u000
uu00 u000
ADSC
1000 0000
uuuu uuuu
1000 0000
1000 0000
uuuu uuuu
1000 0000
1000 0000
ADR
xxxx xxxx
uuuu uuuu
xxxx xxxx
xxxx xxxx
uuuu uuuu
xxxx xxxx
xxxx xxxx
Note: ²*² stands for ²warm reset²
²u² stands for ²unchanged²
²x² stands for ²unknown²
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HT82J97E
Timer/Event Counter
which means that the clock source comes from an external (TMR) pin. The timer mode functions as a normal
timer with the clock source coming from the fSYS/4
(Timer). The pulse width measurement mode can be
used to count the high or low level duration of the external signal (TMR). The counting is based on the fSYS/4.
A timer/event counter (TMR) is implemented in the
microcontroller.
The timer/event counter contains a 16-bit programmable count-up counter and the clock may come from an
external source or from the system clock divided by 4.
In the event count or timer mode, once the timer/event
counter starts counting, it will count from the current
contents in the timer/event counter to FFFFH. Once
overflow occurs, the counter is reloaded from the
timer/event counter preload register and generates the
interrupt request flag (TF; bit 6 of the INTC) at the same
time.
Using the internal clock source, there is only 1 reference
time-base for the timer/event counter. The internal clock
source is coming from fSYS/4. The external clock input
allows the user to count external events, measure time
intervals or pulse widths.
There are 3 registers related to the timer/event counter;
TMRH (0FH), TMRL (10H), TMRC (11H). Writing TMRL
will only put the written data to an internal lower-order
byte buffer (8 bits) and writing TMRH will transfer the
specified data and the contents of the lower-order byte
buffer to TMRH and TMRL preload registers, respectively. The timer/event counter preload register is
changed by each writing TMRH operations. Reading
TMRH will latch the contents of TMRH and TMRL counters to the destination and the lower-order byte buffer,
respectively. Reading the TMRL will read the contents of
the lower-order byte buffer. The TMRC is the
timer/event counter control register, which defines the
operating mode, counting enable or disable and active
edge.
In the pulse width measurement mode with the TON and
TE bits equal to one, once the TMR has received a transient from low to high (or high to low if the TE bit is ²0²) it
will start counting until the TMR returns to the original
level and resets the TON. The measured result will remain in the timer/event counter even if the activated
transient occurs again. In other words, only one cycle
measurement can be done. Until setting the TON, the
cycle measurement will function again as long as it receives further transient pulse. Note that, in this operating mode, the timer/event counter starts counting not
according to the logic level but according to the transient
edges. In the case of counter overflows, the counter is
reloaded from the timer/event counter preload register
and issues the interrupt request just like the other two
modes. To enable the counting operation, the timer ON
The TM0, TM1 bits define the operating mode. The
event count mode is used to count external events,
Label (TMRC)
Bits
¾
0~2
Function
Unused bit, read as ²0²
TE
3
Defines the TMR active edge of the timer/event counter
(0=active on low to high; 1=active on high to low)
TON
4
Enable/disable the timer counting
(0=disable; 1=enable)
5
Unused bit, read as ²0²
6
7
Defines the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
¾
TM0
TM1
TMRC Register
D a ta B u s
fS
Y S /4
T M 1
T M 0
T M R
1 6 B its
T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
R e lo a d
T E
T M 1
T M 0
T O N
L o w B y te
B u ffe r
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
1 6 B its
T im e r /E v e n t C o u n te r
(T M R H /T M R L )
O v e r flo w
to In te rru p t
Timer/Event Counter
Rev. 1.30
13
May 10, 2004
HT82J97E
control. To function as an input, the corresponding latch
of the control register must write a ²1². The input source
also depends on the control register. If the control register bit is ²1², the input will read the pad state. If the control register bit is ²0², the contents of the latches will
move to the internal bus. The latter is possible in the
²read-modify-write² instruction. For output function,
CMOS/NMOS/PMOS configurations can be selected
(NMOS and PMOS are available for PA only). These
control registers are mapped to locations 13H, 15H and
17H.
bit (TON; bit 4 of TMRC) should be set to 1. In the pulse
width measurement mode, the TON will be cleared automatically after the measurement cycle is completed.
But in the other two modes the TON can only be reset by
instructions. The overflow of the timer/event counter is
one of the wake-up sources. No matter what the operation mode is, writing a 0 to ET can disable the corresponding interrupt services.
In the case of timer/event counter OFF condition, writing
data to the timer/event counter preload register will also
reload that data to the timer/event counter. But if the
timer/event counter is turned on, data written to it will
only be kept in the timer/event counter preload register.
The timer/event counter will still operate until overflow
occurs (a timer/event counter reloading will occur at the
same time). When the timer/event counter (reading
TMR) is read, the clock will be blocked to avoid errors.
As clock blocking may result in a counting error, this
must be taken into consideration by the programmer.
After a chip reset, these input/output lines remain at high
levels or in a floating state (depending on the
pull-high/low options). Each bit of these input/output
latches can be set or cleared by ²SET [m].i² and ²CLR
[m].i² (m=12H, 14H or 16H) instructions.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Input/Output Ports
There are 20 bidirectional input/output lines in the
microcontroller, labeled from PA to PC, which are
mapped to the data memory of [12H], [14H] and [16H]
respectively. All of these I/O ports can be used for input
and output operations. For input operation, these ports
are non-latching, that is, the inputs must be ready at the
T2 rising edge of instruction ²MOV A,[m]² (m=12H, 14H
or 16H). For output operation, all the data is latched and
remains unchanged until the output latch is rewritten.
Each line of port A has the capability of waking-up the
device.
There are pull-high/low (PA only) options available for
I/O lines. Once the pull-high/low option of an I/O line is
selected, the I/O line have pull-high/low resistor. Otherwise, the pull-high/low resistor is absent. It should be
noted that a non-pull-high/low I/O line operating in input
mode will cause a floating state.
Each I/O line has its own control register (PAC, PBC,
PCC) to control the input/output configuration. With this
control register, CMOS/NMOS/PMOS output or Schmitt
trigger input with or without pull-high/low resistor structures can be reconfigured dynamically under software
It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
to avoid consuming power under input floating state.
V
C o n tr o l B it
D a ta B u s
W r ite C o n tr o l R e g is te r
W r ite D a ta R e g is te r
P o rt O u tp u t
C o n fig u r a tio n
R e a d D a ta R e g is te r
P A W a k e -u p
P A 7 /T M R
A N 0 ~ A N 5 , V R L , V R H
P H
Q
D
C K
Q B
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
D D
P A
P B
P B
P C
D a ta B it
Q
D
C K
0 ~
0 /A
6 /V
0 ~
P A
N
R
P C
6 , P A 7 /T M R
0 ~ P B 5 /A N 5
L , P B 7 /V R H
3
Q B
S
P L
M
U
X
P A W a k e - u p O p tio n
Input/Output Ports
Note: The outputs of PC2 and PC3 will be PWM outputs when PWM outputs are enabled.
Rev. 1.30
14
May 10, 2004
HT82J97E
Low Voltage Reset - LVR
The relationship between VDD and VLVR is shown below.
The microcontroller contains a low voltage reset circuit
in order to monitor the supply voltage of the device. If the
supply voltage of the device drops to within the range of
0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally.
V D D
5 .5 V
O P R
5 .5 V
V
The LVR includes the following specifications:
L V R
2 .7 V
· For a valid LVR signal, a low voltage (0.9V~VLVR) must
2 .4 V
exist for more than 1ms. If the low voltage state does
not exceed 1ms, the LVR will ignore it and will not perform a reset function.
· The LVR uses the ²OR² function with the external
0 .9 V
Note: VOPR is the voltage range for proper chip operation at 6MHz or 12MHz system clock.
RES signal to perform a chip reset.
V
V
D D
5 .5 V
V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
N o r m a l O p e r a tio n
R e s e t
R e s e t
*1
*2
Low Voltage Reset
Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
*2: A low voltage has to exist for more than 1ms, after that 1ms delay, the device enters a reset mode.
Rev. 1.30
15
May 10, 2004
HT82J97E
USB with MCU Interface
There are eight registers, including Pipe_ctrl, Address+Remote_WakeUp, Stall, Pipe, SIES, Misc, FIFO 0 and FIFO 1
in this buffer function.
Register Name Pipe_ctrl Addr.+Remote
Stall
Pipe
SIES
Misc
FIFO 0
FIFO 1
Mem. Addr.
43H
44H
45H
46H
48H
49H
41H
42H
Reserved Addr.
Bank 1, Address 40H, 4AH, 4FH
Register Memory Mapping
Address+Remote_WakeUp register represents current address and remote wake-up function. The initial value is
²00000000² from MSB to LSB.
Register
Address
R/W
01000010B
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Remote Wake-up Function
0: Not this function
1: The function exists
Address value
Default value=00000000
Address+Remote_WakeUp Register
The PIPE_ctrl, STALL and PIPE are bitmap ones. The Pipe_ctrl Register is used for configuring IN (Bit=1) or OUT
(Bit=0) Pipe. The default is defined as IN Pipe. The Pipe register represents whether the corresponding endpoint is accessed by host or not. After a USB interrupt signal is being sent out, the MCU can check which endpoint had been accessed. This register is set only after the host accessed the corresponding endpoint. The Stall register shows whether
the corresponding endpoint works or not. As soon as the endpoint works improperly, the corresponding bit must be set.
The bitmaps are listed as follows:
Register
Name
R/W
Register
Address
Bit7~Bit2 Reserved
Bit 1
Bit 0
Default
Value
Pipe_ctrl
R/W
01000001B
¾
Pipe 1
Pipe 0
00000011
Stall
R/W
01000011B
¾
Pipe 1
Pipe 0
00000000
Pipe
R
01000100B
¾
Pipe 1
Pipe 0
00000000
Stall and Pipe Registers
The SIES Register is used to indicate the present signal state which the USB SIE received and also determines
whether the USB SIE has to change the device address automatically.
Bit No.
Function
Read/Write
7
MNI
R/W
6
EOT
R
5
CRC_ERR
R/W
4
NAK
R
3
IN
R
2
OUT
R/W
1
F0_ERR
R/W
0
Adr_set
R/W
Register Address
01000101B
SIES Registers Table
Rev. 1.30
16
May 10, 2004
HT82J97E
Function
Name
Read/Write
Description
Adr_set
R/W
This bit is used to configure the USB SIE to automatically change the device address with
the value of the Address+Remote_WakeUp Register (42H).
When this bit is set to 1 by F/W, the USB SIE will update the device address with the value
of the Address+Remote_WakeUp Register (42H) after the PC Host has successfully read
the data from the device by the IN operation. The USB SIE will clear the bit after updating
the device address.
Otherwise, when this bit is cleared to 0, the USB SIE will update the device address immediately after an address is written to the Address+Remote_WakeUp Register (42H).
F0_Err
R/W
This bit is used to indicate when there are some errors that occurred when the FIFO0 is
accessed.
This bit is set by the USB SIE and cleared by F/W.
Out
R/W
This bit is used to indicate that there are OUT token (except for the OUT zero) that has
been received. The F/W clears the bit after the OUT data has been read. Also, this bit will
be cleared by the USB SIE after the next valid SETUP token is received.
IN
R
This bit is used to indicate that the current USB receiving signal from the PC Host is IN token.
NAK
R
This bit is used to indicate that the USB SIE has transmitted the NAK signal to the Host in
response to the PC Host IN or OUT token.
R/W
This bit indicates that there are CRC error (bit=1). The programmer must do something to
save the device and keep it alive.
This bit is set by the USB SIE and cleared by F/W.
EOT
R
End of transient flag, normal status is 1. If suspend=²1² line & EOT=²0² indicates that
something is wrong in the USB Interface. The programmer must do something to save the
device and keep it alive.
MNI
R/W
CRC_err
This bit is for masking the NAK interrupt when MNI=²1², the default value=²0²
SIES Function Table
The Misc register is actually a command + status to control the desired FIFO action and to show the status of the desired FIFO. Every bit¢s meaning and usage are listed as follows:
Bit No.
Function
Read/Write
7
Len0
R/W
6
Ready
R
5
Set CMD
R/W
4
Sel_pipe1
R/W
3
Sel_pipe0
R/W
2
Clear
R/W
1
Tx
R/W
0
Request
R/W
Register Address
01000110B
Misc Registers Table
Rev. 1.30
17
May 10, 2004
HT82J97E
Function
Name
Read/Write
Description
R/W
After setting the other desired status, FIFO can be requested by setting this bit high active.
After work has been done, this bit must be set low.
Tx
R/W
Represents the direction and transition end of the MCU accesses. When being set as logic
1, the MCU wants to write data to FIFO. After work has been done, this bit must be set to
logic 0 before terminating the request to represent a transition end. For reading action, this
bit must be set to logic 0 to indicate that the MCU wants to read and must be set to logic 1
after work is done.
Clear
R/W
Represents MCU clear requested FIFO, even if FIFO is not ready.
Sel_pipe1
Sel_pipe0
R/W
Determines which FIFO is desired, ²00² for FIFO 0, ²01² for FIFO 1
Set CMD
R/W
Shows that the data in FIFO is setup as command. This bit will be cleared by firmware. So,
even if the MCU is busy, nothing is missed by the SETUP command from the host.
Request
Ready
Len0
R
R/W
Indicates that the desired FIFO is ready to work.
Indicates that the host sent a 0-sized packet to the MCU. This bit must be cleared by a
read action to the corresponding FIFO. Also, this bit will be cleared by the USB SIE after
the next valid SETUP token is received.
Misc Function Table
HT82J97E allows a maximum of 8 bytes of data in each
packet.
The HT82J97E has two 8´8 bidirectional FIFO for the
two endpoints (control and Interrupt). User can easily
read/write the FIFO data by accessing the corresponding FIFO pointer register (FIFO0, FIFO1). The following
are two examples for reading and writing the FIFO data:
The HT82J97E FIFO is written by packet. To write to
FIFO, the following should be followed:
· Select a set of FIFO, set in the write mode (MISC TX
HT82J97E FIFO is read by packet. To read from FIFO,
the following should be followed:
bit = 1), and set the REQ bit to ²1²
· Check the ready bit until the status = 1
· Select one set of FIFO, set in the read mode (MISC
· Write through the FIFO pointer register and take down
TX bit = 0), and set the REQ bit to ²1².
the data number that has been written
· Check the ready bit until the status = 1
· Repeat steps 2 and 3 until writing is complete or the
· Read through the FIFO pointer register, and record
ready bit becomes 0 which indicates that the FIFO no
longer allows any data writing.
· Set MISC TX bit = 0
the data number that has been read.
· Repeat steps 2 and 3 until the ready bit becomes 0
· Clear the REQ bit to 0. Complete writing.
which indicates the end of the FIFO data reading.
· Set MISC TX bit = 1
User writes the data through the FIFO pointer register,
user has to record the number of bytes that have been
written. The HT82J97E allows a maximum of 8 bytes of
data in each packet.
· Clear the REQ bit to 0. Complete reading.
User reads the data through the FIFO pointer register,
user has to record the number of bytes to be read. The
Rev. 1.30
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May 10, 2004
HT82J97E
There are some timing constrains and usages illustrated here. By setting the MISC register, the MCU can perform reading, writing and clearing actions. There are some examples shown in the following table for endpoint FIFO reading, writing and clearing.
Actions
MISC Setting Flow and Status
Read FIFO0 sequence
00H®01H®delay of 2ms, check 41H®read* from FIFO0 register
and check if not ready (01H)®03H®02H
Write FIFO1 sequence
0AH®0BH®delay of 2ms, check 4BH®write* to FIFO1 register and
check if not ready (0BH)®09H®08H
Check whether FIFO0 can be read or not
00H®01H®delay of 2ms, check 41H (if ready) or 01H (if not
ready)®00H
Check whether FIFO1 can be written to or not
0AH®0BH®delay of 2ms, check 4BH (if ready) or 0BH (if not
ready)®0AH
Write 0-sized packet sequence to FIFO 0
02H®03H®delay of 2ms, check 43H®01H®00H
Note: *: There are 2ms gap existing between 2 reading actions or between 2 writing actions
Register Name
R/W
Register Address
Bit7~Bit0
FIFO 0
R/W
01001000B
Data7~Data0
FIFO 1
R/W
01001001B
Data7~Data0
FIFO Register Address Table
USB Active Pipe Timing
The USB active pipe accessed by the host cannot be used by the MCU simultaneously. When the host finishes its work,
the signal, a USB_INT will be produced to tell the MCU that the pipe can be used and the acted pipe No. will be shown
in the signal, ACT_PIPE as well. The timing is illustrated in the Figure below.
L a s t A c te d P ip e
A C T _ P IP E
U S B _ IN T
USB Active Pipe Timing
the Resume line (bit 3 of the USC) is set. In order to
make the HT82J97E function properly, the programmer
must set the USBCKEN (bit 3 of the SCC) to 1 and clear
the SUSP2 (bit4 of the SCC). Since the Resume signal
will be cleared before the Idle signal is sent out by the
host and the Suspend line (bit 0 of the USC) is going to
²0². So when the MCU is detecting the Suspend line
(bit0 of the USC), the Resume line should be remembered and taken into consideration.
Suspend Wake-Up and Remote Wake-Up
If there is no signal on the USB bus for over 3ms, the
HT82J97E will go into a suspend mode. The Suspend
line (bit 0 of the USC) will be set to 1 and a USB interrupt
is triggered to indicate that the HT82J97E should jump
to the suspend state to meet the 500mA USB suspend
current spec.
In order to meet the 500mA suspend current, the programmer should disable the USB clock by clearing the
USBCKEN (bit3 of the SCC) to ²0². The suspend current is 400mA.
After finishing the resume signal, the suspend line will
go inactive and a USB interrupt is triggered. The following is the timing diagram:
The user can also further decrease the suspend current
to 250mA by setting the SUSP2 (bit4 of the SCC). But if
the SUSP2 is set, the user has to make sure not to enable the LVR OPT option, otherwise the HT82J97E will
be reset.
S U S P E N D
U S B R e s u m e S ig n a l
When the resume signal is sent out by the host, the
HT82J97E will wake-up the MCU by USB interrupt and
Rev. 1.30
U S B _ IN T
19
May 10, 2004
HT82J97E
If SPS2=0, and SUSB=1, the HT82J97E is defined as a
USB interface. Both the USBD- and USBD+ are driven
by the USB SIE of the HT82J97E. User only writes or
reads the USB data through the corresponding FIFO.
The device with remote wake-up function can wake-up
the USB Host by sending a wake-up pulse through
RMWK (bit 1 of USC). Once the USB Host receive the
wake-up signal from the HT82J97E, it will send a Resume signal to the device. The timing is as follows:
Both SPS2 and SUSB default is ²0².
S U S P E N D
To Configure the ADC Block
M in . 1 U S B C L K
The HT82J97E has built-in an 8-bit A/D converter with 6
channels (PB0~PB5). In order to make the A/D converter more flexible, there are two modes: External Reference voltage and Internal Reference voltage. It can be
easily configured by setting the ADREF (bit 6 of the
USR). For External Reference voltage, the reference
voltage of the A/D converter comes from an external
PB6/VRL and PB7/VRH pins. Otherwise, the reference
voltage is coming from the VDD and VSS of the MCU.
R M W K
U S B R e s u m e S ig n a l
M in .2 .5 m s
U S B _ IN T
To Configure the HT82J97E as PS2 Device
PB0~PB5 is the 6-channel input of the A/D converter, it
is easy to define which channel is converting by configuring ACS2~ACS0 (bit 2~0 of the ADSC). Also there are
four converter clock sources to be selected by setting
ADCS1 (bit 4 of the ADSC), ADCS0 ( bit 3 of the ADSC).
The HT82J97E can be defined as a USB interface or a
PS2 interface by configuring the SPS2 (bit 4 of the USR)
and SUSB (bit 5 of the USR). If SPS2=1, and SUSB=0,
the HT82J97E is defined as PS2 interface, pin USBD- is
now defined as PS2 Data pin and USBD+ is now defined as PS2 Clk pin. The user can easily read or write to
the PS2 Data or PS2 Clk pin by accessing the corresponding bit PS2DAI (bit 4 of the USC), PS2CKI (bit 5 of
the USC), PS2DAO (bit 6 of the USC) and S2CKO (bit 7
of the USC) respectively.
Once the ADON (bit 6 of the ADSC) is set, it sends the
start pulse through START (bit 5 of ADSC). The A/D
converter will be in operation. There are EOCB (bit 7 of
the ADSC) to indicate whether the A/D converter is busy
or not. The EOCB is cleared when the conversion is
completed. User can read the converter data by reading
the register ADR. In order to meet 500mA suspend current spec., user should disable the A/D by clearing
ADON before jumping to suspend mode.
The user should make sure that in order to read the data
properly, the corresponding output bit must be set to ²1².
For example, if user wants to read the PS2 Data by
reading PS2DAI, the PS2DAO should be set to ²1². Otherwise it always read a ²0².
The following is an A/D converter timing diagram:
N o rm a l M o d e
T 1
A D O N
0
A /D
S T A R T
0
D 7
0
C o n v e r s io n S ta r ts
A /D
A /D
D 0
A /D
C o n v e r s io n
C o n v e r s io n S ta r ts
A /D
0 o r 1
C o n v e r s io n T im e
0 o r 1
A /D
C o n v e r s io n
C o n v e r s io n T im e
0 o r 1
0 o r 1
1
E O C B
P o w e r_ d o w n
Rev. 1.30
A /D
C o n v e r s io n F in is h e d
20
A /D
C o n v e r s io n F in is h e d
May 10, 2004
HT82J97E
PWM1 Low pulse period = PWM cycle period-high pulse
period
To Configure PWM Block
The HT82J97E has two PWM outputs (PWM1 and
PWM2), which are shared with PC2, PC3 and can be
easily enabled or disabled by the PWM1_EN or
PWM2_EN bit of PORT_PC (16H) respectively.
PWM2 duty (high pulse) = (PWM2DR+1)/256´100%
PWM2 high pulse period = PWM2 duty´PWM cycle period
PWM2 Low pulse period = PWM cycle period-high pulse
period
Also there is a one 8-bit PWMBR (PWM Base Period
Register, 18H) which defines both PWM output waveform cycle period.
For example PWMBR=17, PWM1DR=63, 4/fSYS (T1) is
selected and fSYS=6MHz
PWM cycle period = 256´1/f SYS ´(PWMBR+1), or
256´4/fSYS´(PWMBR+1)
PWM cycle period = 256´4/6´(17+1) = about 3072ms
(0.325kHz)
where 1/fSYS or 4/fSYS is defined by PWM_S bit of the
PORT_PC (16H)
PWM1 duty = (63+1)/256 = 25%
For example if PWMBR = 17, 4/fSYS (T1) is selected and
fSYS = 6MHz.
PWM1 high pulse period = 25%´3072ms = 768ms
PWM1 low pulse period = 3072ms -768ms = 2304ms
So both output waveform cycle period is 256´4/6
´(17+1) = about 3072ms (0.325kHz)
P W M
H ig h P u ls e
Now user can easily define the corresponding PWM
duty by configuring the PWM1DR (for PWM1) or
PWM2DR (for PWM2) duty registers
P W M
PWM1 duty (high pulse) = (PWM1DR+1)/256´100%
C y c le P e r io d
PWM1 high pulse period = PWM1 duty´PWM cycle period
I/O Port Special Registers Definition
· Port-A (12H) - PA
Register
PA
(12H)
Bits
Labels
Read/Write
Option
Functions
0
PA0
R/W
¾
I/O (R/W) has pull-low and pull-high ROM code option.
Has falling edge wake-up ROM code option.
1
PA1
R/W
¾
I/O (R/W) has pull-low and pull-high option.
Has falling edge wake-up option.
2
PA2
R/W
¾
I/O (R/W) has pull-low and pull-high option.
Has falling edge and rising edge wake-up option.
3
PA3
R/W
¾
I/O (R/W) has pull-low and pull-high option.
Has falling edge and rising edge wake-up option.
4
PA4
R/W
¾
I/O (R/W) has pull-high option.
Has falling edge wake-up option.
5
PA5
R/W
¾
I/O (R/W) has pull-high option.
Has falling edge wake-up option.
6
PA6
R/W
¾
I/O (R/W) has pull-high option.
Has falling edge wake-up option.
7
PA7
R/W
¾
I/O (R/W) has pull-high option.
Has falling edge wake-up option, pin-shared with timer input pin.
· Port-A Control (13H) - PAC
This port configure the input or output mode of Port-A
Rev. 1.30
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May 10, 2004
HT82J97E
· Port-B Control (14H) - PB
Register
PB
(14H)
Bits
Labels
Read/Write
Option
Functions
0
PB0
R/W
¾
I/O (R/W), has pull-high option, ADC input.
1
PB1
R/W
¾
I/O (R/W), has pull-high option, ADC input.
2
PB2
R/W
¾
I/O (R/W), has pull-low and pull-high option, ADC input.
3
PB3
R/W
¾
I/O (R/W), has pull-low and pull-high option, ADC input.
4
PB4
R/W
¾
I/O (R/W), has pull-high option, can wake-up, ADC input.
5
PB5
R/W
¾
I/O (R/W), has pull-high option, ADC input.
6
PB6
R/W
¾
I/O (R/W), has pull-high option, ADC input, VRL input for
ADC external mode.
7
PB7
R/W
¾
I/O (R/W), has pull-high option, ADC input, VRH input for
ADC external mode, has wake-up capability.
· Port-B Control (15H) - PBC
This port configures the input or output mode of Port-B for I/O mode
· Port-C Control (16H) - PC
Register
PC
(16H)
Bits
Labels
Read/Write
Option
Functions
0
PC0
R/W
¾
I/O (R/W), has pull-high option
1
PC1
R/W
¾
I/O (R/W), has pull-high option
2
PC2
R/W
¾
I/O (R/W), has pull-high option, can be used as PWM1 output
3
PC3
R/W
¾
I/O (R/W), has pull-high option, can be used as PWM2 output
4
PC4
¾
¾
Reserved bit
5
PC5
R/W
PWM_S
PWM base period register frequency source
0= T1 (default)
1= fSYS
6
PC6
R/W
PWM1_EN
1: Internal register bit, enable PWM1 output
0: Disable (default)
7
PC7
R/W
PWM2_EN
1: Internal register bit, enable output
0: Disable (default)
· Port-C Control (17H) - PCC
This port is used to control whether the Port-C pin is input or output pin except PC4~PC7
Rev. 1.30
22
May 10, 2004
HT82J97E
USB/PS2 Status and Control Register USC (Address 0X1A)
Register
USC
(0X1A)
Bits
Labels
Read/Write
Option
Functions
0
PE0
R
SUSPEND
USB suspend mode status bit. When 1, indicates that
the USB system entry is in suspend mode.
1
PE1
W
RMOT_WK
USB remote wake-up signal. Default value is 0.
2
PE2
R/W
3
PE3
R
RESUME_O
4
PE4
R
PS2_DAI
USBD-/DATA input
5
PE5
R
PS2_CKI
USBD+/CLK input
6
PE6
W
PS2_DAO
Output for driving USBD-/DATA pin, when working under 3D PS2 mouse function. Default value is 1.
7
PE7
W
PS2_CKO
Output for driving USBD-/DATA pin, when working under 3D PS2 mouse function. Default value is 1.
URST_FLAG USB bus reset event flag. Default value is 0.
When RESUME_OUT EVENT, RESUME_O is set to 1.
Default value is 0.
Endpoint Interrupt Status Register USR (Address 0X1B)
The USR (USB endpoint interrupt status register) register is used to indicate which endpoint is accessed and to select
the serial bus (PS2 or USB) and A/D converter operation modes. The endpoint request flags (EP0IF, EP1IF) are used
to indicate which endpoints are accessed. If an endpoint is accessed, the related endpoint request flag will be set to ²1²
and a USB interrupt will occur (If a USB interrupt is enabled and the stack is not full). When the active endpoint request
flag is served, the endpoint request flag has to be cleared to ²0².
Register
Bits
0
USR
(0X1B)
Rev. 1.30
Labels
PEC0
Read/Write
R/W
Option
Functions
EP0IF
When set to ²1², indicates an endpoint 0 interrupt event.
Must wait for the MCU to process the interrupt event and
clear this bit by firmware. This bit must be ²0², then the
next interrupt event will be processed. Default value is
²0².
When set to ²1², indicates an endpoint 1 interrupt event.
Must wait for the MCU to process the interrupt event,
then clear this bit by firmware. This bit must be ²0², then
the next interrupt event will be processed. Default value
is ²0².
1
PEC1
R/W
EP1IF
2
PEC2
R/W
¾
Reserved bit, set to ²0²
3
PEC3
R/W
¾
Reserved bit, set to ²0²
4
PEC4
R/W
SELPS2
When set to ²1², indicates that the chip is working under
PS2 mode. Default value is ²0².
5
PEC5
R/W
SELUSB
When set to ²1², indicates that the chip is working under
USB mode. Default value is 0.
6
PEC6
R/W
VRSEL
When set to ²0², indicates the reference voltage of the
8-bit ADC from the external input pin. When set to ²1²,
indicates that the reference voltage is from the internal
power line. Default value is ²1².
7
PEC7
R/W
USB_flag
This flag is used to show that the MCU is in USB mode
(Bit=1). This bit is R/W by FW and will be cleared to zero
after power-on reset. The default is ²0².
23
May 10, 2004
HT82J97E
Clock Control Register SCC (Address 0X1C)
There is a system clock control register implemented to select the clock used in the MCU. This register consists of USB
clock control bit (USBCKEN), second suspend mode control bit (SUSPEND2) and system clock selection (SCLKSEL).
Register
SCC
(0X1C)
Bits
Labels
Read/Write
Option
Functions
2~0
PF2~PF0
R/W
¾
3
PF3
R/W
USBCKEN
USB clock control bit. When set to ²1², indicates a
USBCK ON, else USBCK OFF. Default value is ²0².
4
PF4
R/W
SUSPEND2
When set to ²1², enables a 7.5kW resistor connected to
D-pin to 5V VDD. Default value is ²0².
5
PF5
R/W
¾
Reserved
Reserved
6
PF6
R/W
SCLKSEL
System clock 6MHz or 12MHz option, when working on
external oscillator mode. Default value is ²0².
0: Operating at external 12MHz mode
1: Operating at external 6MHz mode
Default value is ²0².
7
PF7
R/W
PS2_flag
This flag is used to show that the MCU is in PS2 mode
(Bit=1). This bit is R/W by FW and will be cleared to zero
after power-on reset. The default is ²0².
ADC Status and Control Register ADC (Address 0X1D)
The A/D converter implemented in the MCU is a 6-channel 8-bit A/D converter. The reference voltage (high reference
voltage and low reference voltage) can be selected as coming from external pins (PB6/VRL and PB7/VRH) or internal
power supplies of the MCU (VDD and VSS). The VRL and VRH are used to set the minimal and maximal boundaries of
the full-scale range of the A/D converter. If an analog input, VRL or VRH is not used for A/D conversion, it can also be
used as a general purpose I/O line. The ADSC (A/D converter status and control register) register is used to set the
configurations and A/D clock sources of the A/D converter and controls the operation of the A/D converter.
Register Bits
Labels
2~0 PFC2~PFC0
ADC
(0X1D)
Rev. 1.30
4~3 PFC4~PFC3
Read/Write
Option
Functions
SEL_CH
These four bits selects one of the eight ADC channels
for conversion. Channels 0 to 5 correspond to inputs
AD0~AD5 on port pins PB0-PB5 respectively. Channels 6 and 7 are the ADC reference inputs VRH and
VRL, on port pins PB6 and PB7 respectively.
000: AD0 (PB0); 001: AD1 (PB1)
010: AD2 (PB2); 011: AD3 (PB3)
100: AD4 (PB4); 101: AD5 (PB5)
110: AD6 or VRL (PB6); 111: AD7 or VRH (PB7)
Default value is 000¢B.
R/W
SEL_CLK
Selecting ADC operating clock.
00: 6MHz (Default clock)
01: 3MHz
10: 1.5MHz
11: 0.75MHz
R/W
5
PFC5
R/W
START
Start of ADC conversion. High active. Default value is
²0²
6
PFC6
R/W
ADON
Enable pin. ADON=1, Enable ADC block.
Default value is ²0².
7
PFC7
R/W
EOCB
End of conversion. This read-only status bit is cleared
when a conversion is completed, indicating that the
ADC Data Register contains a valid result.
24
May 10, 2004
HT82J97E
ADC High-byte Data Register ADCR (Address 0X1E)
Register Bits
ADCR
(0X1E)
Labels
7~0
Read/Write
PG7~PG0
R
Option
Functions
ADCDR
The ADCDR stores the result of a valid ADC conversion
bit7~bit0.
Table High Byte Pointer for Current Table Read TBHP (Address 0X1F)
Register Bits
TBHP
(0X1F)
2~0
Labels
Read/Write
Option
PGC2~PG0
R
¾
Functions
Store current table read bit10~bit8 data
PWM Base Period Register PWMBR (Address 0X18)
This register is used to define the base period of the PWM cycle period. The period is defined according to the following
equation:
Base period = (4/fSYS)´(PWMBR+1) or (1/fSYS) ´ (PWMBR+1)
Where 4/fSYS or 1/fSYS is defined by PWM_S bit of PORT_PC
Where PWMBR = 1~255, PWMBR=0 is not available
PWM cycle period = 256´Base period
Base period equals to 1/256 duty cycle.
Register Bits
PWMBR
7~0
(0X18)
Labels
PD7~PD0
Read/Write
R
Option
Functions
Used to define the base period of the PWM
Range =2~256´Base Period
Where PWMBR=1~255, PWMBR=0 is not available
¾
PWM Duty Register PWM1DR (Address 0XCH) and PWM2DR (Address 0XDH)
This register is used to define the duty of the PWM1 output (PC2) or PWM2 output (PC3) respectively. Both PWM cycle
frequency is defined according to the following equation:
Register
Bits
Read/Write
Option
PWM1DR (0XCH)
PWM2DR (0XDH)
7~0
R/W
¾
Functions
Used to define the PWM duty
PWM1 duty = (PWM1DR+1)/PWM cycle´100% period
Where PWM1DR= 0~255
If the PWM function is enabled by setting the corresponding bit (PWM1_EN or PWM2_EN of Port C), the PWM output
(PC2 or PC3) pins always output the PWM signal whether the corresponding control register bit (PCC2 or PCC3 ) is defined as in input or output mode.
OTP Options
No.
Option
1
WDT clock source: RC (system/4) (default: T1)
2
WDT clock source: enable/disable for normal mode (default: disable)
3
PA0~PA7 ,PB4, PB7 wake-up by bit (PA2, PA3 both wake-up by falling or rising edge) (default: non wake-up)
4
PA0~PA7 pull-high by bit (default: Pull-high)
5
PC0~3,PB pull-high by nibble (default: Pull-high)
6
2.7 V (error 0.3V) LVR enable/disable (default: enable)
7
PA0~PA3, PB2, PB3 Pull-low by bit (default: non pull-low 30kW)
8
²CLR WDT², 1 or 2 instructions
9
TBHP enable/disable (default: disable)
10
PA output mode (CMOS/NMOS/PMOS) by bit (default: CMOS)
The LVR voltage is define as 2.7V±0.3V and default is enable.
Rev. 1.30
25
May 10, 2004
HT82J97E
Application Circuits
Crystal or Ceramic Resonator for Multiple I/O Applications
5 W
V D D
U S B -
0 .1 m F
U S B +
*
3 3 W
*
1 0 m F
*
1 0 0 k W
V S S
5 W
X 1
2 2 p F
0 .1 m F
P B 0 ~ P B 7
P C 0 ~ P C 3
2 2 p F
**
*
P A 0 ~ P A 7
V D D
0 .1 m F
1 0 k W
**
*
0 .1 m F
O S C 1
1 .5 k W
V 3 3 O
0 .1 m F
O S C 2
*
R E S
3 3 W
U S B D -/D A T A
4 7 p F *
V S S
4 7 p F *
4 7 p F
3 3 W
U S B D + /C L K
H T 8 2 J 9 7 E
*
*
*
*
4 7 p F
Note: The resistance and capacitance for the reset circuit should be designed in such a way as to ensure that the VDD
is stable and remains within a valid operating voltage range before bringing RES to high.
X1 can use 6MHz or 12MHz, X1 as close OSC1 & OSC2 as possible
Components with * are used for EMC issue.
Components with ** are used for resonator only.
Rev. 1.30
26
May 10, 2004
HT82J97E
Instruction Set Summary
Description
Instruction
Cycle
Flag
Affected
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to data memory with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1
1
1(1)
1
1
1(1)
1
1(1)
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
1
1(1)
Z
Z
Z
Z
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1
1(1)
1
1(1)
1
1(1)
1
1(1)
None
None
C
C
None
None
C
C
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Mnemonic
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Rev. 1.30
27
May 10, 2004
HT82J97E
Mnemonic
Description
Instruction
Cycle
Flag
Affected
2
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
2(1)
2(1)
2(1)
None
None
None
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
None
TO,PDF
Branch
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC[M](5) Read ROM code (locate by TBLPand TBHP) to data memory and TBLH
TABRDC [m](6) Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
Note: x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
:
and (2)
(4)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
²CLR WDT1² or ²CLR WDT2² instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
(5)
: ²ROM code TBHP option² is enabled
(6)
: ²ROM code TBHP option² is disabled
Rev. 1.30
28
May 10, 2004
HT82J97E
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
29
May 10, 2004
HT82J97E
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ PC+1
PC ¬ addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
The contents of the specified data memory are cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
30
May 10, 2004
HT82J97E
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
0
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
31
May 10, 2004
HT82J97E
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory is decremented by 1.
Operation
[m] ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
32
May 10, 2004
HT82J97E
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation
PC ¬ PC+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
1
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Data in the specified data memory is incremented by 1
Operation
[m] ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
PC ¬addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV A,[m]
Move data memory to the accumulator
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
33
May 10, 2004
HT82J97E
MOV A,x
Move immediate data to the accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
PC ¬ PC+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
34
May 10, 2004
HT82J97E
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a 2-cycle instruction.
Operation
PC ¬ Stack
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data.
Operation
PC ¬ Stack
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
PC ¬ Stack
EMI ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
35
May 10, 2004
HT82J97E
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
36
May 10, 2004
HT82J97E
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
37
May 10, 2004
HT82J97E
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Bit i of the specified data memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
38
May 10, 2004
HT82J97E
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
39
May 10, 2004
HT82J97E
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (locate by TBLP and TBHP) to TBLH and data memory (ROM code
TBHP is enabled)
Description
The low byte of ROM code addressed by the table pointers (TBLPand TBHP) is moved to
the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory (ROM code TBHP is
disabled)
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
40
May 10, 2004
HT82J97E
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
41
May 10, 2004
HT82J97E
Package Information
20-pin SOP (300mil) Outline Dimensions
1 1
2 0
A
B
1
1 0
C
C '
G
H
D
E
Symbol
Rev. 1.30
a
F
Dimensions in mil
Min.
Nom.
Max.
A
394
¾
419
B
290
¾
300
C
14
¾
20
C¢
490
¾
510
D
92
¾
104
E
¾
50
¾
F
4
¾
¾
G
32
¾
38
H
4
¾
12
a
0°
¾
10°
42
May 10, 2004
HT82J97E
28-pin SOP (300mil) Outline Dimensions
2 8
1 5
A
B
1
1 4
C
C '
G
H
D
E
Symbol
Rev. 1.30
a
F
Dimensions in mil
Min.
Nom.
Max.
A
394
¾
419
B
290
¾
300
C
14
¾
20
C¢
697
¾
713
D
92
¾
104
E
¾
50
¾
F
4
¾
¾
G
32
¾
38
H
4
¾
12
a
0°
¾
10°
43
May 10, 2004
HT82J97E
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SOP 20W
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330±1.0
B
Reel Inner Diameter
62±1.5
C
Spindle Hole Diameter
13.0+0.5
-0.2
D
Key Slit Width
2.0±0.5
T1
Space Between Flange
24.8+0.3
-0.2
T2
Reel Thickness
30.2±0.2
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330±1.0
B
Reel Inner Diameter
62±1.5
C
Spindle Hole Diameter
13.0+0.5
-0.2
D
Key Slit Width
2.0±0.5
T1
Space Between Flange
24.8+0.3
-0.2
T2
Reel Thickness
30.2±0.2
Rev. 1.30
44
May 10, 2004
HT82J97E
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
C
D 1
B 0
P
K 0
A 0
SOP 20W
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
24.0+0.3
-0.1
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
11.5±0.1
D
Perforation Diameter
1.5+0.1
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
10.8±0.1
B0
Cavity Width
13.3±0.1
K0
Cavity Depth
3.2±0.1
t
Carrier Tape Thickness
0.3±0.05
C
Cover Tape Width
21.3
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
24.0±0.3
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
11.5±0.1
D
Perforation Diameter
1.5+0.1
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
10.85±0.1
B0
Cavity Width
18.34±0.1
K0
Cavity Depth
2.97±0.1
t
Carrier Tape Thickness
0.35±0.01
C
Cover Tape Width
Rev. 1.30
21.3
45
May 10, 2004
HT82J97E
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shanghai Sales Office)
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 021-6485-5560
Fax: 021-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor Inc. (Shenzhen Sales Office)
43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031
Tel: 0755-8346-5589
Fax: 0755-8346-5590
ISDN: 0755-8346-5591
Holtek Semiconductor Inc. (Beijing Sales Office)
Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 010-6641-0030, 6641-7751, 6641-7752
Fax: 010-6641-0125
Holmate Semiconductor, Inc. (North America Sales Office)
46712 Fremont Blvd., Fremont, CA 94538
Tel: 510-252-9880
Fax: 510-252-9885
http://www.holmate.com
Copyright Ó 2004 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.30
46
May 10, 2004