HOLTEK HT46RB50

HT46RB50
A/D Type USB 8-Bit MCU
Technical Document
· Tools Information
· FAQs
· Application Note
Features
· Operating voltage:
· 6-level subroutine nesting
fSYS=6MHz: 2.2V~5.5V
fSYS=12MHz: 2.7V~5.5V
· 8 channels 10-bit resolution A/D converter
· 2-channel 8-bit PWM output shared with two I/O lines
· 38 bidirectional I/O lines (max.)
· SIO (synchronous serial I/O) function
· 1 interrupt input shared with an I/O line
· Supports Interrupt, Control, Bulk transfer
· One 16-bit programmable timer/event counter with
· USB 1.1 full speed function compatible
overflow interrupt
· 4 endpoints supported (endpoint 0 included)
· One 8-bit programmable timer/event counter with
· Total FIFO size is 88 byte (8, 8, 8, 64 for EP0~EP3)
overflow interrupt and 7 stage prescaler
· Bit manipulation instruction
· Only crystal oscillator (6MHz or 12MHz)
· 15-bit table read instruction
· Watchdog Timer
· 63 powerful instructions
· 4096´15 program memory
· All instructions in one or two machine cycles
· 192´8 data memory RAM
· Low voltage reset function
· HALT function and wake-up feature reduce power
· 28-pin SOP/SKDIP, 48-pin SSOP package
consumption
· Up to 0.33ms instruction cycle with 12MHz system
clock at VDD=5V
General Description
touch-pads, PS II joysticks, XBOX joysticks, USB Mice
keyboards and joystick. A HALT feature is included to
reduce power consumption.
This device is an 8-bit high performance RISC
architecture microcontroller designed for USB product
applications. It is particularly suitable for use in products
such as USB and/or SPI touch-panels, USB and/or SPI
Rev. 1.20
1
November 1, 2006
HT46RB50
Block Diagram
U S B D +
V 3 3 O
U S B D -
T M R 0 C
U S B 1 .1
F u ll S p e e d
T M R 1 C
S T A C K
P ro g ra m
C o u n te r
P r e s c a le r
U
X
M
T M R 1
IN T C
U
fS
Y S
P C 1 /T M R 0
T M R 0
In te rru p t
C ir c u it
P ro g ra m
R O M
M
fS
Y S
X
/4
P C 2 /T M R 1
E N /D IS
W D T S
In s tr u c tio n
R e g is te r
M
M P
U
X
W D T P r e s c a le r
D A T A
M e m o ry
P A C
M U X
In s tr u c tio n
D e c o d e r
P o rt A
P A
P B C
A L U
T im in g
G e n e ra to r
S T A T U S
P o rt B
P B
S h ifte r
A /D
O S C 1
R E S
V D D
V S S
A V D D
A V S S
P o rt C
P C
A C C
U
fS
Y S
/4
W D T O S C
X
P A 0 ~ P A 7
P B 0 /A N 0 ~ P B 7 /A N 7
C o n v e rte r
P C C
O S C 2
M
W D T
P D C
P o rt D
P D
P C 0 /IN T
P C 3 ~ P C 7
P D 0 /P W M 0 ~ P D 1 /P W M 1 ,
P D 2 ~ P D 7
P W M
P E C
P E
S e r ia l
In te rfa c e
Rev. 1.20
2
P o rt E
P E
P E
P E
P E
P E
4 ~ P
0 /S
1 /C
2 /S
3 /S
E 5
C S
L K
D I
D O
November 1, 2006
HT46RB50
Pin Assignment
P A 3
1
2 8
P A 3
1
4 8
P A 4
P A 2
2
4 7
P A 5
P A 1
3
4 6
P A 6
P A 0
4
4 5
P A 7
P D 3
5
4 4
P D 4
P D 2
6
4 3
P D 5
P D 1 /P W M 1
7
4 2
P D 6
P D 0 /P W M 0
8
4 1
P D 7
P B 7 /A N 7
9
4 0
R E S
P B 6 /A N 6
1 0
3 9
A V D D
P A 4
P B 5 /A N 5
1 1
3 8
V D D
P A 2
2
2 7
P A 5
P B 4 /A N 4
1 2
3 7
A V S S
P A 1
3
2 6
P A 6
P C 7
1 3
3 6
V S S
P A 0
4
2 5
P A 7
P C 6
1 4
3 5
O S C 1
P D 1 /P W M 1
5
2 4
R E S
P C 5
1 5
3 4
O S C 2
P D 0 /P W M 0
6
2 3
V D D /A V D D
P C 4
1 6
3 3
P E 4
P B 5 /A N 5
7
2 2
V S S /A V S S
P B 3 /A N 3
1 7
3 2
P E 5
P B 4 /A N 4
8
2 1
O S C 1
P B 2 /A N 2
1 8
3 1
V 3 3 O
P B 3 /A N 3
9
2 0
O S C 2
P B 1 /A N 1
1 9
3 0
U D P
P B 2 /A N 2
1 0
1 9
V 3 3 O
P B 0 /A N 0
2 0
2 9
U D N
P B 1 /A N 1
1 1
1 8
U D P
P E 3 /S D O
2 1
2 8
P C 0 /IN T
P B 0 /A N 0
1 2
1 7
U D N
P E 2 /S D I
2 2
2 7
P C 1 /T M R 0
P E 3 /S D O
1 3
1 6
P C 0 /IN T
P E 1 /C L K
2 3
2 6
P C 2 /T M R 1
1 4
1 5
P E 1 /C L K
P E 0 /S C S
2 4
2 5
P C 3
P E 2 /S D I
H T 4 6 R B 5 0
2 8 S O P -A /S K D IP -A
H T 4 6 R B 5 0
4 8 S S O P -A
Pin Description
Pin Name
PA0~PA7
PB0/AN0~
PB7/AN7
PC0/INT
PC1/TMR0
PC2/TMR1
PC3~PC7
PD0/PWM0~
PD1/PWM1
PD2~PD7
PE0/SCS
PE1/CLK
Rev. 1.20
I/O
Options
Description
I/O
Pull-high
(bit option)
Wake-up
(bit option)
Bidirectional 8-bit input/output port. Each bit can be configured as a
wake-up input by ROM code option. The input or output mode is controlled
by PAC (PA control register, bit option). Pull-high resistor options:
PA0~PA7, bit option, wake-up options: PA0~PA7.
I/O
Pull-high
(bit option)
Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output or Schmitt trigger input with pull-high resistor (determined by
pull-high options: bit option). The PB can be used as analog input of the analog to digital converter.
I/O
Pull-high
(nibble option)
Bidirectional I/O lines. Software instructions determine the CMOS output or
Schmitt trigger input with pull-high resistor (determined by pull-high options:
nibble option). The PC0, PC1 PC2 are pin-shared with INT, TMR0 or TMR1,
respectively.
I/O
Pull-high
(nibble option)
I/O or PWM
Bidirectional I/O lines. Software instructions determine the CMOS output or
Schmitt trigger input with pull-high resistor (determined by pull-high options:
nibble option). The PD0/PD1 are pin-shared with PWM0/PWM1 (dependent
on PWM options).
I/O
Pull-high
(nibble option)
Bidirectional I/O lines. Software instructions determine the CMOS output or
Schmitt trigger input with pull-high resistor (determined by pull-high options:
nibble option). The PE0 is pin-shared with SCS. SCS is a chip select pin of
the Serial interface, Master mode is output, Slave mode is input.
I/O
Pull-high
(nibble option)
Bidirectional I/O lines. Software instructions determine the CMOS output or
Schmitt trigger input with pull-high resistor (determined by pull-high options:
nibble option). The PE1 is pin-shared with CLK. CLK is a Serial interface serial clock input/output (Initial is input).
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November 1, 2006
HT46RB50
Pin Name
I/O
Options
Description
PE2/SDI
I/O
Pull-high
(nibble option)
Bidirectional I/O lines. Software instructions determine the CMOS output or
Schmitt trigger input with pull-high resistor (determined by pull-high options:
nibble option). The PE2 is pin-shared with SDI. SDI is Serial interface serial
input.
PE3/SDO
I/O
Pull-high
(nibble option)
Bidirectional I/O lines. Software instructions determine the CMOS output or
Schmitt trigger input with pull-high resistor (determined by pull-high options:
nibble option). The PE3 is pin-shared with SDO. SDO is a Serial interface
serial output.
PE4~PE5
I/O
Pull-high
(nibble option)
Bidirectional I/O lines. Software instructions determine the CMOS output or
Schmitt trigger input with pull-high resistor (determined by pull-high options:
nibble option).
I
¾
RES
Schmitt trigger reset input, active low
VSS
¾
¾
Negative power supply, ground
AVSS
¾
¾
ADC negative power supply, ground
VDD
¾
¾
Positive power supply
AVDD
¾
¾
ADC positive power supply, AVDD should be externally connected to VDD.
OSC1
OSC2
I
O
¾
OSC1 and OSC2 are connected to a 6MHz or 12MHz Crystal/resonator (determined by software instructions) for the internal system clock.
V33O
O
¾
3.3V regulator output.
UDP
I/O
¾
UDP is USBD+ line
USB function is controlled by software control register.
UDN
I/O
¾
UDN is USBD- line
USB function is controlled by software control register.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
IOL Total ..............................................................150mA
Total Power Dissipation .....................................500mW
Operating Temperature...........................-40°C to 85°C
IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
VDD
VDD
Operating Voltage
¾
IDD1
Operating Current (6MHz Crystal)
5V
IDD2
Operating Current (12MHz Crystal)
ISTB1
Standby Current (WDT Enabled)
ISTB2
Rev. 1.20
Standby Current (WDT Disabled)
3V
5V
3V
5V
3V
5V
Conditions
Min.
Typ.
Max.
Unit
fSYS=6MHz
2.2
¾
5.5
V
fSYS=12MHz
2.7
¾
5.5
V
No load, fSYS=6MHz
¾
6.5
12
mA
¾
3.6
10
mA
¾
7.5
16
mA
No load, system HALT,
USB suspended
¾
¾
5
mA
¾
¾
10
mA
No load, system HALT,
USB suspended
¾
¾
1
mA
¾
¾
2
mA
No load, fSYS=12MHz
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November 1, 2006
HT46RB50
Symbol
Parameter
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
¾
150
200
mA
ISTB3
Standby Current (WDT Disabled)
5V
No load, system HALT,
USB transceiver and
3.3V regulator On
VIL1
Input Low Voltage for I/O Ports
¾
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O Ports
¾
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
4
8
¾
mA
10
20
¾
mA
-2
-4
¾
mA
-5
-10
¾
mA
VIH2
IOL
I/O Port Sink Current
3V
5V
3V
VOL=0.1VDD
IOH
I/O Port Source Current
RPH
Pull-high Resistance
VLVR
Low Voltage Reset Voltage
¾
Option 3.0V
VV33O
3.3V Regulator Output
5V
IV33O=-5mA
EAD
A/D Conversion Error
¾
¾
5V
VOH=0.9VDD
3V
¾
5V
20
60
100
kW
10
30
50
kW
2.7
3
3.3
V
3
3.3
3.6
V
¾
±0.5
±1
LSB
A.C. Characteristics
Symbol
Parameter
fSYS
System Clock
fTIMER
Timer I/P Frequency (TMR0/TMR1)
tWDTOSC
Watchdog Oscillator Period
tRES
External Reset Low Pulse Width
Ta=25°C
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
¾
2.2V~5.5V
400
¾
6000
kHz
¾
3.3V~5.5V
400
¾
12000
kHz
¾
2.2V~5.5V
0
¾
6000
kHz
¾
3.3V~5.5V
0
¾
12000
kHz
3V
¾
45
90
180
ms
5V
¾
32
65
130
ms
¾
¾
1
¾
¾
ms
¾
1024
¾
*tSYS
tSST
System Start-up Timer Period
¾
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
tAD
A/D Clock Period
¾
¾
1
¾
¾
ms
tADC
A/D Conversion Time
¾
¾
¾
76
¾
tAD
tADCS
A/D Sampling Time
¾
¾
¾
32
¾
tAD
Wake-up from HALT
Note: *tSYS=1/fSYS
Rev. 1.20
5
November 1, 2006
HT46RB50
Functional Description
points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading a PCL register, a
subroutine call, an initial reset, an internal interrupt, an
external interrupt, or returning from a subroutine, the PC
manages the program transfer by loading the address
corresponding to each instruction.
Execution Flow
The system clock is derived from a crystal. It is internally
divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way
that a fetch takes one instruction cycle while decoding
and execution takes the next instruction cycle. The
pipelining scheme makes it possible for each instruction
to be effectively executed in a cycle. If an instruction
changes the value of the program counter, two cycles
are required to complete the instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get a proper instruction, otherwise proceed to the next instruction.
Program Counter - PC
The lower byte of the PC (PCL) is a readable and
writeable register (06H). Moving data into the PCL performs a short jump. The destination is within 256 locations.
The program counter (PC) is 12 bits wide and it controls
the sequence in which the instructions stored in the program ROM are executed. The contents of the PC can
specify a maximum of 4096 addresses. After accessing
a program memory word to fetch an instruction code,
the value of the PC is incremented by 1. The PC then
S y s te m
C lo c k
T 1
T 2
T 3
T 4
T 1
When a control transfer takes place, an additional
dummy cycle is required.
T 2
P C
P C
T 3
T 4
T 1
T 2
T 3
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
T 4
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
External Interrupt
0
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter 0 Overflow
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter 1 Overflow
0
0
0
0
0
0
0
0
1
1
0
0
USB Interrupt
0
0
0
0
0
0
0
1
0
0
0
0
A/D Converter Interrupt
0
0
0
0
0
0
0
1
0
1
0
0
Serial Interface Interrupt
0
0
0
0
0
0
0
1
1
0
0
0
Skip
Program Counter+2
Loading PCL
*11
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:
*11~*0: Program counter bits
#11~#0: Instruction code bits
Rev. 1.20
S11~S0: Stack register bits
@7~@0: PCL bits
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November 1, 2006
HT46RB50
· Location 00CH
Program Memory - EPROM
Location 00CH is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and if the
interrupt is enabled and the stack is not full, the program begins execution at location 00CH.
The program memory (EPROM) is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized
into 4096´15 bits which are addressed by the Program
Counter and table pointer.
· Location 010H
Certain locations in the ROM are reserved for special
usage:
Location 010H is reserved for the USB interrupt service program. If the USB interrupt is activated, the interrupt is enabled and the stack is not full, the program
begins execution at location 010H.
· Location 000H
Location 000H is reserved for program initialization.
After a chip reset, the program always begins execution at this location.
· Location 014H
Location 014H is reserved for the A/D converter interrupt service program. If an A/D converter interrupt results from an end of A/D conversion, and the stack is
not full, the program begins execution at location
014H.
· Location 004H
Location 004H is reserved for the external interrupt
service program. If the INT input pin is activated, and
the interrupt is enabled, and the stack is not full, the
program begins execution at location 004H.
· Location 018H
Location 018H is reserved when 8 bits data have been
received or transmitted successfully from serial interface, and the related interrupts are enabled, and the
stack is not full, the program begins execution at location 018H.
· Location 008H
Location 008H is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the
interrupt is enabled and the stack is not full, the program begins execution at location 008H.
0 0 0 H
0 0 C H
Any location in the ROM can be used as a look-up table. The instructions ²TABRDC [m]² (the current page,
page=256 words) and ²TABRDL [m]² (the last page)
transfer the contents of the lower-order byte to the
specified data memory, and the contents of the
higher-order byte to TBLH (Table Higher-order byte
register) (08H). Only the destination of the lower-order
byte in the table is well-defined; the other bits of the table word are all transferred to the lower portion of
TBLH. The TBLH is read only, and the table pointer
(TBLP) is a read/write register (07H), indicating the table location. Before accessing the table, the location
should be placed in TBLP. All the table related instructions require 2 cycles to complete the operation.
These areas may function as a normal ROM depending upon users requirements.
D e v ic e In itia liz a tio n P r o g r a m
0 0 4 H
0 0 8 H
· Table location
E x te r n a l In te r r u p t S u b r o u tin e
T im e r /E v e n t C o u n te r 0 In te r r u p t S u b r o u tin e
T im e r /E v e n t C o u n te r 1 In te r r u p t S u b r o u tin e
0 1 0 H
0 1 4 H
0 1 8 H
U S B In te r r u p t S u b r o u tin e
A /D
C o n v e r te r In te r r u p t S u b r o u tin e
P ro g ra m
M e m o ry
S e r ia l In te r fa c e In te r r u p t S u b r o u tin e
n 0 0 H
L o o k - u p T a b le ( 2 5 6 w o r d s )
n F F H
Stack Register - STACK
This is a special part of the memory which is used to
save the contents of the Program Counter only. The
stack is organized into 6 levels and is neither part of the
data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
L o o k - u p T a b le ( 2 5 6 w o r d s )
F F F H
1 5 B its
N o te : n ra n g e s fro m
0 to F
Program Memory
Table Location
Instruction
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note: *11~*0: Table location bits
@7~@0: Table pointer bits
Rev. 1.20
P11~P8: Current program counter bits
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November 1, 2006
HT46RB50
0 0 H
At a subroutine call or an interrupt acknowledgment, the
contents of the program counter are pushed onto the
stack. At the end of the subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the
program counter is restored to its previous value from
the stack. After a chip reset, the SP will point to the top of
the stack.
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
0 4 H
0 5 H
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt is
serviced. This feature prevents stack overflow, allowing
the programmer to use the structure more easily. If the
stack is full and a ²CALL² is subsequently executed,
stack overflow occurs and the first entry will be lost (only
the most recent 6 return addresses are stored).
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
0 A H
S T A T U S
0 B H
IN T C 0
0 C H
Data Memory - RAM
The data memory (RAM) is designed with 238´8 bits,
and is divided into two functional groups, namely; special function registers (46´8 bits) and general purpose
data memory (192´8 bits) most of which are readable/writeable, although some are read only.
0 D H
T M R 0
0 E H
T M R 0 C
0 F H
T M R 1 H
1 0 H
T M R 1 L
1 1 H
T M R 1 C
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 6 H
P C
1 7 H
P C C
1 8 H
P D
1 9 H
P D C
1 A H
P E
1 B H
P E C
1 C H
The unused space before 40H is reserved for future expanded usage and reading these locations will get
²00H². The general purpose data memory, addressed
from 40H to FFH, is used for data and control information under instruction commands.
1 D H
1 E H
IN T C 1
S p e c ia l P u r p o s e
D a ta M e m o ry
1 F H
2 0 H
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the
data memory can be set and reset by ²SET [m].i² and
²CLR [m].i². They are also indirectly accessible through
memory pointer registers (MP0;01H/MP1;03H).
Indirect Addressing Register
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write operation of [00H] and [02H] accesses the RAM pointed to
by MP0 (01H) and MP1 (03H) respectively. Reading location 00H or 02H indirectly returns the result 00H.
While, writing into it, indirectly leads to no operation. The
function of data movement between two indirect addressing registers is not supported. The memory pointer
registers, MP0 and MP1, are both 8-bit registers used to
access the RAM by combining corresponding indirect
addressing registers.
U S C
2 1 H
U S R
2 2 H
U C C
2 3 H
A W R
2 4 H
S T A L L
2 5 H
S IE S
2 6 H
M IS C
2 7 H
S E T IO
2 8 H
F IF O 0
2 9 H
F IF O 1
2 A H
F IF O 2
2 B H
F IF O 3
2 C H
2 D H
2 E H
2 F H
3 0 H
A D R L
3 1 H
A D R H
3 2 H
A D C R
3 3 H
A C S R
3 4 H
P W M 0
3 5 H
P W M 1
3 6 H
3 7 H
Accumulator - ACC
3 8 H
S B C R
3 9 H
3 A H
S B D R
3 F H
4 0 H
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the RAM and capable
of operating with immediate data. The data movement
between two data memory locations must pass through
the accumulator.
Rev. 1.20
In d ir e c t A d d r e s s in g R e g is te r 0
0 1 H
F F H
G e n e ra l P u rp o s e
D a ta M e m o ry
(1 9 2 B y te s )
: U n u s e d
R e a d a s "0 0 "
RAM Mapping
8
November 1, 2006
HT46RB50
Arithmetic and Logic Unit - ALU
Interrupts
This circuit performs 8-bit arithmetic and logic operations.
The ALU provides the following functions:
This device provides external interrupts (INT pin interrupt, A/D Converter interrupt, Serial Interface interrupt)
and internal timer/event counter interrupts. The Interrupt
Control Register0 (INTC0;0BH) and interrupt control
register1 (INTC1:1EH) both contain the interrupt control
bits that are used to set the enable/disable status and interrupt request flags.
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ, etc.)
Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the
EMI bit and the corresponding bit of the INTC0 or INTC1
may be set to allow interrupt nesting. If the stack is full,
the interrupt request will not be acknowledged, even if
the related interrupt is enabled, until the Stack Pointer is
decremented. If immediate service is desired, the stack
must be prevented from becoming full.
The ALU not only saves the results of a data operation
but also changes the status register.
Status Register - STATUS
The status register (0AH) is 8 bits wide and contains, a
carry flag (C), an auxiliary carry flag (AC), a zero flag (Z),
an overflow flag (OV), a power down flag (PDF), and a
Watchdog time-out flag (TO). It also records the status information and controls the operation sequence. Except
for the TO and PDF flags, bits in the status register can be
altered by instructions similar to other registers. Data
written into the status register does not alter the TO or
PDF flags. Operations related to the status register, however, may yield different results from those intended. The
TO and PDF flags can only be changed by a Watchdog
Timer overflow, chip power-up, or clearing the Watchdog
Timer and executing the ²HALT² instruction.
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified location in the program memory. Only the program counter is pushed onto
the stack. If the contents of the register or status register
(STATUS) are altered by the interrupt service program
which corrupts the desired control sequence, the contents should be saved in advance.
The Z, OV, AC, and C flags reflect the status of the latest
operations. On entering the interrupt sequence or executing a subroutine call, the status register will not be
automatically pushed onto the stack. If the contents of
the status is important, and if the subroutine is likely to
corrupt the status register, the programmer should take
precautions and save it properly.
External interrupts can are triggered by a falling edge
transition of INT), and the related interrupt request flag
(EIF; bit4 of the INTC0) is set as well. After the interrupt
is enabled, the stack is not full, and the external interrupt
is active (INT pin), a subroutine call at location 04H occurs. The interrupt flag (EIF) and EMI bits are all cleared
to disable other maskable interrupts.
Bit No.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation, otherwise C is cleared. C is also affected by a rotate through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction, otherwise AC is cleared.
2
Z
3
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa, otherwise OV is cleared.
4
PDF
PDF is cleared by a system power-up or executing the ²CLR WDT² instruction.
PDF is set by executing the ²HALT² instruction.
5
TO
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction.
TO is set by a WDT time-out.
6~7
¾
Unused bit, read as ²0²
Z is set if the result of an arithmetic or logic operation is zero, otherwise Z is cleared.
Status (0AH) Register
Rev. 1.20
9
November 1, 2006
HT46RB50
The internal Timer/Event Counter 0 interrupt is initialized
by setting the Timer/Event Counter 0 interrupt request
flag (bit 5 of the INTC0), caused by a Timer 0 overflow.
When the interrupt is enabled, the stack is not full and the
T0F bit is set, a subroutine call to location 08H will occur.
The related interrupt request flag (T0F) will be reset and
the EMI bit cleared to disable further interrupts.
rupt is triggered. So user can easily determine which FIFO
is accessed. When the interrupt has been served, the corresponding bit should be cleared by firmware. When the
HT46RB50 receives a USB Suspend signal from the Host
PC, the suspend line (bit0 of the USC) of the HT46RB50 is
set and a USB interrupt is also triggered.
Also when the HT46RB50 receives a Resume signal
from the Host PC, the resume line (bit3 of the ) of the
HT46RB50 is set and a USB interrupt is triggered.
The internal Timer/Event Counter 1 interrupt is initialized
by setting the Timer/Event Counter 1 interrupt request
flag (bit 6 of the INTC0), caused by a Timer 1 overflow.
When the interrupt is enabled, the stack is not full and the
T1F is set, a subroutine call to location 0CH will occur.
The related interrupt request flag (T1F) will be reset and
the EMI bit cleared to disable further interrupts.
Whenever a USB reset signal is detected, a USB interrupt is triggered.
The A/D converter interrupt is controlled by setting the
A/D interrupt control bit (EADI; bit 1 of the INTC1). When
the interrupt is enabled, the stack is not full and the A/D
conversion is finished, a subroutine call to location 14H
will occur. The related interrupt request flag ADF (bit5 of
the INTC1) will be reset and the EMI bit cleared to disable further interrupts.
USB interrupts are triggered by the following USB
events and the related interrupt request flag (USBF; bit
4 of the INTC1) will be set.
· The access of the corresponding USB FIFO from PC
· The USB suspend signal from the PC
The serial interface interrupt is indicated by the interrupt
flag (SIF; bit 6 of the INTC1), that is caused by a reception or a complete transmission of an 8-bit data between
the HT46RB50 and an external device. The serial interface interrupt is controlled by setting the Serial interface
interrupt control bit (ESII ; bit 2 of the INTC1). After the
interrupt is enabled (by setting SBEN; bit 4 of the
SBCR), and the stack is not full and the SIF is set, a subroutine call to location 18H occurs.
· The USB resume signal from the PC
· USB Reset signal
When the interrupt is enabled, the stack is not full and
the external interrupt is active, a subroutine call to location 10H will occur. The interrupt request flag (USBF)
and EMI bits will be cleared to disable other interrupts.
When PC Host access the FIFO of the HT46RB50, the
corresponding request bit of USR is set, and a USB interBit No.
Label
Function
0
EMI
Controls the master (global) interrupt (1= enable; 0= disable)
1
EEI
Controls the external interrupt (1= enable; 0= disable)
2
ET0I
Controls the Timer/Event Counter 0 interrupt (1= enable; 0= disable)
3
ET1I
Controls the Timer/Event Counter 1 interrupt (1= enable; 0= disable)
4
EIF
External interrupt request flag (1= active; 0= inactive)
5
T0F
Internal Timer/Event Counter 0 request flag (1= active; 0= inactive)
6
T1F
Internal Timer/Event Counter 1 request flag (1= active; 0= inactive)
7
¾
Unused bit, read as ²0²
INTC0 (0BH) Register
Bit No.
Label
Function
0
EUI
1
EADI
Control the A/D converter interrupt (1= enable; 0=disable)
2
ESII
Control Serial interface interrupt (1= enable; 0= disable)
Control the USB interrupt (1= enable; 0= disable)
3, 7
¾
4
USBF
Unused bit, read as ²0²
USB interrupt request flag (1= active; 0= inactive)
5
ADF
A/D converter request flag (1= active; 0= inactive)
6
SIF
Serial interface interrupt request flag (1= active; 0= inactive)
INTC1 (1EH) Register
Rev. 1.20
10
November 1, 2006
HT46RB50
The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if
the system enters a power down mode and the system
clock is stopped, but the WDT oscillator still works. The
WDT oscillator can be disabled by ROM code option to
conserve power.
During the execution of an interrupt subroutine, other interrupt acknowledge signals are held until the ²RETI² instruction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, ²RET² or ²RETI²
may be invoked. RETI will set the EMI bit to enable an
interrupt service, but RET will not.
Watchdog Timer - WDT
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Interrupt Source
Priority
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4) determined by options. This
timer is designed to prevent a software malfunction or
sequence jumping to an unknown location with unpredictable results. The watchdog timer can be disabled by
options. If the watchdog timer is disabled, all executions
related to the WDT results in no operation.
Vector
External Interrupt
1
04H
Timer/Event Counter 0 Overflow
2
08H
Timer/Event Counter 1 Overflow
3
0CH
USB Interrupt
4
10H
A/D Converter Interrupt
5
14H
Serial Interface Interrupt
6
18H
Once an internal WDT oscillator (RC oscillator with a period of 65ms, normally at 5V) is selected, it is divided by
212~215 (by option to get the WDT time-out period). The
WDT time-out minimum period is 300ms~600ms. This
time-out period may vary with temperature, VDD and
process variations. By selection from the WDT option,
longer time-out periods can be realized. If the WDT
time-out is selected as 215, the maximum time-out period is divided by 215~216 which about 2.3s~4.7s.
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only one
stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged
once the ²CALL² operates in the interrupt subroutine.
If the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operates in the
same manner except that in the HALT state the WDT
may stop counting and lose its protecting purpose. In
this situation the logic can only be restarted by external
logic. If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock.
Oscillator Configuration
There is an oscillator circuit in the microcontroller.
The WDT overflow under normal operation will initialize
a ²chip reset² and set the status bit TO. Whereas in the
HALT mode, the overflow will initialize a ²warm reset²
and only the Program Counter and SP are reset to zero.
To clear the contents of WDT, three methods are
adopted; external reset (a low level to RES), software instructions, or a HALT instruction. The software instructions include ²CLR WDT² and the other set ²CLR
WDT1² and ²CLR WDT2². Of these two types of instruction, only one can be active depending on the option ²CLR WDT times selection option². If the ²CLR WDT² is
selected (i.e. CLRWDT times equal one), any execution
of the ²CLR WDT² instruction will clear the WDT. In case
²CLR WDT1² and ²CLR WDT2² are chosen (i.e.
²CLRWDT² times equal two), these two instructions
must be executed to clear the WDT, otherwise, the WDT
may reset the chip due to time-out.
O S C 1
O S C 2
C r y s ta l O s c illa to r
System Oscillator
This oscillator is designed for system clocks. The HALT
mode stops the system oscillator and ignores an external signal to conserve power.
A crystal across OSC1 and OSC2 is needed to provide
the feedback and phase shift required for the oscillator.
No other external components are required. Instead of a
crystal, a resonator can also be connected between
OSC1 and OSC2 to get a frequency reference, but two
external capacitors in OSC1 and OSC2 are required.
Rev. 1.20
11
November 1, 2006
HT46RB50
S y s te m
C lo c k /4
W D T
O S C
(1 2 k H z )
R O M
C o d e
o p tio n
fW
D T
D iv id e r
fW
D T
/2
8
W D T P r e s c a le r
C K
M a s k O p tio n
R
T
C K
R
T
W D T C le a r
T im e - o
fs /2 1 5 ~
fs /2 1 4 ~
fs /2 1 3 ~
fs /2 1 2 ~
u t R e s e t
fs /2 1 6
fs /2 1 5
fs /2 1 4
fs /2 1 3
Watchdog Timer
Power Down Operation - HALT
period) to resume normal operation. In other words, a
dummy period is inserted after wake-up. If the wake-up
results from an interrupt acknowledge, the actual interrupt subroutine execution is delayed by more than one
cycle. However, if the wake-up results in the next instruction execution, this will be executed immediately
after the dummy period is finished.
The HALT mode is initialized by the ²HALT² instruction
and results in the following:
· The system oscillator is turned off but the WDT oscil-
lator keeps running (if the WDT oscillator or the real
time clock is selected).
· The contents of the on-chip RAM and registers remain
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
unchanged.
· The WDT will be cleared and start recounting (if the
WDT clock source is from the WDT oscillator or the
real time clock).
Reset
· All of the I/O ports maintain their original status.
There are three ways in which a reset may occur:
· The PDF flag is set and the TO flag is cleared.
· RES reset during normal operation
· RES reset during HALT
The system can quit the HALT mode in many ways, by
an external reset, an interrupt, an external falling edge
signal on Port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow performs a ²warm reset². After examining the TO and PDF
flags, the cause for a chip reset can be determined. The
PDF flag is cleared by a system power-up or by executing the ²CLR WDT² instruction and is set when executing the ²HALT² instruction. On the other hand, the TO
flag is set if the WDT time-out occurs, and causes a
wake-up that only resets the Program Counter and SP;
and leaves the others in their original status.
· WDT time-out reset during normal operation
The WDT time-out during HALT differs from other chip
reset conditions, for it can perform a ²warm reset² that
resets only the Program Counter and Stack Pointer,
leaving the other circuits in their original state. Some
registers remain unaffected during any other reset conditions. Most registers are reset to the ²initial condition²
when the reset conditions are met. Examining the
PDF and TO flags, the program can distinguish between
different ²chip resets².
The Port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit
in Port A can be independently selected to wake-up the
device by option. Awakening from an I/O port stimulus,
the program will resume execution of the next instruction. If it awakens from an interrupt, two sequences may
occur. If the related interrupt is disabled or the interrupt
is enabled but the stack is full, the program will resume
execution at the next instruction. But if the interrupt is
enabled and the stack is not full, a regular interrupt response takes place. When an interrupt request flag is
set to ²1² before entering the HALT mode, the wake-up
function of the related interrupt will be disabled. If a
wake-up event occurs, it takes 1024 fSYS (system clock
Rev. 1.20
TO
PDF
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up at HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up at HALT
Note: ²u² stands for ²unchanged²
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the system awakes from the HALT state or during power up.
12
November 1, 2006
HT46RB50
V
D D
V D D
0 .0 1 m F *
R E S
1 0 0 k W
tS
S T
+ tO
P D
S S T T im e - o u t
R E S
C h ip
R e s e t
1 0 k W
Reset Timing Chart
0 .1 m F *
Awaking from the HALT state or system power up, an
SST delay is added. An extra SST delay is added during
power up period, and any wake-up from HALT may enable only the SST delay. The functional unit chip reset
status are shown below.
Reset Circuit
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to
avoid noise interference.
Note:
H A L T
W D T
W D T
T im e - o u t
R e s e t
R E S
W a rm
R e s e t
E x te rn a l
C o ld
R e s e t
S S T
1 0 - b it R ip p le
C o u n te r
O S C 1
Program Counter
000H
Interrupt
Disable
Prescaler, Divider
Cleared
WDT
Clear. After master reset,
WDT begins counting
Timer/event Counter
Off
Input/output Ports
Input mode
Stack Pointer
Points to the top of the stack
P o w e r - o n D e te c tio n
Reset Configuration
The registers states are summarized in the following table.
Reset
(Power On)
WDT
Time-out
(Normal
Operation)
RES Reset
(Normal
Operation)
RES Reset
(HALT)
WDT
Time-out
(HALT)*
USB Reset
(Normal)
USB Reset
(HALT)
TMR0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
xxxx xxxx
xxxx xxxx
TMR0C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
00-0 1000
00-0 1000
TMR1H
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
xxxx xxxx
xxxx xxxx
TMR1L
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
xxxx xxxx
xxxx xxxx
TMR1C
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
00-0 1---
00-0 1---
Program
Counter
000H
000H
000H
000H
000H
000H
000H
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
-xxxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
--uu uuuu
--01 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
-000 0000
-000 0000
INTC1
-000 -000
-000 -000
-000 -000
-000 -000
-uuu -uuu
-000 -000
-000 -000
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
Register
Rev. 1.20
13
November 1, 2006
HT46RB50
Reset
(Power On)
WDT
Time-out
(Normal
Operation)
RES Reset
(Normal
Operation)
RES Reset
(HALT)
WDT
Time-out
(HALT)*
USB Reset
(Normal)
USB Reset
(HALT)
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PCC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PD
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PDC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PE
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PEC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
AWR
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
STALL
---- 1110
---- uuuu
---- 1110
---- 1110
---- uuuu
---- 1110
---- 1110
MISC
0xx- -000
uxx- -uuu
0xx- -000
0xx- -000
uxx- -uuu
000- -000
000- -000
SETIO
---- 1110
---- uuuu
---- 1110
---- 1110
---- uuuu
---- 1110
---- 1110
FIFO0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
FIFO1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
FIFO2
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
FIFO3
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
USC
1-00 0000
u-uu uuuu
1-00 0000
1-00 0000
u-uu uuuu
u-00 0100
u-00 0100
USR
--00 0000
--uu uuuu
--00 0000
--00 0000
--uu uuuu
--00 0000
--00 0000
UCC
-000 0000
-uuu uuuu
-000 0000
-000 0000
-uuu uuuu
-uu0 u000
-uu0 u000
SIES
0100 0000
uuuu uuuu
0100 0000
0100 0000
uuuu uuuu
0100 0000
0100 0000
Register
ADRL
xx-- ----
xx-- ----
xx-- ----
xx-- ----
uu-- ----
xx-- ----
xx-- ----
ADRH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
xxxx xxxx
xxxx xxxx
ADCR
0100 0000
0100 0000
0100 0000
0100 0000
uuuu uuuu
0100 0000
0100 0000
ACSR
1--- --00
1--- --00
1--- --00
1--- --00
u--- --uu
1--- --00
1--- --00
PWM0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
PWM1
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
SBCR
0110 0000
0110 0000
0110 0000
0110 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
SBDR
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
Note:
²*² stands for warm reset
²u² stands for unchanged
²x² stands for unknown
Rev. 1.20
14
November 1, 2006
HT46RB50
Timer/Event Counter
and the lower-order byte buffer, respectively. Reading
the TMR1L will read the contents of the lower-order byte
buffer. The TMR0C (TMR1C) is the Timer/Event Counter 0 (1) control register, which defines the operating
mode, counting enable or disable and an active edge.
Two Timer/Event Counters (TMR0, TMR1) are implemented in the microcontroller. The Timer/Event Counter
0 contains a 8-bit programmable count-up counter and
the clock may come from an external source or an internal clock source. An internal clock source comes from
fSYS. The Timer/Event Counter 1 contains a 16-bit programmable count-up counter and the clock may come
from an external source or an internal clock source. An
internal clock source comes from fSYS/4. The external
clock input allows the user to count external events,
measure time intervals or pulse widths, or generate an
accurate time base.
The T0M0, T0M1 (TMR0C) and T1M0, T1M1 (TMR1C)
bits define the operation mode. The event count mode is
used to count external events, which means that the
clock source is from an external (TMR0, TMR1) pin. The
timer mode functions as a normal timer with the clock
source coming from the internal selected clock source.
Finally, the pulse width measurement mode can be used
to count the high or low level duration of the external signal (TMR0, TMR1), and the counting is based on the internal selected clock source.
There are five registers related to the Timer/Event
Counter 0; TMR0 (0DH), TMR0C (0EH) and the
Timer/Event Counter 1; TMR1H (0FH), TMR1L (10H),
TMR1C (11H). For 16bits timer to Write data to TMR1L
will only put the written data to an internal lower-order
byte buffer (8-bit) and writing TMR1H will transfer the
specified data and the contents of the lower-order byte
buffer to TMR1H and TMR1L registers. The Timer/Event
Counter 1 preload register is changed by each writing
TMR1H operations. Reading TMR1H will latch the contents of TMR1H and TMR1L counters to the destination
In the event count or timer mode, the timer/event counter starts counting at the current contents in the
timer/event counter and ends at FFFFH(for 16 bits timer
is FFFFH, bit 8 bits timer will be FFH). Once an overflow
occurs, the counter is reloaded from the timer/event
counter preload register, and generates an interrupt request flag (T0F; bit 5 of the INTC0, T1F; bit 6 of the
INTC0).
P W M
(6 + 2 ) o r (7 + 1 )
C o m p a re
fS
Y S
T o P D 0 /P D 1 C ir c u it
8 - s ta g e P r e s c a le r
f IN
8 -1 M U X
T 0 D 2 ~ T 0 D 0
T
D a ta B u s
T M 1
T M 0
T M R 0
8 - B it T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
R e lo a d
T E
T M 1
T M 0
T O N
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
8 - B it T im e r /E v e n t C o u n te r
(T M R 0 )
O v e r flo w
to In te rru p t
Timer/Event Counter 0
fS
Y S
/4
f IN
D a ta B u s
T
T M 1
T M 0
T M R 1
1 6 - B it T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
R e lo a d
T E
T M 1
T M 0
T O N
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
1 6 - B it T im e r /E v e n t C o u n te r
(T M R 1 H /T M R 1 L )
O v e r flo w
to In te rru p t
Timer/Event Counter 1
Rev. 1.20
15
November 1, 2006
HT46RB50
In the case of timer/event counter OFF condition, writing
data to the timer/event counter preload register also reloads that data to the timer/event counter. But if the
timer/event counter is turned on, data written to the
timer/event counter is kept only in the timer/event counter preload register. The timer/event counter still continues its operation until an overflow occurs.
In the pulse width measurement mode with the values of
the T0ON/T1ON and T0E/T1E bits equal to 1, after the
TMR0 (TMR1) has received a transient from low to high
(or high to low if the T0E/T1E bit is ²0²), it will start counting until the TMR0 (TMR1) returns to the original level
and resets the T0ON/T1ON. The measured result remains in the timer/event counter even if the activated
transient occurs again. In other words, only 1-cycle
measurement can be made until the T0ON/T1ON is set.
The cycle measurement will re-function as long as it receives further transient pulse. In this operation mode,
the timer/event counter begins counting not according
to the logic level but to the transient edges. In the case of
counter overflows, the counter is reloaded from the
timer/event counter register and issues an interrupt request, as in the other two modes, i.e., event and timer
modes.
When the timer/event counter (reading TMR0/TMR1) is
read, the clock is blocked to avoid errors, as this may results in a counting error. Blocking of the clock should be
taken into account by the programmer. It is strongly recommended to load a desired value into the TMR0/TMR1
register first, before turning on the related timer/event
counter, for proper operation since the initial value of
TMR0/TMR1 is unknown. Due to the timer/event
scheme, the programmer should pay special attention
on the instruction to enable then disable the timer for the
first time, whenever there is a need to use the
timer/event function, to avoid unpredictable result. After
this procedure, the timer/event function can be operated
normally.
To enable the counting operation, the Timer ON bit
(T0ON: bit 4 of the TMR0C; T10N: bit 4 of the TMR1C)
should be set to 1. In the pulse width measurement
mode, the T0ON/T1ON is automatically cleared after
the measurement cycle is completed. But in the other
two modes, the T0ON/T1ON can only be reset by instructions. The overflow of the Timer/Event Counter 0/1
is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ET0I or ET1I disables the related interrupt service.
Bit No.
Label
0
1
2
T0PSC0
T0PSC1
T0PSC2
3
T0E
4
T0ON
5
¾
6
7
The bit0~bit2 of the TMR0C can be used to define the
pre-scaling stages of the internal clock sources of
timer/event counter. The definitions are as shown. The
timer prescaler is also used as the PWM counter.
T0M0
T0M1
Function
Defines the prescaler stages, T0PSC2, T0PSC1, T0PSC0=
000: fINT=fSYS
001: fINT=fSYS/2
010: fINT=fSYS/4
011: fINT=fSYS/8
100: fINT=fSYS/16
101: fINT=fSYS/32
110: fINT=fSYS/64
111: fINT=fSYS/128
Defines the TMR active edge of the timer/ event counter
(0=active on low to high; 1=active on high to low)
Enable/disable timer counting (0=disable; 1=enable)
Unused bit, read as ²0²
Defines the operating mode, T0M1, T0M0:
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR0C (0EH) Register
Rev. 1.20
16
November 1, 2006
HT46RB50
Bit No.
Label
0~2, 5
¾
3
T1E
4
T1ON
Enable/disable timer counting (0=disable; 1=enable)
T1M0
T1M1
Defines the operating mode, T1M1, T1M0:
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
6
7
Function
Unused bit, read as ²0²
Defines the TMR active edge of the timer/ event counter
(0=active on low to high; 1=active on high to low)
TMR1C (11H) Register
depends on the control register. If the control register bit
is ²1² the input will read the pad state. If the control register bit is ²0² the contents of the latches will move to the
internal bus. The latter is possible in the ²Read-modifywrite² instruction. For output function, CMOS is the only
configuration. These control registers are mapped to locations 13H, 15H, 17H, 19H and 1BH.
Input/Output Ports
There are 38 bidirectional input/output lines in the
microcontroller, labeled from PA to PE, which are
mapped to the data memory of [12H], [14H], [16H],
[18H] and [1A] respectively. All of these I/O ports can be
used for input and output operations. For input operation, these ports are non-latching, that is, the inputs
must be ready at the T2 rising edge of instruction ²MOV
A,[m]² (m=12H, 14H, 16H, 18H or 1A). For output operation, all the data is latched and remains unchanged until the output latch is rewritten.
After a chip reset, these input/output lines remain at high
levels or floating state (depending on the pull-high options). Each bit of these input/output latches can be set
or cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H,
16H, 18H or 1AH ) instructions.
Each I/O line has its own control register (PAC, PBC,
PCC, PDC, PEC) to control the input/output configuration. With this control register, CMOS output or Schmitt
trigger input with or without pull-high resistor structures
can be reconfigured dynamically under software control.
To function as an input, the corresponding latch of the
control register must write a ²1². The input source also
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
V
D a ta B u s
W r ite C o n tr o l R e g is te r
C o n tr o l B it
Q
D
P U
P A 0
P B 0
P C 0
P C 1
P C 2
P C 3
P D 0
P D 2
P E 0
P E 1
P E 2
P E 3
P E 4
Q
C K
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
D a ta B it
Q
D
C K
S
Q
M
P D 0 ~ P D 3
P W M 0 ~ P W M 3
M
R e a d D a ta R e g is te r
S y s te m
W a k e -u p
( P A o n ly )
U
D D
U
~ P
/A
/IN
/T
/T
~ P
/P
~ P
/S
/C
/S
/S
~ P
A 7
N 0 ~ P B 7 /A N 7
T
M R 0
M R 1
C 7
W M 0 ~ P D 1 /P W M 1
D 7
C S
L K
D I
D O
E 5
X
M a s k O p tio n
X
M a s k O p tio n
IN T fo r P C 0
T M R 0 fo r P C 1
T M R 1 fo r P C 2
Input/Output Ports
Rev. 1.20
17
November 1, 2006
HT46RB50
A (6+2) bits mode PWM cycle is divided into four modulation cycles (modulation cycle 0~modulation cycle 3).
Each modulation cycle has 64 PWM input clock period.
In a (6+2) bit PWM function, the contents of the PWM
register is divided into two groups. Group 1 of the PWM
register is denoted by DC which is the value of
PWM.7~PWM.2.
Each line of Port A has the capability of waking-up the
device.
It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
to avoid consuming power under input floating state.
Pulse Width Modulator - PWM
Group 2 is denoted by AC which is the value of
PWM.1~PWM.0.
The microcontroller provides 2 channels (6+2)/(7+1)
(depending on options) bits PWM output shared with
PD0/PD1. The data register of the PWM channels are
denoted as PWM0 (34H) and PWM1 (35H). The frequency source of the PWM counter comes from fSYS.
There are four 8-bit PWM registers. The waveforms of
the PWM outputs are as shown. Once the PD0/PD1 are
selected as the PWM outputs and the output function of
PD0/PD1 are enabled (PDC.0/PDC.1=²0²), writing a ²1²
to PD0/PD1 data register will enable the PWM output
function and writing a ²0² will force the PD0/PD1 to
remain at ²0².
fS
In a (6+2) bits mode PWM cycle, the duty cycle of each
modulation cycle is shown in the table.
Parameter
AC (0~3)
Duty Cycle
i<AC
DC+1
64
i³AC
DC
64
Modulation cycle i
(i=0~3)
/2
Y S
[P W M ] = 1 0 0
P W M
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 6 /6 4
[P W M ] = 1 0 1
P W M
[P W M ] = 1 0 2
P W M
[P W M ] = 1 0 3
P W M
2 6 /6 4
P W M
m o d u la tio n p e r io d : 6 4 /fS
M o d u la tio n c y c le 0
Y S
M o d u la tio n c y c le 1
P W M
M o d u la tio n c y c le 2
c y c le : 2 5 6 /fS
M o d u la tio n c y c le 3
M o d u la tio n c y c le 0
Y S
(6+2) PWM Mode
fS
Y S
/2
[P W M ] = 1 0 0
P W M
5 0 /1 2 8
5 0 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 2 /1 2 8
[P W M ] = 1 0 1
P W M
[P W M ] = 1 0 2
P W M
[P W M ] = 1 0 3
P W M
5 2 /1 2 8
P W M
m o d u la tio n p e r io d : 1 2 8 /fS
Y S
M o d u la tio n c y c le 0
M o d u la tio n c y c le 1
P W M
c y c le : 2 5 6 /fS
M o d u la tio n c y c le 0
Y S
(7+1) PWM Mode
Rev. 1.20
18
November 1, 2006
HT46RB50
bit of the ADCR is used to begin the conversion of the
A/D converter. Giving START bit a rising edge and falling edge means that the A/D conversion has started. In
order to ensure that A/D conversion is completed, the
START bit should remain at ²0² until the EOCB is
cleared to ²0² (end of A/D conversion).
A (7+1) bits mode PWM cycle is divided into two modulation cycles (modulation cycle 0~modulation cycle 1).
Each modulation cycle has 128 PWM input clock period.
In a (7+1) bits PWM function, the contents of the PWM
register is divided into two groups. Group 1 of the PWM
register is denoted by DC which is the value of
PWM.7~PWM.1.
Bit 7 of the ACSR register is used for test purposes only
and must not be used for other purposes by the application program. Bit1 and bit0 of the ACSR register are
used to select the A/D clock source.
Group 2 is denoted by AC which is the value of PWM.0.
In a (7+1) bits mode PWM cycle, the duty cycle of each
modulation cycle is shown in the table.
Parameter
AC (0~1)
Modulation cycle i
(i=0~1)
i<AC
i³AC
When the A/D conversion has completed, the A/D interrupt request flag will be set. The EOCB bit is set to ²1²
when the START bit is set from ²0² to ²1².
Duty Cycle
DC+1
128
DC
128
Important Note for A/D initialisation:
Special care must be taken to initialise the A/D converter each time the Port B A/D channel selection bits
are modified, otherwise the EOCB flag may be in an undefined condition. An A/D initialisation is implemented
by setting the START bit high and then clearing it to zero
within 10 instruction cycles of the Port B channel selection bits being modified. Note that if the Port B channel
selection bits are all cleared to zero then an A/D initialisation is not required.
The modulation frequency, cycle frequency and cycle
duty of the PWM output signal are summarized in the
following table.
PWM
Modulation Frequency
fSYS/64 for (6+2) bits mode
fSYS/128 for (7+1) bits mode
PWM Cycle PWM Cycle
Frequency
Duty
fSYS/256
[PWM]/256
Bit No. Label
A/D Converter
This microcontroller has 8 channels and 10-bit resolution A/D (9-bit accuracy) converter. The reference voltage is VDD. The A/D converter contains 4 special
registers which are; ADRL (30H), ADRH (31H), ADCR
(32H) and ACSR (33H). The ADRH and ADRL are A/D
result register higher-order byte and lower-order byte
and are read-only. After the A/D conversion is completed, the ADRH and ADRL should be read to get the
conversion result data. The ADCR is an A/D converter
control register, which defines the A/D channel number,
analog channel select, start A/D conversion control bit
and end of A/D conversion flag. If users want to start an
A/D conversion, first, define PB configuration, select the
converted analog channel, and give START bit a raising
edge and falling edge (0®1®0). At the end of A/D conversion, the EOCB bit is cleared and an A/D converter
interrupt occurs (if the A/D converter interrupt is enabled). The ACSR is A/D clock setting register, which is
used to select the A/D clock source.
0
1
2~6
7
¾
TEST
Unused bit, read as ²0²
For test mode used only
ACSR (33H) Register
Bit No. Label
The A/D converter control register is used to control the
A/D converter. The bit2~bit0 of the ADCR are used to
select an analog input channel. There¢s a total of eight
channels to select. The bit5~bit3 of the ADCR are used
to set PB configurations. PB can be an analog input or
as digital I/O line determined by these 3 bits. Once a PB
line is selected as an analog input, the I/O functions and
pull-high resistor of this I/O line are disabled and the A/D
converter circuit is powered on. The EOCB bit (bit6 of
the ADCR) is end of A/D conversion flag. Check this bit
to know when A/D conversion is completed. The START
Rev. 1.20
Function
Selects the A/D converter clock source
00= system clock/2
ADCS0
01= system clock/8
ADCS1
10= system clock/32
11= Undefined
Function
0
1
2
ACS0
ACS1
ACS2
Defines the analog channel select
3
4
5
PCR0
PCR1
PCR2
Defines the Port B configuration select. If PCR0, PCR1 and PCR2 are all
zero, the ADC circuit is powered off to
reduce power consumption
6
EOCB
Indicates end of A/D conversion.
(0= end of A/D conversion)
Each time bits 3~5 change state the
A/D should be initialised by issuing a
START signal, otherwise the EOCB
flag may have an undefined condition. See ²Important note for A/D initialisation².
7
Starts the A/D conversion.
0®1®0= Start
START
0®1= Reset A/D converter and set
EOCB to ²1².
ADCR (32H) Register
19
November 1, 2006
HT46RB50
ACS2
ACS1
ACS0
Analog Channel
0
0
0
AN0
0
0
1
AN1
0
1
0
AN2
0
1
1
AN3
1
0
0
AN4
1
0
1
AN5
1
1
0
AN6
1
1
1
AN7
When the A/D conversion is completed, the A/D interrupt request flag is set. The EOCB bit is set to ²1² when
the START bit is set from ²0² to ²1².
Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
ADRL
D1
D0
¾
¾
¾
¾
¾
¾
ADRH
D9
D8
D7
D6
D5
D4
D3
D2
Note:
D0~D9 is A/D conversion result data bit
LSB~MSB.
Analog Input Channel Selection
PCR2
PCR1
PCR0
7
6
5
4
3
2
1
0
0
0
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
0
0
1
PB7
PB6
PB5
PB4
PB3
PB2
PB1
AN0
0
1
0
PB7
PB6
PB5
PB4
PB3
PB2
AN1
AN0
0
1
1
PB7
PB6
PB5
PB4
PB3
AN2
AN1
AN0
1
0
0
PB7
PB6
PB5
PB4
AN3
AN2
AN1
AN0
1
0
1
PB7
PB6
PB5
AN4
AN3
AN2
AN1
AN0
1
1
0
PB7
PB6
AN5
AN4
AN3
AN2
AN1
AN0
1
1
1
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
Port B Configuration
M in im u m
o n e in s tr u c tio n c y c le n e e d e d , M a x im u m
te n in s tr u c tio n c y c le s a llo w e d
S T A R T
E O C B
A /D
tA
P C R 2 ~
P C R 0
s a m p lin g tim e
A /D
tA
D C S
0 0 0 B
s a m p lin g tim e
A /D
tA
D C S
1 0 0 B
1 0 0 B
s a m p lin g tim e
D C S
1 0 1 B
0 0 0 B
1 . P B p o rt s e tu p a s I/O s
2 . A /D c o n v e r te r is p o w e r e d o ff
to r e d u c e p o w e r c o n s u m p tio n
A C S 2 ~
A C S 0
0 0 0 B
P o w e r-o n
R e s e t
0 1 0 B
0 0 0 B
0 0 1 B
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
R e s e t A /D
c o n v e rte r
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
1 : D e fin e P B c o n fig u r a tio n
2 : S e le c t a n a lo g c h a n n e l
A /D
N o te :
A /D
tA D
tA
C S
D C
c lo c k m u s t b e fS
= 3 2 tA D
= 7 6 tA D
Y S
/2 , fS
tA D C
c o n v e r s io n tim e
Y S
/8 o r fS
Y S
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
A /D
tA D C
c o n v e r s io n tim e
d o n 't c a r e
E n d o f A /D
c o n v e r s io n
A /D
tA D C
c o n v e r s io n tim e
/3 2
A/D Conversion Timing
Rev. 1.20
20
November 1, 2006
HT46RB50
The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete,
whereas in the second example, the A/D interrupt is used to determine when the conversion is complete.
Example: using EOCB Polling Method to detect end of conversion
clr
EADI
; disable ADC interrupt
mov
a,00000001B
mov
ACSR,a
; setup the ACSR register to select fSYS/8 as the A/D clock
mov
a,00100000B
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
mov
ADCR,a
; and select AN0 to be connected to the A/D converter
:
:
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Start_conversion:
clr
START
set
START
; reset A/D
clr
START
; start A/D
Polling_EOC:
sz
EOCB
; poll the ADCR register EOCB bit to detect end of A/D conversion
jmp
polling_EOC
; continue polling
mov
a,ADRH
; read conversion result high byte value from the ADRH register
mov
adrh_buffer,a
; save result to user defined memory
mov
a,ADRL
; read conversion result low byte value from the ADRL register
mov
adrl_buffer,a
; save result to user defined memory
:
:
jmp
Start_conversion
; start next A/D conversion
Example: using Interrupt Method to detect end of conversion
clr
EADI
; disable ADC interrupt
mov
a,00000001B
mov
ACSR,a
; setup the ACSR register to select fSYS/8 as the A/D clock
mov
mov
a,00100000B
ADCR,a
:
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
; and select AN0 to be connected to the A/D converter
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Start_conversion:
clr
START
set
START
clr
START
clr
ADF
set
EADI
set
EMI
:
:
:
; ADC interrupt service routine
ADC_ISR:
mov
acc_stack,a
mov
a,STATUS
mov
status_stack,a
:
:
mov
a,ADRH
mov
adrh_buffer,a
mov
a,ADRL
mov
adrl_buffer,a
clr
START
set
START
clr
START
:
:
Rev. 1.20
; reset A/D
; start A/D
; clear ADC interrupt request flag
; enable ADC interrupt
; enable global interrupt
; save ACC to user defined memory
; save STATUS to user defined memory
; read conversion result high byte value from the ADRH register
; save result to user defined register
; read conversion result low byte value from the ADRL register
; save result to user defined register
; reset A/D
; start A/D
21
November 1, 2006
HT46RB50
EXIT_INT_ISR:
mov
a,status_stack
mov
STATUS,a
mov
a,acc_stack
reti
; restore STATUS from user defined memory
; restore ACC from user defined memory
Low Voltage Reset - LVR
The relationship between VDD and VLVR is shown below.
The microcontroller provides low voltage reset circuit in
order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR, such as changing a battery, the LVR will automatically reset the device internally.
V D D
5 .5 V
V
O P R
5 .5 V
V
The LVR includes the following specifications:
L V R
3 .0 V
· The low voltage range (0.9V~VLVR) has to be main-
2 .2 V
tained for over 1ms, otherwise, the LVR will ignore it
and do not perform a reset function.
· The LVR uses the ²OR² function with the external RES
0 .9 V
signal to perform a chip reset.
Note: VOPR is the voltage range for proper chip
operation at 4MHz system clock.
V
D D
5 .5 V
V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
N o r m a l O p e r a tio n
R e s e t
R e s e t
*1
*2
Low Voltage Reset
Note:
*1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before resuming normal operation.
*2: Low voltage state has to be maintained in its original state for over 1ms, then after 1ms delay,
the device enters the reset mode.
Rev. 1.20
22
November 1, 2006
HT46RB50
Serial Interface
Serial interface function has four basic signals included. They are SDI (serial data input), SDO (serial data output), SCK
(serial clock) and SCS (slave select pin).
Note: SCS can be named SCS in the design note.
S C S
C L K
S D I
S D O
S B C R
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
C K S
M 1
M 0
S B E N
M L S
C S E N
W C O L
T R F
D E F A U L T
: S E R IA L B U S
0
1
1
0
0
0
0
0
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
S B D R
U
U
U
U
U
U
U
U
D A T A R E G IS T E R
D E F A U L T
S B D R
S B C R
C O N T R O L R E G IS T E R
: S E R IA L B U S
N o te : "U " m e a n s u n c h a n g e d .
¨
Two registers (SBCR and SBDR) unique to serial interface provide control, status, and data storage.
Bit2 (CSEN) ® serial bus selection signal enable/disable (SCS), when CSEN=0, SCSB is floating.
· SBCR: Serial bus control register
Bit7 (CKS) clock source selection: fSIO=fSYS/4, select
as 0
Bit6 (M1), Bit5 (M0) master/slave mode and baud rate
selection
M1, M0: 00 ® MASTER MODE, BAUD RATE= fSIO
01 ® MASTER MODE, BAUD RATE= fSIO/4
10 ® MASTER MODE, BAUD RATE= fSIO/16
11 ® SLAVE MODE
Bit1 (WCOL) ® this bit is set to 1 if data is written to
SBDR (TXRX buffer) when data is transferred,
writing will be ignored if data is written to SBDR
(TXRX buffer) when data is transferred.
Bit0 (TRF) ® data transferred or data received
used to generate an interrupt.
Note: data receiving is still working when the MCU
enters HALT mode.
· Bit4 (SBEN) ® serial bus enable/disable (1/0)
¨
Enable: (SCS dependent on CSEN bit)
· SBDR: Serial bus data register
Disable ® enable: SCK, SDI, SDO, SCS= 0
(SCKB= ²0²) and waiting for writing data to SBDR
(TXRX buffer)
Data written to SBDR ® write data to TXRX buffer
only
Data read from SBDR ® read from SBDR only
Operating Mode description:
Master transmitter: clock sending and data I/O started
by writing SBDR
Master clock sending started by writing SBDR
Slave transmitter: data I/O started by clock received
Slave receiver: data I/O started by clock received
Master mode: write data to SBDR (TXRX buffer)
start transmission/reception automatically
Master mode: when data has been transferred, set
TRF
Slave mode: when an SCK (and SCS dependent on
CSEN) is received, data in TXRX buffer is
shifted-out and data on SDI is shifted-in.
Rev. 1.20
Disable: SCK (SCK), SDI, SDO, SCS floating
Bit3 (MLS) ® MSB or LSB (1/0) shift first control bit
23
November 1, 2006
HT46RB50
Clock polarity= rising (CLK) or falling (CLK): 1 or 0 (mask option)
Modes
Operations
1.
Select CKS and select M1, M0 = 00,01,10
2.
Select CSEN, MLS (the same as the slave)
3.
Set SBEN
4.
Writing data to SBDR ® data is stored in TXRX buffer ® output CLK (and SCS) signals ® go to
step 5 ® (SIO internal operation ® data stored in TXRX buffer, and SDI data is shifted into TXRX
buffer ® data transferred, data in TXRX buffer is latched into SBDR)
Master
5.
Check WCOL; WCOL= 1 ® clear WCOL and go to step 4; WCOL= 0 ® go to step 6
6.
Check TRF or waiting for SBI (serial bus interrupt)
7.
Read data from SBDR
8.
Clear TRF
9.
Go to step 4
1.
CKS don¢t care and select M1, M0= 11
2.
Select CSEN, MLS (the same as the master)
3.
Set SBEN
4.
Writing data to SBDR ® data is stored in TXRX buffer ® waiting for master clock signal (and SCS):
CLK ® go to step 5 ® (SIO internal operations ® CLK (SCS) received ® output data in TXRX
buffer and SDI data is shifted into TXRX buffer ® data transferred, data in TXRX buffer is latched
into SBDR)
5.
Check WCOL; WCOL= 1 ® clear WCOL, go to step 4; WCOL= 0 ® go to step 6
6.
Check TRF or wait for SBI (serial bus interrupt)
7.
Read data from SBDR
8.
Clear TRF
9.
Go to step 4
Slave
Operation of Serial Interface
SCS pin (master and slave) should be floating. CSEN
has 2 options: CSEN mask option is used to enable/disable software CSEN function. If CSEN mask option is
disabled, the software CSEN is always disabled. If
CSEN mask option is enabled, software CSEN function
can be used.
WCOL: master/slave mode, set while writing to SBDR
when data is transferring (transmitting or receiving) and
this writing will then be ignored. WCOL function can be
enabled/disabled by mask option. WCOL is set by SIO
and cleared by users.
Data transmission and reception are still working when
the MCU enters the HALT mode.
SBEN= 1 ® serial bus standby; SCS (CSEN= 1) = 1;
SCS= floating (CSEN= 0); SDI= floating; SDO= 1; master CLK= output 1/0 (dependent on CPOL mask option),
slave CLK= floating
CPOL is used to select the clock polarity of CLK. It is a
mask option.
MLS: MSB or LSB first selection
SBEN= 0 ® serial bus disabled; SCS= SDI= SDO=
CLK= floating
CSEN: chip select function enable/disable, CSEN=1 ®
SCS signal function is active. Master should output SCS
signal before CLK signal is set and slave data transferring should be disabled (or enabled) before (after) SCS
signal is received. CSEN= 0, SCS signal is not needed,
Rev. 1.20
TRF is set by SIO and cleared by users. When data
transfer (transmission and reception) is completed, TRF
is set to generate SBI (serial bus interrupt).
24
November 1, 2006
HT46RB50
S B E N = 1 , C S E N = 0 a n d w r ite d a ta to S B D R
( if p u ll- h ig h e d )
S B E N = C S E N = 1 a n d w r ite d a ta to S B D R
S C S
C L K
D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7
S D I
D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7
S D O
C L K B
S B C R
D e fa u lt
S B D R
D e fa u lt
D 7
C K S
0
D 7
u
D 6
M 1
1
D 6
u
D 5
M 0
1
D 5
u
D 4
S B E N
0
D 4
u
D 3
M L S
0
D 3
u
D 2
C S E N
0
D 2
u
D 1
W C O L
0
D 1
u
D 0
T R F
0
D 0
u
N o te : "u " m e a n s u n c h a n g e d .
D a ta B u s
S B D R
( R e c e iv e d D a ta R e g is te r )
D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0
M
S D O
U
X
B u ffe r
S B E N
M L S
M
In te r n a l B a u d R a te C lo c k
a n d , s ta rt
E N
C L K
a n d , s ta rt
C lo c k P o la r ity
S D I
U
X
M
S D O
U
X
T R F
C 0 C 1 C 2
M a s te r o r S la v e
A N D
In te r n a l B u s y F la g
S B E N
a n d , s ta rt
E N
W r ite S B D R
W r ite S B D R
S B E N
W C O L F la g
E n a b le /D is a b le
W r ite S B D R
S C S
M a s te r o r S la v e
S B E N
C S E N
W C O L : s e t b
C S E N : e n a b
1 . m a s te r
2 . s la v e m
S B E N : e n a b
1 . W h e n S
2 . W h e n S
T R F 1 : d a ta
C P O L 1 /0 : c
Rev. 1.20
y S IO c le a r e d b y u s e r s
le /d is a b le c h ip s e le c tio n fu n c tio
m o d e 1 /0 : w ith /w ith o u t S C S B o
o d e 1 /0 : w ith /w ith o u t S C S B in p
le /d is a b le s e r ia l b u s ( 0 : in itia liz
B E N = 0 , a ll s ta tu s fla g s s h o u ld
B E N = 0 , a ll S IO r e la te d fu n c tio
tr a n s m itte d o r r e c e iv e d , 0 : d a ta
lo c k p o la r ity r is in g /fa llin g e d g e
25
n p
u tp
u t
e a
b e
n p
is
: m
in
u t fu n c tio n
c o n tro l fu n
ll s ta tu s fla
in itia liz e d
in s s h o u ld
tr a n s m ittin
a s k o p tio n
c tio n
g s )
s ta y a t flo a tin g s ta te
g o r s till n o t r e c e iv e d
November 1, 2006
HT46RB50
Suspend Wake-Up or Remote Wake-Up
The device with remote wake-up function can wake-up
the USB Host by sending a wake-up pulse through
RMWK (bit 1 of the USC). Once the USB Host receive
the wake-up signal from the HT46RB50, it will send a
If there is no signal on the signal bus for over 3ms, the
HT46RB50 will go into suspend mode. The Suspend
line (bit 0 of the USC) will be set to 1 and a USB interrupt
is triggered to indicate that the HT46RB50 should jump
to suspend state to meet the 500mA USB suspend current spec.
S U S P E N D
M in . 1 U S B C L K
R M W K
In order to meet the 500mA suspend current, the firmware should disable the USB clock by clearing the
USBCKEN (bit3 of the UCC) to ²0². The suspend current is about 400mA.
U S B R e s u m e S ig n a l
M in .2 .5 m s
U S B _ IN T
The user can also further decrease the suspend current
to 250mA by setting the SUSP2 (bit4 of the UCC). But if
the SUSP2 is set, user should make sure not to enable
the LVR OPT option, otherwise, the HT46RB50 will be
reset.
Resume signal to the device. The timing is as follow:
USB Interface
When the resume signal is sent out by the host, the
HT46RB50 will wake-up the by USB interrupt and the
Resume line (bit 3 of the USC) is set. In order to make
the HT46RB50 work properly, the firmware must set the
USBCKEN (bit 3 of the UCC) to 1 and clear the SUSP2
(bit4 of the UCC). Since the Resume signal will be
cleared before the Idle signal is sent out by the host and
the Suspend line (bit 0 of the USC) is going to ²0². So
when the MCU is detecting the Suspend line (bit0 of
USC), the Resume line should be remembered and
taken into consideration.
The HT46RB50 has 4 Endpoints (EP0~EP3). EP0~EP2
are support Interrupt transfer, EP3 is support Bulk transfer.
There are 12 registers, including USC (20H), USR
(21H), UCC (22H), AWR (address+remote wake-up
23H), STALL (24H), SIES (25H), MISC (26H), SETIO
(27H), FIFO0 (28H), FIFO1 (29H), FIFO2 (2AH) and
FIFO3 (2BH) used for the USB function.
The FIFO size of each FIFO is 8 byte (FIFO0), 8 byte
(FIFO1), 8 byte (FIFO2) and 64 byte (FIFO3), and total
of 88 bytes.
After finishing the resume signal, the suspend line will
go inactive and a USB interrupt is triggered. The following is the timing diagram:
URD (bit7 of the USC) is USB reset signal control function definition bit.
S U S P E N D
U S B R e s u m e S ig n a l
U S B _ IN T
Rev. 1.20
26
November 1, 2006
HT46RB50
Bit No.
Label
R/W
Function
0
SUSP
R
Read only, USB suspend indication. When this bit is set to ²1² (set by SIE), it indicates that the USB bus enters the suspend mode. The USB interrupt is also triggered on any changes of this bit.
1
RMWK
R/W
USB remote wake-up command. It is set by the MCU to force the USB host leaving
the suspend mode. Set RMWK bit to ²1² to enable remote wake-up. When this bit
is set to ²1², a 2ms delay for clearing this bit to ²0² is needed to insure that the
RMWK command is accepted by the SIE.
2
URST
R/W
USB reset indication. This bit is set/cleared by USB SIE. When the URST is set to
²1², this indicates that a USB reset has occurred and a USB interrupt will be initialized.
USB resume indication. When the USB leaves the suspend mode, this bit is set to
²1² (set by SIE). This bit will appear for 20ms, waiting for the MCU to detect it.
When the RESUME is set by SIE, an interrupt will be generated to wake-up the
MCU. In order to detect the suspend state, MCU should set the USBCKEN and
SUSP2 (in the SCC register) to enable the SIE detect function. The RESUME will
be cleared while the SUSP is set to ²0². When MCU detects the SUSP, the RESUME (which causes MCU to wake-up) should be remembered and token into
consideration.
3
RESUME
R
4
V33C
R/W
0/1: Turn-off/on V33O output
5
PLL
R/W
0:Turn-on the PLL (default mode); 1: turn-of the PLL
6
¾
¾
7
URD
R/W
Undefined bit, read as ²0²
USB reset signal control function definition
1: USB reset signal will reset the MCU
0: USB reset signal cannot reset the MCU
USC (20H) Definitions
The USR (USB endpoint interrupt status register) register is used to indicate which endpoint is accessed and then selects A/D converter operation modes. The endpoint request flags (EP0IF, EP1IF, EP2IF and EP3IF) are used to indicate which endpoints are accessed. If an endpoint is accessed, the related endpoint request flag will be set to ²1² and
the USB interrupt will occur (if the USB interrupt is enabled and the stack is not full). When the active endpoint request
flag is served, the endpoint request flag has to be cleared to ²0².
Bit No.
Label
R/W
Function
0
EP0IF
R/W
When this bit is set to ²1² (set by SIE), it indicates that the endpoint 0 is accessed
and a USB interrupt will occur. When the interrupt has been served, this bit should
be cleared by firmware.
1
EP1IF
R/W
When this bit is set to ²1² (set by SIE), it indicates that the endpoint 1 is accessed
and a USB interrupt will occur. When the interrupt has been served, this bit should
be cleared by firmware.
2
EP2IF
R/W
When this bit is set to ²1² (set by SIE), it indicates that the endpoint 2 is accessed
and a USB interrupt will occur. When the interrupt has been served, this bit should
be cleared by firmware.
3
EP3IF
R/W
When this bit is set to ²1² (set by SIE), it indicates that the endpoint 3 is accessed
and a USB interrupt will occur. When the interrupt has been served, this bit should
be cleared by firmware.
4~7
¾
¾
Undefined bit, read as ²0²
USR (21H) Definitions
Rev. 1.20
27
November 1, 2006
HT46RB50
There is a system clock control register implemented to select the clock used in the MCU. This register consists of USB
clock control bit (USBCKEN), second suspend mode control bit (SUSP2) and system clock selection (SYSCLK)
The following table defines which endpoint FIFO is selected, EPS2, EPS1 and EPS0.
Bit No.
Label
R/W
Function
0~2
EPS0~EPS2
R/W
Accessing endpoint FIFO selection.
EPS2, EPS1, EPS0:
000: Select endpoint 0 FIFO
001: Select endpoint 1 FIFO
010: Select endpoint 2 FIFO
011: Select endpoint 3 FIFO
100: Reserved for future expansion, cannot be used
101: Reserved for future expansion, cannot be used
110: Reserved for future expansion, cannot be used
111: Reserved for future expansion, cannot be used
If the selected endpoints do not exist, the related functions are not available.
3
USBCKEN
R/W
USB clock control bit. When this bit is set to ²1², it indicates that the USB clock
is enabled.
Otherwise, the USB clock is turned-off.
4
SUSP2
R/W
This bit is used to reduce power consumption in suspend mode.
In normal mode, clear this bit to 0 (default)
In HALT mode, set this bit to 1 to reduce power consumption.
5
fSYS
(24MHz)
R/W
This bit is used to define the MCU system clock to come from either the external OSC or from PLL output 24MHz clock.
0: system clock comes from OSC
1: system clock comes from PLL output 24MHz
This bit is used to specify the system clock oscillator frequency used by the
MCU. If a 6MHz crystal oscillator or resonator is used, this bit should be set to
²1². If a 12MHz crystal oscillator or resonator is used. this bit should be cleared
to ²0² (default).
6
SYSCLK
R/W
7
¾
¾
Undefined, read as ²0²
UCC (22H) Definitions
The AWR register contains the current address and the remote wake-up function control bit. The initial value of the
AWR is ²00H². The address value extracted from the USB command is not to be loaded into this register until the
SETUP stage is finished.
Bit No.
Label
R/W
Function
0
WKEN
R/W
Remote wake-up enable/disable
7~1
AD6~AD0
R/W
USB device address
AWR (23H) Definitions
The STALL register shows whether the corresponding endpoint works properly or not. As soon as the endpoint works
improperly, the related bit in the STALL has to be set to ²1². The STALL will be cleared by the USB reset signal.
Bit No.
Label
R/W
Function
3~0
STL3~STL0
R/W
Set by users when the related USB endpoints are stalled. They are cleared by
USB reset and Setup Token event
7~4
¾
¾
Undefined bit, read as ²0²
STALL (24H) Definitions
Rev. 1.20
28
November 1, 2006
HT46RB50
Bit No.
Label
R/W
Function
0
ASET
R/W
This bit is used to configure the SIE to automatically change the device address
with the value stored in the AWR register. When this bit is set to ²1² by firmware,
the SIE will update the device address with the value stored in the AWR register
after the PC host has successfully read the data from the device by IN operation.
Otherwise, when this bit is cleared to ²0², the SIE will update the device address
immediately after an address is written to the AWR register. So, in order to work
properly, firmware has to clear this bit after the next valid SETUP token is received.
1
ERR
R/W
This bit is used to indicate there are some errors occurred during the FIFO0 is accessed. This bit is set by SIE and should be cleared by firmware.
2
OUT
R/W
This bit is used to indicate there are OUT token (except for the OUT zero length
token) that have been received. The firmware clears this bit after the OUT data
has been read. Also, this bit will be cleared by SIE after the next valid SETUP token is received.
3
IN
R
This bit is used to indicate that the current USB receiving signal from the PC host
is IN token. (1=IN token; 0=Non IN token)
4
NAK
R
This bit is used to indicate that the SIE has transmitted a NAK signal to the host in
response to the PC host IN or OUT token. (1=NAK signal; 0=Non NAK signal)
5
CRCF
R/W
Error condition failure flag include CRC, PID, no integrate token error, CRCF will
be set by hardware and the CRCF need to be cleared by firmware.
6
EOT
R
7
NMI
R/W
Token Package active flag, low active.
NAK token interrupt mask flag. If this bit is set, when the device sent a NAK token
to the host, interrupt will not occur. Otherwise, when this bit is cleared, and the
device sent a NAK token to the host, it will enter the interrupt sub-routine.
SIES (25H) Definitions
MISC register combines a command and status to control the desired endpoint FIFO action and to show the status of
the desired endpoint FIFO. The MISC will be cleared by USB reset signal.
Bit No.
Label
R/W
Function
0
REQUEST
R/W
After selecting the desired endpoint, FIFO can be requested by setting this bit as
high active. Afterwards, this bit must be set low.
1
TX
R/W
This indicates the direction and transition end which the MCU accesses. When
set as logic 1, the MCU writes data to FIFO. Afterwards, this bit must be set to
logic 0 before terminating request to indicate transition end. For reading action,
this bit must be set to logic 0 to indicate that the MCU wants to read and must be
set to logic 1 afterwards.
2
CLEAR
R/W
This indicates an MCU clear requested FIFO, even if the FIFO is not ready. After
clearing the FIFO, USB interface will send force_tx_err to tell Host that data under-run if Host want to read data.
3~4
¾
R/W
Reserved bit
5
SETCMD
R/W
To show that the data in FIFO is setup command. This bit will last this state until
next one entering the FIFO. (1=SETCMD token; 0=Non SETCMD token)
6
READY
R
7
LEN0
R/W
To tell that the desired FIFO is ready to work.
(1=Ready to work; 0=Non ready to work)
To tell that host sent a 0-sized packet to MCU. This bit must be cleared by read
action to corresponding FIFO. (1=Host sent a 0-sized packet)
MISC (26H) Definitions
Rev. 1.20
29
November 1, 2006
HT46RB50
There are some timing constrains and usages illustrated here. By setting the MISC register, MCU can perform reading,
writing and clearing actions. There are some examples shown in the following table for endpoint FIFO reading, writing
and clearing.
Actions
MISC Setting Flow and Status
Read FIFO0 sequence
00H®01H®delay 2ms, check 41H®read* from FIFO0 register and
check not ready (01H)®03H®02H
Write FIFO0 sequence
02H®03H®delay 2ms, check 43H®write* to FIFO0 register and
check not ready (03H)®01H®00H
Check whether FIFO0 can be read or not
00H®01H®delay 2ms, check 41H (ready) or 01H (not ready)®00H
Check whether FIFO0 can be written or not
02H®03H®delay 2ms, check 43H (ready) or 03H (not ready)®02H
Read 0-sized packet sequence form FIFO0
00H®01H®delay 2ms, check 81H®read once (01H)®03H®02H
Write 0-sized packet sequence to FIFO0
02H®03H®delay 2ms, check 03H®07H®06H®00H
Read or Write FIFO Table
Note:
*: There are 2ms existing between 2 reading action or between 2 writing action
R e q .
R e q .
T x
T x
R e a d y
R e a d y
R e a d F IF O
T im in g
W r ite F IF O
T im in g
Bit No.
Label
R/W
0
DATATG*
R/W
To toggle this bit, all the DATA token will send a DATA0 first.
Function
1
SETIO1**
R/W
Set endpoint 1 input or output pile (1/0), default input pipe (1)
2
SETIO2**
R/W
Set endpoint 2 input or output pile (1/0), default input pipe (1)
3
SETIO3**
R/W
Set endpoint 3 input or output pile (1/0), default input pipe (1)
4~7
¾
¾
Undefined bit, read as ²0²
SETIO Register (27H), USB Endpoint 1~Endpoint5 Set IN/OUT Pipe Register
Note:
*USB definition: when the host sends a ²set Configuration², the Data pipe should send the DATA0 (Data toggle) first. So, when the device receives a ²set configuration² setup command, user needs to toggle this bit so
the next data will send a Data0 first.
**Needs to set the data pipe as an input pile or output pile. The purpose of this function is to avoid the host from
abnormally sending only an IN or OUT token and disables the endpoint.
Options
The following table shows all kinds of options in the microcontroller. All of the OTP options must be defined to ensure a
proper functioning system.
No.
Option
1
PA0~PA7 pull-high resistor enable or disable (by bit)
2
PB0~PB7 pull down resistor enable or disable (by bit)
3
PC0~PC7 pull-high resistor enable or disable (by nibble)
4
PD0~PD7 pull-high resistor enable or disable (by nibble)
5
PE0~PE5 pull-high resistor enable or disable (by nibble)
6
LVR enable or disable
Rev. 1.20
30
November 1, 2006
HT46RB50
No.
Option
7
PWM selection: (7+1) or (6+2) mode
PD0: level output or PWM0 output
PD1: level output or PWM1 output
8
SIO (Serial Interface) enable/disable (if SIO is enabled then PE0~PE3 I/O port will be disabled)
9
SIO_ CPOL: Clock polarity 1/0: clock polarity rising or falling edge
10
SIO_WCOL: Enable/disable
11
SIO_CSEN: Enable/disable, CSEN mask option is used to enable/disable (1/0) software CSEN function
12
WDT enable/disable
13
WDT clock source: fSYS/4 or WDTOSC
14
WDT timeout period: 212/fS~213/fS, 213/fS~214/fS, 214/fS~215/fS, 215/fS~216/fS
15
²CLRWDT² instruction (s): 1 or 2
16
PA0~PA7 wake-up enable/disable (by bit)
17*
EP1~EP3 Data pipe enable: EP1, EP2, EP3 enable/disable. (Default is enable)
Note:
*: The purpose of this option is to enable the endpoint that will be used, and disable the endpoint that will not be
used.
Application Circuits
V D D
U S B -
5 W *
0 .1 m F *
P A 0 ~ P A 7
3 3 W *
1 0 0 k W
U S B +
V D D
1 0 k W
V S S
5 W *
0 .1 m F *
P B 0 ~ P B 7
P C 0 ~ P C 7
0 .1 m F
P D 0 ~ P D 7
P E 0 ~ P E 5
R E S
0 .1 m F *
V 3 3 O
2 2 p F
0 .1 m F
4 7 p F *
3 3 W *
U S B D O S C 1
4 7 p F *
2 2 p F
4 7 p F
3 3 W *
U S B D +
O S C 2
1 .5 k W
4 7 p F
V S S
H T 4 6 R B 5 0
Note:
The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is
stable and remains within a valid operating voltage range before bringing RES to high.
X1 can use 6MHz or 12MHz, X1 as close to OSC1 and OSC2 as possible
Components with ²*² are used for EMC issue
22pF capacitance are used for resonator only
Rev. 1.20
31
November 1, 2006
HT46RB50
Instruction Set Summary
Description
Instruction
Cycle
Flag
Affected
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to data memory with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1
1
1(1)
1
1
1(1)
1
1(1)
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
1
1(1)
Z
Z
Z
Z
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1
1(1)
1
1(1)
1
1(1)
1
1(1)
None
None
C
C
None
None
C
C
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Mnemonic
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Rev. 1.20
32
November 1, 2006
HT46RB50
Instruction
Cycle
Flag
Affected
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
None
TO,PDF
Mnemonic
Description
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
:
(4)
Rev. 1.20
and (2)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
²CLR WDT1² or ²CLR WDT2² instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
33
November 1, 2006
HT46RB50
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
34
November 1, 2006
HT46RB50
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ Program Counter+1
Program Counter ¬ addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
The contents of the specified data memory are cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
35
November 1, 2006
HT46RB50
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
0
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
36
November 1, 2006
HT46RB50
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory is decremented by 1.
Operation
[m] ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
37
November 1, 2006
HT46RB50
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation
Program Counter ¬ Program Counter+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
1
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Data in the specified data memory is incremented by 1
Operation
[m] ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
Program Counter ¬addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV A,[m]
Move data memory to the accumulator
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
38
November 1, 2006
HT46RB50
MOV A,x
Move immediate data to the accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
Program Counter ¬ Program Counter+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
39
November 1, 2006
HT46RB50
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a 2-cycle instruction.
Operation
Program Counter ¬ Stack
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
40
November 1, 2006
HT46RB50
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
41
November 1, 2006
HT46RB50
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
42
November 1, 2006
HT46RB50
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Bit i of the specified data memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
43
November 1, 2006
HT46RB50
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
44
November 1, 2006
HT46RB50
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
45
November 1, 2006
HT46RB50
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
46
November 1, 2006
HT46RB50
Package Information
28-pin SOP (300mil) Outline Dimensions
2 8
1 5
A
B
1
1 4
C
C '
G
H
D
E
Symbol
Rev. 1.20
a
F
Dimensions in mil
Min.
Nom.
Max.
A
394
¾
419
B
290
¾
300
C
14
¾
20
C¢
697
¾
713
D
92
¾
104
E
¾
50
¾
F
4
¾
¾
G
32
¾
38
H
4
¾
12
a
0°
¾
10°
47
November 1, 2006
HT46RB50
28-pin SKDIP (300mil) Outline Dimensions
A
B
2 8
1 5
1
1 4
H
C
D
E
Symbol
Rev. 1.20
F
a
G
I
Dimensions in mil
Min.
Nom.
Max.
A
1375
¾
1395
B
278
¾
298
C
125
¾
135
D
125
¾
145
E
16
¾
20
F
50
¾
70
G
¾
100
¾
H
295
¾
315
I
330
¾
375
a
0°
¾
15°
48
November 1, 2006
HT46RB50
48-pin SSOP (300mil) Outline Dimensions
4 8
2 5
A
B
2 4
1
C
C '
G
H
D
F
E
Symbol
Rev. 1.20
a
Dimensions in mil
Min.
Nom.
Max.
A
395
¾
420
B
291
¾
299
C
8
¾
12
C¢
613
¾
637
D
85
¾
99
E
¾
25
¾
F
4
¾
10
G
25
¾
35
H
4
¾
12
a
0°
¾
8°
49
November 1, 2006
HT46RB50
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330±1
B
Reel Inner Diameter
62±1.5
C
Spindle Hole Diameter
13+0.5
-0.2
D
Key Slit Width
2±0.5
T1
Space Between Flange
24.8+0.3
-0.2
T2
Reel Thickness
30.2±0.2
SSOP 48W
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330±1
B
Reel Inner Diameter
100±0.1
C
Spindle Hole Diameter
13+0.5
-0.2
D
Key Slit Width
2±0.5
T1
Space Between Flange
32.2+0.3
-0.2
T2
Reel Thickness
38.2±0.2
Rev. 1.20
50
November 1, 2006
HT46RB50
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
C
D 1
B 0
P
K 0
A 0
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
24±0.3
P
Cavity Pitch
12±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
11.5±0.1
D
Perforation Diameter
1.5+0.1
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4±0.1
P1
Cavity to Perforation (Length Direction)
2±0.1
A0
Cavity Length
10.85±0.1
B0
Cavity Width
18.34±0.1
K0
Cavity Depth
2.97±0.1
t
Carrier Tape Thickness
0.35±0.01
C
Cover Tape Width
Rev. 1.20
21.3
51
November 1, 2006
HT46RB50
P 0
D
P 1
t
E
F
W
D 1
C
B 0
K 1
P
K 2
A 0
SSOP 48W
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
32±0.3
P
Cavity Pitch
16±0.1
E
Perforation Position
1.75±0.1
14.2±0.1
F
Cavity to Perforation (Width Direction)
D
Perforation Diameter
2 Min.
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4±0.1
P1
Cavity to Perforation (Length Direction)
2±0.1
A0
Cavity Length
12±0.1
B0
Cavity Width
16.2±0.1
K1
Cavity Depth
2.4±0.1
K2
Cavity Depth
3.2±0.1
t
Carrier Tape Thickness
C
Cover Tape Width
Rev. 1.20
0.35±0.05
25.5
52
November 1, 2006
HT46RB50
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shanghai Sales Office)
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 021-6485-5560
Fax: 021-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District,
Shenzhen, China 518057
Tel: 0755-8616-9908, 8616-9308
Fax: 0755-8616-9533
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Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 010-6641-0030, 6641-7751, 6641-7752
Fax: 010-6641-0125
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709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016
Tel: 028-6653-6590
Fax: 028-6653-6591
Holmate Semiconductor, Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538
Tel: 510-252-9880
Fax: 510-252-9885
http://www.holmate.com
Copyright Ó 2006 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.20
53
November 1, 2006