HV430 High Voltage Ring Generator Ordering Information Operating Voltage Package Options VPP1-VNN1 SOW-20 325V HV430WG Features General Description ❏ 105Vrms ring signal ❏ Output over current protection ❏ 5.0V CMOS logic control ❏ Logic enable/disable to save power ❏ Adjustable deadband in single-control mode The Supertex HV430 is a high voltage PWM ring generator integrated circuit. The high voltage outputs, VPGATE and VNGATE, are used to drive the gates of external high voltage P-channel and N-channel MOSFETs in a push-pull configuration. Over current protection is implemented for both the P-channel and Nchannel MOSFETs. External sense resistors set the over-current trip point. ❏ Power-on reset ❏ Fault output for problem detection The RESET input functions as a power-on reset when connected to an external capacitor. The FAULT output indicates an over-current condition and is cleared after 4 consecutive cycles with no overcurrent condition. A logic low on RESET or ENABLE clears the FAULT output. It is active-low and open-drain to allow wire OR’ing of multiple drivers. Applications ❏ Line access cards ❏ Set-top/Street box Pgate and Ngate are controlled independently by logic inputs PIN and NIN when the MODE pin is at logic high. A logic high on PIN will turn on the external P-channel MOSFET. Similarly, a logic high on NIN will turn on the external N-channel MOSFET. Lockout circuitry prevents the N and P switches from turning on simultaneously. A pulse width limiter restricts pulse widths to no less than 100200ns. Absolute Maximum Ratings VPP1 – VNN1, power supply voltage +340V VPP1, positive high voltage supply +220V VPP2, positive gate voltage supply +220V VNN1, negative high voltage supply -220V VNN2, negative gate voltage supply -220V VDD, logic supply +7.5V Storage temperature Power dissipation For applications where a single control input is desired, the MODE pin should be connected to SGND. The PWM control signal is then input to the NIN pin. A user-adjustable deadband in the control logic ensures break-before-make on the outputs, thus avoiding cross conduction on the high voltage output during switching. A logic high on NIN will turn the external P-Channel MOSFET on and the N-Channel off, and vice versa. The IC can be powered down by applying a logic low on the ENABLE pin, placing both external MOSFETs in the off state. -65°C to +150°C 600mW 12/13/01 Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, 1 refer to the most current databook or to the Legal/Disclaimer page on the Supertex website. HV430 Electrical Characteristics (Over operating supply voltage unless otherwise specified, TA = -40°C to +85°C.) External Supplies Symbol Parameter VPP1 High voltage positive supply IPP1Q VPP quiescent current IPP1 VPP operating current VNN1 High voltage negative supply INN1Q VNN1 quiescent current INN1 VNN1 operating current VDD Logic supply voltage IDDQ VDD quiescent current IDD VDD operating current Min Typ 50 250 VPP1-325 250 4.50 300 Max Unit Conditions 200 V 500 µA PIN=NIN=0V 2.0 mA No load VOUTP and VOUTN switching at 100kHz -50 V 500 µA PIN=NIN=0V, RDB =18kΩ 1.0 mA No load VOUTP and VOUTN switching at 100kHz 5.50 V 400 µA PIN=NIN=0V, RDB =18kΩ 1.0 mA PIN=NIN=100kHz, RDB =18kΩ Max Unit Internal Supplies Symbol Parameter Min Typ VPP2 Positive linear regulator output voltage VPP1-16 VPP1-10 V VNN2 Negative linear regulator output voltage VNN1+10 VNN1+14 V Conditions Positive High Voltage Output Symbol Parameter Min Typ Unit Conditions VPP1 V No load on VPgate VPgate Output voltage swing RsourceP VPgate source resistance 12.5 Ω IOUT=80mA RsinkP VPgate sink resistance 12.5 Ω IOUT=-80mA triseP VPgate rise time 50 ns Cload=1.4nF tfallP VPgate fall time 50 ns Cload=1.4nF tpwp(min) VPgate minimum pulse width (internally limited) 200 ns 300 ns VPP1-1.15 V 150 ns tdelayP PIN to Pgate delay time VPsen VPgate current sense voltage tshortP VPgate current sense off time VPP2 Max 100 150 VPP1-0.85 VPP1-1.0 2 mode=1 HV430 Negative High Voltage Output Symbol Parameter Min Typ Unit Conditions VNN1 V No load on VNgate VNgate Output voltage swing RsourceN VNgate source resistance 15.0 Ω IOUT=80mA RsinkN VNgate sink resistance 15.0 Ω IOUT=-80mA triseN VNgate rise time 50 ns Cload=1.0nF tfallN VNgate fall time 50 ns Cload=1.0nF tpwn(min) VNgate minimum pulse width (internally limited) 200 ns 300 ns VNN1+1.15 V 150 ns tdelayN NIN to VNgate delay time VNsen VNgate current sense voltage tshortN VNgate current sense OFF time VNN2 Max 100 150 VNN1+0.85 VNN1+1.0 mode=1 Control Circuitry Symbol Parameter Min Typ Max Unit Conditions VIL Logic input low voltage 0 0.60 V VDD=5.0V VIH Logic input high voltage 2.7 5.0 V VDD=5.0V IINdn Input pull-down current 0.5 1 5 µA PIN, NIN, ENABLE Rup Input pull-up resistance 100 200 300 kΩ MODE VOL Logic output low voltage 0.50 V VDD=5.0V, IOUT=-0.5mA VOH Logic output high voltage 4.50 V VDD=5.0V, IOUT=0.5mA VRST(OFF) Reset voltage, device off 3.2 3.5 V VDD=5.0V VRST(ON) Reset voltage, device on 3.7 4.0 V VDD=5.0V VRST(HYS) Reset hysteresis voltage 0.3 V VDD=5.0V Ireset Reset pull-up current 13 µA VRESET=0-4.5V tRST(ON) RESET on delay 1.0 µs tRST(OFF) RESET off delay 1.0 µs tEN(ON) ENABLE on delay 150 µs tEN(OFF) ENABLE off delay 1.0 µs tFLT(HOLD) FAULT hold time tDB Deadband time 7 50 10 100 NIN/PIN cycles 4 ENABLE=1 35 50 70 ns Mode=0, Rdb=5.6kΩ 105 140 175 ns Mode=0, Rdb=18kΩ tdelay(N-P) N-off to P-on transistion delay 300 ns Mode=0, Rdb<27kΩ tdelay(P-N) P-off to N-on transistion delay 300 ns Mode=0, Rdb<27kΩ ∆tdelay(N-P) Delay difference tdelayN(off) - tdelayP(on) -80 0 80 ns Mode=1 ∆tdelay(P-N) Delay difference tdelayP(off) - tdelayN(on) -80 0 80 ns Mode=1 3 HV430 Truth Table Logic Inputs* Output NIN PIN mode EN RESET External N-Channel MOSFET External P-Channel MOSFET L L H H > Vreset(on) OFF OFF L H H H > Vreset(on) OFF ON H L H H > Vreset(on) ON OFF H H H H > Vreset(on) OFF OFF H X L H > Vreset(on) OFF ON L X L H > Vreset(on) ON OFF X X X L X OFF OFF X X X X < Vreset(off) OFF OFF * Unused logic inputs should be connected to VDD or GND. Block Diagram and Application Circuit VPP1 VDD +5V VPP2 VPP2 Regulator VDD FAULT VPP1 De-glitcher clk reset PIN Down Translator Current Trip VPSEN Up Translator P Driver VPGATE Rsense MODE DEADBAND NC Control Logic Ringer Output NC NIN ENABLE VDD 10µA RESET SIG GND Up Translator N Driver VNGATE Down Translator Current Trip VNSEN PWR GND VNN2 Regulator VNN1 Rsense VNN2 VNN1 Note: P IN, NIN, and ENABLE are internally pulled low. MODE is internally pulled high. A Reset capacitor in the range of 1-10µF will yield a couple-second turn-on delay. Tantalum is recommended. 4 HV430 Single-Control Mode Timing 1 VDD 0 GND N IN tN-Pdelay tP-Ndelay VPP2 ON P OUT OFF tPrise VPP1 tPfall tN-Pdeadband tP-Ndeadband VNN2 ON N OUT VNN1 OFF tNfall tNrise Dual-Control Mode Timing VDD 1 P IN GND 0 tPdelay(on) tPdelay(off) tPpulse(min) VPP2 ON P OUT OFF VPP1 tPrise tPfall VDD 1 N IN GND 0 tNdelay(on) tNdelay(off) tNpulse(min) VNN2 ON N OUT VNN1 OFF tNrise 5 tNfall HV430 ENABLE Timing 1 VDD 0 GND 1 VDD ENABLE N IN /P IN Switching GND 0 tEN(ON) tEN(OFF) VPP2 ON P OUT Off Switching Off OFF VPP1 VNN2 ON Off N OUT Switching Off VNN1 OFF RESET Timing VRESET(ON) VRESET(OFF) RESET GND VDD 1 N IN /P IN Switching GND 0 t RST(OFF) tRST(ON) VPP2 ON P OUT Off Switching Off OFF VPP1 VNN2 ON Off N OUT Switching Off VNN1 OFF 6 HV430 FAULT Timing ENABLE or RESET 1 VDD 0 GND 1 VDD 0 GND ON VPP2 OFF VPP1 ON VNN2 OFF VNN1 N IN P OUT N OUT Over N SENSE OK ENABLE or RESET clears FAULT immediately tFAULT(HOLD) VDD FAULT w/ext pull-up GND Note: Nsense overcurrent shown. Psense operates identically. 7 HV430 Pin Description VPP1 Positive high voltage supply. VPP2 Positive gate voltage supply. Generated by an internal linear regulator. A 25V, 100nF capacitor should be connected between VPP2 and VPP1. VNN1 Negative high voltage supply. VNN2 Negative gate voltage supply. Generated by an internal linear regulator. A 25V, 100nF capacitor should be connected between VNN2 and VNN1. VDD Logic supply voltage. SGnd Low voltage logic ground. PGnd High voltage power ground. PIN Logic control input. When mode is high, logic input high turns ON the external high voltage P-channel MOSFET. Internally pulled low. NIN Logic control input. When mode is high, logic input high turns ON the external high voltage N-channel MOSFET. Internally pulled low. ENABLE Logic enable input. Logic high enables IC. Internally pulled low. MODE Logic mode input. 0=single-control; 1=dual-control. When MODE is high, NIN and PIN independently control NOUT and POUT, respectively. When MODE is low, NIN controls both outputs in a complementary manner. (See Truth Table) FAULT Logic output. Fault is at logic low when either current limit sense pin, VPsen or VNsen, is activated. Remains active until overcurrent condition clears or ENABLE=0 or RESET=0. RESET Power-on reset. A capacitor connected between this pin and ground determines the delay time between application of VDD and when the device outputs are enabled. Low leakage tantalum recommended. DEADBAND A resistor between this pin and ground sets the ‘break-before-make’ time between output transitions. Applicable only in single-control mode. For minimum deadtime, a 5.6kΩ resistor to ground should be used. For dual-input mode, tie to Vdd. VPgate Gate drive for external P-channel MOSFET. VNgate Gate drive for external N-channel MOSFET. VPsen Pulse by pulse over current sensing for P-Channel MOSFET. VNsen Pulse by pulse over current sensing for N-Channel MOSFET. Pin Configuration VDD 1 20 VPP2 Fault 2 19 VPP1 Mode 3 18 VPSEN PIN 4 17 VPGATE NIN 5 16 N/C Enable 6 15 N/C Reset 7 14 VNGATE Deadband 8 13 VNSEN SGND 9 12 VNN1 PGND 10 11 VNN2 top view SOW 20 12/13/010 ©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited. 8 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 • FAX: (408) 222-4895 www.supertex.com