FA7711V
FUJI Power Supply Control IC
DC/DC Power Supply control IC
FA7711V
Application Note
June-2010
Fuji Electric Systems Co.,Ltd.
Fuji Electric Systems Co., Ltd.
AN-060E Rev.1.0
Jun-2010
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FA7711V
WARNING
1. This Data Book contains the product specifications, characteristics, data, materials, and structures as of
June 2010. The contents are subject to change without notice for specification changes or other reasons.
When using a product listed in this Data Book, be sure to obtain the latest specifications.
2. All applications described in this Data Book exemplify the use of Fuji's products for your reference only.
No right or license, either express or implied, under any patent, copyright, trade secret or other intellectual
property right owned by Fuji Electric Co., Ltd. is (or shall be deemed) granted. Fuji makes no
representation or warranty, whether express or implied, relating to the infringement or alleged
infringement of other's intellectual property rights, which may arise from the use of the applications,
described herein.
3. Although Fuji Electric is enhancing product quality and reliability, a small percentage of semiconductor
products may become faulty. When using Fuji Electric semiconductor products in your equipment, you are
requested to take adequate safety measures to prevent the equipment from causing a physical injury, fire,
or other problem if any of the products become faulty. It is recommended to make your design fail-safe,
flame retardant, and free of malfunction.
4.The products introduced in this Data Book are intended for use in the following electronic and electrical
equipment, which has normal reliability requirements.
• Computers • OA equipment • Communications equipment (Pin devices)
• Measurement equipment • Machine tools • audiovisual equipment • electrical home appliances
• Personal equipment • Industrial robots etc.
5.If you need to use a product in this Data Book for equipment requiring higher reliability than normal, such
as for the equipment listed below, it is imperative to contact Fuji Electric to obtain prior approval. When
using these products for such equipment, take adequate measures such as a backup system to prevent
the equipment from malfunctioning even if a Fuji's product incorporated in the equipment becomes faulty.
• Transportation equipment (mounted on cars and ships) • Trunk communications equipment
• Traffic-signal control equipment • Gas leakage detectors with an auto-shut-off feature
• Emergency equipment for responding to disasters and anti-burglary devices • Safety devices
6. Do not use products in this Data Book for the equipment requiring strict reliability such as (without
limitation)
• Space equipment
• Aeronautic equipment
• Atomic control equipment
• Submarine repeater equipment
• Medical equipment
7. Copyright © 1995 by Fuji Electric Co., Ltd. All rights reserved. No part of this Data Book may be
reproduced in any form or by any means without the express permission of Fuji Electric.
8. If you have any question about any portion in this Data Book, ask Fuji Electric or its sales agents before
using the product. Neither Fuji nor its agents shall be liable for any injury caused by any use of the
products not in accordance with instructions set forth herein.
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FA7711V
CONTENTS
1. Description
····························································· 4
2. Features
····························································· 4
3. Outline
····························································· 4
4. Block diagram
····························································· 5
5. Pin assignment
····························································· 5
6. Ratings and characteristics························································· 6
7. Characteristics curves
····························································· 10
8. Description of each circuit··························································· 15
9. Design advice
10. Application circuit
····························································· 18
····························································· 25
Note
• Parts tolerance and characteristics are not defined in all application described in this Data book. When
design an actual circuit for a product, you must determine parts tolerances and characteristics for safe and
stable operation.
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FA7711V
1. Description
FA7711V is a PWM type DC-to-DC converter control IC with 3ch outputs that can directly drive power
MOSFETs. CMOS devices with high breakdown voltage are used in this IC and low power consumption is
achieved. This IC is suitable for very small DC-to-DC converters because of their small and thin package
(1.2mm max.), and high frequency operation (to 800kHz). You can select Pch or Nch of MOSFETs driven, and
design any topology of DC-to-DC converter circuit like a buck, a boost, a inverting, a fly-back, or a forward.
2. Features
・MOSFET direct driving ( Note : This function is available only for that Vcc is below 20V )
・Selectable output stage for Pch/Nch MOSFET on each channel
・Low operating current by CMOS process: 7mA (typ.)
・3ch PWM control IC
・High frequency operation: 200kHz to 800kHz
・Simple setting of operation frequency by timing resistor
・Soft start function at each channel
・Adjustable maximum duty cycle at each channel
・Built-in under voltage lockout
・High accuracy reference voltage: VREF: 3.7V±1%
・Adjustable built-in timer latch for short-circuit protection
・Thin and small package: TSSOP-24
3. Outline
Typ.
7.8±0.1
7.6±0.2
7 711V
H 0 1D 02
5.6±0.1
24
12
1.0±0.1
0.27±0.02
0.10±0.05
0.65
1.20 MAX
Lot.No.
0.17
#1
Unit：mm
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FA7711V
4. Block diagram
⑯ CS3 ⑭ CS2 ⑪ CS1
④ VREF
⑱ VCC
Reference
voltge
Soft
start
ＵＶＬＯ
PVCC
② RT
⑥ IN1+
⑦ IN1-
Oscillator
⑰ PVCC
Er.Amp.1
Comp.1
PVCC
＋
＋
－
P ch
drive
－
⑫ OUT1
⑧ FB1
PGND
21 IN2+
⑳ IN2-
Er.Amp.2
＋
Comp.2
PVCC
－
－
N/P ch
drive
＋
⑲ FB2
PGND
Er.Amp.3
24 IN3+
＋
23 IN3-
－
Comp.3
⑬ OUT2
⑤ SEL2
PVCC
＋
N/P ch
drive
－
22 FB3
⑮ OUT3
③ SEL3
PGND
⑩ PGND
Timer
latch
FB voltage
dtection
① CP
PGND
⑨ GND
5. Pin assignment
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Pin
symbol
CP
RT
SEL3
VREF
SEL2
IN1+
IN1FB1
GND
PGND
CS1
OUT1
OUT2
CS2
OUT3
CS3
PVCC
VCC
FB2
IN2IN2+
FB3
IN3IN3+
Description
Timer latched short circuit protection
Oscillator timing resistor
Selection of type of driven MOSFET(OUT3)
Reference voltage
Selection of type of driven MOSFET(OUT2)
Ch.1 non-inverting input to error amplifier
Ch.1 inverting input to error amplifier
Ch.1 output of error amplifier
Ground
Ground for driver
Soft start for Ch.1
Ch.1 output
Ch.2 output
Soft start for Ch.2
Ch.3 output
Soft start for Ch.3
Power supply for driver
Power supply
Ch.2 output of error amplifier
Ch.2 inverting input to error amplifier
Ch.2 non-inverting input to error amplifier
Ch.3 output of error amplifier
Ch.3 inverting input to error amplifier
Ch.3 non-inverting input to error amplifier
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FA7711V
6. Ratings and characteristics
(1)Absolute maximum ratings
Item
Symbol
Power supply voltage (VCC,PVCC pin)
VCC
SEL2,SEL3 pin voltage
VSEL
FB1,IN1-,IN1+,FB2,IN2-,IN2+,FB3,IN3-,I
VEA_IN
N3+ pin voltage
CS1,CS2,CS3,CP,RT,VREF pin voltage
VCTR_IN
OUT1/2/3 pin source current
IOUTOUT1/2/3 pin sink current
IOUT+
OUT1/2/3 pin source current
IOUTOUT1/2/3 pin sink current
IOUT+
Power dissipation
Pd
Operating junction temperature
Tj
Operating ambient temperature
TOPR
Storage temperature
TSTG
Conditions
Ta≦25℃
Ratings
30
- 0.3 to 5.0
Units
V
V
- 0.3 to 5.0
V
- 0.3 to 5.0
- 800(peak)
+800(peak)
- 50(continuous)
+50(continuous)
800
+125
- 20 to +85
- 40 to +125
V
mA
mA
mA
mA
mW
℃
℃
℃
*1: IC is soldered on glass-epoxy printed board (40mm×80mm×1.6mm).
Derating factor Ta≧25℃ :8mW/℃
Maximum power dissipation curve
Maximum power dissipation
[mW]
1000
800
600
400
200
0
-20
0
20
40
60
80
100
120
140
Ambient temperature [℃]
Thermal resistance:θj-c(Junction to Case)=70℃/W
IC is soldered on glass-epoxy printed board (40mm×80mm×1.6mm).
(2)Recommended operating conditions
Item
Symbol
Condition
Power supply voltage (VCC)
VCC
Power supply voltage (PVCC) *2
VPCC
CS1,CS2,CS3,CP pin voltage
VCTR_IN
SEL2,SEL3 pin voltage
VSEL_IN
IN1-,IN1+,IN2-,IN2+,IN3-,IN3+
VEA_IN
pin voltage
Oscillation frequency
fOSC
VREF pin capacitance
CREF
VCC pin capacitance
CVCC
PVCC pin capacitance
CPVCC
CS1,CS3 pin capacitance
CCS1 Between CS1/3 and GND
Between CS2 and VREF
CS2 pin capacitance
CCS2
Between CP and GND
CP pin capacitance
CCP
*2: Apply the same voltage to Vcc, PVCC pins.
MIN.
4.5
4.5
0.0
0.0
TYP.
－
－
－
－
MAX.
28
28
4.1
4.1
Unit
V
V
V
V
0.0
－
4.1
V
200
1.0
1.0
1.0
0.1
0.1
0.01
－
－
－
－
－
－
－
800
4.7
－
－
－
－
－
kHz
μF
μF
μF
μF
μF
μF
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FA7711V
(3)Electrical chracteristics
・ The characteristics is based on the condition of VCC=12V，CREF=1.0 μF，RT=9.0kΩ，Ta=+25℃,unless
otherwise specified
(1)Refreence voltage section (VREF pin)
Item
Reference voltage
Symbol
Condition
VREF
Line regulation
VREF_LINE
Load regulation
VREF_LOAD
Variation with temperature
VREF_TC1
VCC=4.5 to 28V,IREF=0mA
IREF=0 to 7mA,VCC=8V to 28V
MIN.
TYP.
MAX.
Unit
3.663
3.700
3.737
V
－
±8
±25
mV
- 20
-5
IREF=0 to 1mA,VCC=4.5V to 8V
mV
-5
Ta=- 20 to +85℃
±0.5
%
(2)Oscillator section (RT pin)
Item
Oscillation frequency
Symbol
fOSC
Condition
RT=9.0kΩ
Line regulation
fOSC_LINE
VCC=4.5 to 28V
Variation with temperature
fOSC_TC1
Ta=- 20 to +85℃
MIN.
TYP.
MAX.
Unit
500
560
620
kHz
－
±1
±5
%
±3
%
(3)Error Amplifier section (IN1+，IN1-，FB1，IN2+，IN2-，FB2，IN3+，IN3-，FB3 pin)
Item
Symbol
Condition
MIN.
TYP.
MAX.
Unit
―
―
±10
mV
Input offset voltage
VOFFSET
VIN+=1.8V，IN+ - IN-
Line regulation (Input offset)
VOFF_LINE
VCC=4.5 to 28V
0
mV
VIN=0.0 to 5V
0
μA
Input current
IIN
Common mode input voltage
VCOM
Open loop gain
AVO
70
dB
fT
1.5
MHz
Unity gain bandwidth
0.5
Output sink current
ISIFB
VFB=0.5V,VIN-=VREF,VIN+=1.8V
Output source current
ISOFB
VFB=VREF- 0.5V,VIN-=0V,VIN+=1.8V
2.7
V
1.9
2.7
3.5
mA
- 280
- 185
- 90
μA
MIN.
TYP.
MAX.
Unit
(4)Soft start section (CS1，CS2，CS3 pin)
Item
Symbol
Condition
Threshold voltage (CS3)
VCS3D20N
DUTY3=20%,VFB3=2.8V
1.4
1.5
1.6
V
(Driving Nch-MOSFET)
VCS3D80N
DUTY3=80%,VFB3=2.8V
2.0
2.1
2.2
V
Threshold voltage (CS1/3)
VCS1/3D0P
DUTY1/3=20%,VFB1/3=2.8V
1.4
1.5
1.6
V
(Driving Pch-MOSFET)
VCS1/3D20P
DUTY1/3=80%,VFB1/3=2.8V
2.0
2.1
2.2
V
Threshold voltage (CS2)
VCS2D20N
DUTY2=20%,VFB2=0.8V
2.0
2.1
2.2
V
(Driving Nch-MOSFET)
VCS2D80N
DUTY2=80%,VFB2=0.8V
1.4
1.5
1.6
V
Threshold voltage (CS2)
VCS2D20P
DUTY2=20%,VFB2=0.8V
2.0
2.1
2.2
V
(Driving Pch-MOSFET)
VCS2D80P
DUTY2=80%,VFB2=0.8V
1.4
1.5
1.6
V
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FA7711V
(5)Pulse width modulation section (FB1，FB2，FB3 pin)
Item
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Threshold voltage (FB3)
VFB3D20N
DUTY3=20%,VCS3=VREF
1.5
V
(Driving Nch-MOSFET)
VFB3D80N
DUTY3=80%,VCS3=VREF
2.1
V
Threshold voltage (FB1/3)
VFB1/3D20P
DUTY1/3=20%,VCS1/3=VREF
1.5
V
(Driving Pch-MOSFET)
VFB1/3D80P
DUTY1/3=80%,VCS1/3=VREF
2.1
V
Threshold voltage (FB2)
VFB2D20N
DUTY2=20%,VCS2=0V
2.1
V
(Driving Nch-MOSFET)
VFB2D80N
DUTY2=80%,VCS2=0V
1.5
V
Threshold voltage (FB2)
VFB2D20P
DUTY2=20%,VCS2=0V
2.1
V
(Driving Pch-MOSFET)
VFB2D80P
DUTY2=80%,VCS2=0V
1.5
V
(6)Under voltage lockout section (VCC pin)
Item
Symbol
ON threshold voltage of VCC
VUVLOON
Hysteresis voltage
VUVLOHYS
Condition
MIN.
TYP.
MAX.
Unit
2.6
3.3
4.0
V
0.1
V
(7)Timer latch protection section (CP pin)
Item
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Threshold voltage of FB1
VTHFB1ON
*7-1
2.8
3.0
3.2
V
Threshold voltage of FB2
VTHFB2ON
*7-2
0.4
0.6
0.8
V
Threshold voltage of FB3
VTHFB3ON
*7-3
2.8
3.0
3.2
V
Charge current of CP
ICP
VCP=0.5V,VFB1=VREF- 0.5V
- 3.5
- 2.5
- 1.5
μA
Threshold voltage of CP
VTHCPON
2.8
3.0
3.2
V
*7-1:The current source of the CP pin operates when the voltage of FB1 exceeds the threshold voltage as shown in the table
*7-2:The current source of the CP pin operates when the voltage of FB2 fall below the threshold voltage as shown in the table
*7-3:The current source of the CP pin operates when the voltage of FB3 exceeds the threshold voltage as shown in the table
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FA7711V
(8)Output section (OUT1，OUT2，OUT3，SEL2，SEL3 pin)
Item
Symbol
Condition
MIN.
TYP.
MAX.
Unit
High side on resistance
RONHI
IOUT=- 100mA
3
5
Ω
Low side on resistance
RONLO
IOUT=+100mA
3
5
Ω
Rise time
(Driving Pch-MOSFET)
Fall time
(Driving Pch-MOSFET)
Rise time
(Driving Nch-MOSFET)
Fall time
(Driving Nch-MOSFET)
SEL2/3 pin voltage for driving
Nch-MOSFET
SEL2/3 pin voltage for driving
Pch-MOSFET
tRISEP
tFALLP
tRISEN
tFALLN
30
VCC- OUT:7Ω+2000pF
*8-1
ns
30
30
OUT- GND:7Ω+2000pF
*8-2
ns
30
VSELN
0.0
―
0.35
V
VSELP
VREF
- 0.35
―
VREF
V
MIN.
TYP.
MAX.
Unit
7
9
mA
RT=5.7kΩ
8
11
latch mode
4
(9)Overall section
Item
Symbol
ICCOP
Operating mode
supply current
ICCD100
Condition
Operating mode
RT=9.0kΩ
mA
*8-1
*8-2
90%
50%
10%
tRISE
tFALL
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FA7711V
7. Characteristic curves
Oscillation Frequency vs. Supply Voltage
900
570
800
568
Oscillation Frequency [kHz]
Oscillation frequency [kHz]
Timing resistor vs. Oscillation frequency
700
600
500
400
300
200
100
0
564
562
560
558
556
554
552
550
0
5
10
15
20
Timing resistor RT [kΩ]
25
30
0
10
15
20
25
30
Reference Voltage vs. Supply Voltage IREF = 0mA
3.720
3.715
Rerfernce Voltage VREF [V]
570
565
560
555
3.710
3.705
3.700
3.695
3.690
3.685
3.680
550
0
-50
3.76
-25
0
25
50
75
100
Ambient temperatureTa [℃]
125
5
150
10
15
20
25
30
10
12
Supply Voltage Vcc [V]
Reference voltage vs. Load current
Reference voltage vs. Ambient temperature
IREF=0A
3.75
3.74
Reference voltage V REF[V]
Reference voltage V REF[V]
5
Vcc [V]
Oscillation frequency vs. Ambient temperature
Oscillation frequency [kHz]
566
3.72
3.70
3.68
3.66
3.64
3.62
3.73
3.71
3.69
3.67
3.65
3.60
-50
-25
0
25
50
75
100
Ambient temperature Ta [℃]
125
0
150
2
4
6
8
Load current IREF[mA]
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FA7711V
FB pin voltage vs. Duty cycle
OUT1
100
90
focs=560kHz
80
70
60
focs=800kHz
50
40
30
focs=560kHz
70
60
focs=800kHz
50
40
30
20
20
10
10
0
0
1.2
1.4
1.6
1.8
2.0
FB1 pin voltage [V]
2.2
2.4
1.2
FB pin voltage vs. Duty cycle
OUT2:Pch driven
100
90
90
Duty cycle [%]
focs=800kHz
60
50
40
30
2.2
2.4
focs=560kHz
70
60
focs=800kHz
50
40
30
20
20
10
10
0
1.6
1.8
2.0
FB3 pin voltage [V]
focs=200kHz
80
focs=560kHz
70
1.4
FB pin voltage vs. Duty cycle
OUT3:Nch driven
100
focs=200kHz
80
Duty cycle [%]
focs=200kHz
80
Duty cycle [%]
Duty cycle [%]
100
focs=200kHz
90
FB pin voltage vs.Duty cycle
OUT3:Pch driven
0
1.2
1.4
1.6
1.8
2.0
FB2 pin voltage [V]
2.2
2.4
1.2
1.4
1.6
1.8
2.0
FB3 pin voltage [V]
2.2
2.4
FB pin voltage vs.Duty cycle
OUT2:Nch driven
100
90
Duty cycle [%]
80
70
60
50
focs=800kHz
40
30
focs=560kHz
20
10
focs=200kHz
0
1.2
1.4
1.6
1.8
2.0
FB2 pin voltage [V]
2.2
2.4
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FA7711V
CS pin voltage vs. Duty cycle
OUT1
100
90
focs=560kHz
80
70
60
focs=800kHz
50
40
30
focs=560kHz
70
60
focs=800kHz
50
40
30
20
20
10
10
0
0
1.2
1.4
1.6
1.8
2.0
CS1 pin voltage [V]
2.2
2.4
1.2
CS pin volatege vs. Duty cycle
OUT2:Pch driven
100
80
Duty cycle [%]
focs=800kHz
40
30
2.4
50
30
10
0
0
2.2
2.4
focs=800kHz
40
20
1.6
1.8
2.0
CS2 pin voltage [V]
2.2
60
10
1.4
2.4
70
20
1.2
2.2
80
focs=560kHz
50
1.6
1.8
2.0
CS3 pin voltage [V]
90
70
60
1.4
CS pin voltage vs. Duty cycle
OUT3:Nch driven
100
focs=200kHz
90
Duty cycle [%]
focs=200kHz
80
Duty cycle [%]
Duty cycle [%]
100
focs=200kHz
90
CS pin voltage vs. Duty cycle
OUT3:Pch driven
focs=560kHz
focs=200kHz
1.2
1.4
1.6
1.8
2.0
CS3 pin voltage [V]
CS pin voltage vs. Duty cycle
OUT2:Nch driven
100
90
Duty cycle [%]
80
70
60
50
40
focs=800kHz
30
focs=560kHz
20
10
focs=200kHz
0
1.2
1.4
1.6
1.8
2.0
CS2 pin voltage [V]
2.2
2.4
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FA7711V
CP pin charge current vs. Ambient temperature
FB2 pin threshold voltage vs. Ambient temperature
0.70
FB2 pin threshold voltage [V]
CP pin charge current [μA]
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
0.65
0.60
0.55
0.50
-50
-25
0
25
50
75
100
Ambient temperature Ta [℃]
125
-50
150
CP pin threshold voltage vs. Ambient temperature
125
150
3.60
UVLO threshold voltage [V]
CP pin threshold voltage [V]
0
25
50
75
100
Ambient temperature Ta [℃]
UVLO threshold voltage vs. Ambient temperature
3.10
3.05
3.00
2.95
2.90
3.50
3.40
3.30
3.20
3.10
3.00
-50
-25
0
25
50
75
100
Ambient tenperature Ta [℃]
125
150
-50
-25
0
25
50
75
100
Ambient temperature Ta [℃]
125
150
Operationg Mode Supply Current vs. Supply Voltage
FB1/3 pin threshold voltage vs. Ambient temperature
3.10
16
f=800kHz
14
Operating Mode Supply
Current [mA]
FB1/3 pin threshold voltage [V]
-25
3.05
3.00
2.95
12
f=560kHz
10
8
f=200kHz
6
4
2
2.90
-50
-25
0
25
50
75
100
Ambient temperature Ta [℃]
125
0
150
0
5
10
15
20
25
30
35
Supply Voltage Vcc [V]
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FA7711V
OUT pin Low side voltage vs.Sink current
0.8
OUT pin sink current [A]
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.0
0.5
1.0
1.5
2.0
OUT pin voltage [V]
2.5
3.0
OUT pin High side voltage vs. Source current
Out pin source current [A]
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.0
0.5
1.0
1.5
2.0
OUT pin voltage [V]
2.5
3.0
Error Amplifier gain and Phase vs. frequency
80
180
60
20
0
0
-20
PHASE [deg]
GAIN [dB]
40
-40
-60
-80
-180
100
1k
10k
100k
Frequency [Hz]
1M
10M
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FA7711V
8. Description of each circuit
（1）Reference voltage circuit
The circuit generates the reference voltage (VREF)
of 3.70V±1% compensated in temperature from VCC
voltage. This voltages start to output when the
undervoltage lockout protection (UVLO) is cancelled,
and they stabilize after the supply voltage (VCC)
reaches up to approx. 4.0V or higher.
The voltage (VREF) outputs externally from REF Pin,
therefore, it can serve as a stabilized power source
for reference voltage of Error Amplifier and maximum
output duty setting or the like. The output current
circuit should be within 1mA. (In case of VCC=8V to
28V should be within 7mA) The VREF voltage also is
used as a regulated power supply for IC’s internal
blocks.
VREF pin have to connect capacitors CREF for in
order to stabilize voltages (To determine capacitance,
refer to recommended operating conditions).
4
Vout1
6
7
8
21
20
19
Vout2
23
22
RT Value:lage
OSC
1.3V
2
For PW M
comparator
IN1-
FB1
IN2+
Er.AMP2
For PW M
comparator
IN2-
FB2
IN3+
Er.AMP3
For PW M
comparator
IN3-
FB3
（4）PWM comparator
The PWM output generates from the oscillator
output, the error amplifier output (FB1, FB2 and
FB3) and CS voltage (CS1, CS2 and CS3) (Fig. 4).
The oscillator output is compared with the preferred
lower voltage between FB and CS for ch1 and ch3.
While the preferred voltage is lower than oscillator
output, the PWM output is low. While the preferred
voltage is higher than oscillator output, the PWM
output is high. Since the phase of Ch2 is the
opposite phase of ch1 and ch3, higher voltage
between FB2 and CS2 is preferred and while the
preferred voltage is lower than the oscillator output,
the PWM output 2 is high. (Cannot be observed
externally)
The output duty changes sharply around the
minimum and the maximum output duty. This
phenomenon occurs more conspicuously when
operating in a high frequency (i.e. when the
pulse width is narrow). Cautious care must be
taken when using high frequency.
The output polarity of OUT1, OUT2 changes
according to the condition of SEL pin. (See Fig. 6)
Fig.2
FB1
Fig.1
Er.AMP1
Fig.3
2.3V
RT
IN1+
Vout3
24
（2）Oscillator
The oscillator generates triangular waveforms by
charging and discharging the built-in capacitor.
Any desired oscillation frequency can be obtained
by setting the value of the resistor connected to
RT Pin (Fig. 1).
The voltage oscillates between approximately
1.3V and 2.3V in charging and discharging with
almost the same gradients (Fig. 2). Your desired
oscillation frequency can be determined by
changing the gradient using the resistor (RT)
connected to RT Pin. (Large RT: Low frequency,
small RT: High frequency) The waveforms of
oscillator cannot be observed from the outside
because a Pin for this purpose is not provided.
Approximately DC 1V is output to RT Pin.
The oscillator output is connected to PWM
comparator.
RT value:small
VREF
PW M
output.1
PW M
Comp.1
RT
OSC
（3）Error amplifier
Error Amplifier has the inverting input IN*(-) Pin
(Pin7, Pin20 and pin23) and non-inverted input
IN*(+) Pin (Pin6, Pin21 and pin24) outputting
externally, various circuit can be designed by
kinds of external circuit structures. FB Pins (Pin,
Pin19 and pin22) are the outputs of Error
Amplifiers. Voltage Gain and phase compensation
can be set by connecting a capacitor (C) and a
resistor (R) between FB Pin and IN*(-) Pin.(Fig.
3) For more information about the connection for
each output voltage of power supply, refer to
Design Advice.
Pch
driv e
CS1
FB2
12 OUT1
PW M
output.2
PW M
Comp.2
N/P ch
driv e
CS2
13 OUT2
5 SEL2
FB3
PW M
output.3
PW M
Comp.3
N/P ch
driv
CS3
15 OUT3
3 SEL3
UVLO
Fig.4
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FA7711V
（6）Timer latched short-circuit protection
This IC has the timer latch short-circuit protection
circuit. This circuit cuts off the output of all channels
when the output voltage of DC-to-DC converter drops
due to short circuit or overload. To set delay time for
timer latch operation, a capacitor CCP should be
connected to the CP pin (Fig. 7).
（5）Soft start circuit
This IC has a soft start function to protect DC-to-DC
converter circuits from damage when starting
operation. CS1 pin (Pin11), CS2 pin (pin14) and CS3
pin (Pin16) are used for soft start function of ch1, ch3
and ch2 respectively. (Fig. 5)
When the supply voltage is applied to the VCC pin
and UVLO is cancelled, capacitor CCS1, CCS2 and
CCS3 is charged by VREF through the resistor RCS1 ,
RCS2 or RCS3. Therefore, CS1 and CS3 voltage
gradually increases and CS2 voltage gradually
decreases. Since CS1, CS2 and CS3 pin are
connected to the PWM comparator internally, the
pulses gradually widen and then the soft start
function operates. (Fig. 6)
The maximum duty cycle can be set by using the CS
pins. (See Design Advice about the detail)
R CS1
4
VREF
11
CS1
C CS2
4
VREF
14
C S2
R CS3
R CS2
C CS1
4
VREF
16
CS3
I CP
1
V CP
C CP
Fig.7
When one of the output voltage of the DC-to-DC
converter drops due to short circuit or overload, the
FB1 and FB3 pin voltage increases up to around the
VREF voltage for ch1 and ch3, or the FB2 pin
voltage drops down to around 0 V for ch2. When FB1
and FB3 pin voltage exceeds 3.2V(max.) or FB2 pin
voltage falls below 0.4V(min.), constant-current
source (2.5μA typ.) starts charging the capacitor CCP
connected to the CP pin. If the voltage of the CP pin
exceeds 3.2 V (max.), the circuit regards the case as
abnormal. Then the IC is set to off latch mode and
the output of all channels is shut off, (Fig. 8) and the
current consumption become 4mA(typ.) The period
(tp) between the occurrence of short-circuit in the
converter output and setting to off latch mode can be
calculated by the following equation:
C CS3
Fig.5
tp[s ] = CCP ×
Oscillator output
CP
Error Amplifier 1,3 output
CS1 ，CS3 pin voltage
VTHCPON
ICP
VTHCPON: CP pin latched mode threshold voltage [V]
ICP: CP charge source current[μA]
CCP: capacitance of CP pin capacitor[μF]
PW M output 1 ，3
CP pin voltage [V]
3.2V(max)
OUT1
OUT3 Pch driv en
(SEL3 ：VREF)
OUT3 Nch driv en
(SEL3 ：G ND)
momentary
short circuit
short circuit
VREF voltage
3.0V
short circuit
protection
2.0V
Start-up
1.0V
tp
CS2 pin voltage
Oscillator output
Time t
Error Amplifier 2 output
Fig.8
You can reset off latched mode of the short-circuit
protection by either of the following ways about 1) CP
pin, or 2) VCC pin:
1) CP voltage = 0V
2) VCC voltage UVLO voltage (3.3V, typ.) or below
PW M output 2
O UT2 Pch driv en
(SEL2 ：VREF)
If the timer-latched mode is not necessary, connect
the CP pin to GND.
O UT2 Nch driv en
(SEL2 ：G ND)
Fig.6
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FA7711V
（7）Output circuit
The IC contains a push-pull output stage and can
directly drive MOSFETs. The maximum peak current
of the output stage is sink current of +800mA, and
source current of - 800mA. The IC can also drive
NPN and PNP transistors. The maximum current in
such cases is ± 50mA. You must design the output
current considering the rating of power dissipation.
(See Design Advice)
You can switch the types of external discrete
MOSFETs by wiring of the SEL pins (Pin 3, Pin 5).
For driving Nch MOS, connect the SEL pins to GND.
For driving Pch MOS, connect the SEL pins to VREF.
You can design buck converter or inverting converter
by driving Pch MOS, and boost converter by driving
Nch MOS.
Connect them either to GND or to VREF surely.
（8）Under voltage lockout circuit（UVLO）
The IC contains a under voltage lockout circuit to
protect the circuit from the damage caused by
malfunctions when the supply voltage drops. When
the supply voltage rises from 0V, the IC starts to
operate at VCC of 3.3V(typ.) and outputs generate
pulses. If a drop of the supply voltage occurs, it stops
output at VCC of 3.2V(typ.). When it occurs, the CS1
and CS3 pin are turned to low level and the CS2 pin
to high level, and then these pins are reset.
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FA7711V
9. Design Advice
（1）Setting the oscillation frequency
As described at Section 8-(2), “Description of Each
Circuit,” a desired oscillation frequency can be
determined by the value of the resistor connected to
the RT pin. When designing an oscillation frequency,
you can set any frequency between 200kHz and
800kHz. You can obtain the oscillation frequency
from the characteristic curve “Oscillation frequency
(fosc) vs. timing resistor resistance (RT)” or the value
can be approximately calculated by the following
expression.
To reset the soft start function, the voltage of CS
pin is discharged with internal switch triggered by
lowering the voltage of Power supply below the
voltage of UVLO (3.3V, typ.). If Power supply
restarts before the voltage is sufficiently
discharged, the soft start function might not
properly operate. Accordingly, cautious care must
be taken about it.
Vcc
Threshold v oltge
(3.3V typ.)
fosc = 4.1× 10 3 × RT −0.905
CS pin v oltage
V CSn
1.105
⎛ 4.1× 10 3 ⎞
⎟⎟
RT = ⎜⎜
⎝ fosc ⎠
t0
fosc: oscillation frequency [kHz]
RT ：timing resistor [kΩ]
This expression, however, can be used for rough
calculation, the obtained value is not guaranteed.
The operation frequency varies due to the conditions
such as tolerance of the characteristics of the ICs,
influence of noises, or external discrete components.
When determining the values, examine the
effectiveness of the values in an actual circuit. The
timing resistor RT should be wired to the GND pin as
shortly as possible because the RT pin is a high
impedance pin and is easy affected by noises.
（3）Setting the maximum output duty
If you need to control the maximum output duty
in the DC-DC converter circuit, you can control
pulse width by connecting VREF pin to CS pin
divided with resistors, as described in Fig. 10.
The output duty of the voltage of CS pin in this
case changes according to the operation
frequency, as described in the chart of “CS pin
voltage vs. Duty cycle” characteristic curves. Set
the output duty accordingly based on your
required operation frequency.
When the maximum duty cycle is limited, CS pin
voltage at start-up is described in Fig. 11, and the
approximate value of soft start period can be
obtained by the following expressions:
（2）Determining soft start period
The period from the start of charging the capacitor
CCS to widening n% of output duty cycle can be
roughly calculated by the following expression: (see
Fig. 5 for symbols)
4
R1
For CS1:
VREF
⎛
⎞
ts1[ms ] = RCS1 ⋅ CCS1 ⋅ ln⎜
⎟
⎝ VREF − VCS1n ⎠
11
R2
VREF
CS1
R4
R3
C CS2
4
VREF
14
CS2
4
VREF
16
CS3
R5
R6
C CS1
C CS3
For CS2
Fig.10
⎛ VREF ⎞
ts 2[ms ] = RCS 2 ⋅ CCS 2 ⋅ ln⎜
⎟
⎝ VCS 2n ⎠
R2
･V REF
R1+R2
R6
R5+R6 ･V REF
CS1,3 pin v oltae
V CS1n
V CS3n
For CS3
V CS2n
R3
R3+R4 ･V REF
VREF
⎛
⎞
ts 3[ms ] = RCS 3 ⋅ CCS 3 ⋅ ln⎜
⎟
⎝ VREF − VCS 3n ⎠
ｔs
CCS1,CCS2,CCS3 :
Capacitance connected to CS* pin [μF]
RCS1,RCS2,RCS3 :
Resistance connected to CS* pin [kΩ]
Fig.11
CS2 pin v oltge
ｔs
For CS1
VCS1
⎛
⎞
ts1[ms ] = R 0 ⋅ CCS1 ⋅ ln⎜
⎟
⎝ VCS1 − VCS1n ⎠
R1 ⋅ R 2
R2
R0 =
VCS1 =
⋅VREF
R1 + R 2
R1 + R 2
VCS*n represents the voltage of CS Pin in the
output duty of n%, and it changes according to
the operation frequency. The value is obtained
simply from the chart of “CS Pin voltage vs.
output duty cycle” characteristic curves.
Charging of CS Pin begins after UVLO is
cancelled. Note that the time from power-on of
Power supply to start of charging Ccs* is t0,
which is not zero as described in Fig. 8. Be
careful.
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Fig.9
ts
For CS2
⎛ VREF − VCS 2 ⎞
ts 2[ms ] = R 0 ⋅ CCS 2 ⋅ ln⎜
⎟
⎝ VCS 2n − VCS 2 ⎠
R3 ⋅ R 4
R3
R0 =
VCS 2 =
⋅VREF
R3 + R 4
R3 + R 4
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FA7711V
For CS3
（5）Restriction and recommended operating
conditions of external discrete component
To achieve a stable operation of the IC, the value of
external discrete components connected to VCC,
PVCC, VREF, CS, CP pins should be within the
recommended operating conditions. And the voltage
and the current applied to each pin should be also
within the recommended operating conditions.
If the pin voltage of OUT1, OUT2, or VREG
becomes higher than the VCC pin voltage, the
current flows from the pins to the VCC pin because
parasitic three diode exist between the VCC pin and
these pins. Be careful not to allow this current to flow.
VCS 3
⎛
⎞
ts 3[ms ] = R 0 ⋅ CCS 3 ⋅ ln⎜
⎟
⎝ VCS 3 − VCS 3n ⎠
R5 ⋅ R 6
R6
R0 =
VCS 3 =
⋅VREF
R5 + R6
R5 + R 6
CCS1,CCS2,CCS3 :
Capacitance connected to CS* pin [μF]
R1 to R6 : Resistance connected to CS* pin [kΩ]
The output duty changes sharply around the
minimum and the maximum output duty. This
phenomenon occurs more conspicuously when
operating in a high frequency (i.e. when the pulse
width is narrow). Cautious care must be taken
when using high frequency.
（6）Performance of output stage
The performance of output stages is the sink
current (peak) of 800mA of and the source current
(peak) of -800mA.
Switching speed is effected by external switching
device, especially at high frequency, so examine the
external switching device and frequency carefully.
If the performance of the ICs is not sufficient for your
design, consider adding a buffer circuit to improve
the performance.
（4）Pull-up/Pull-down resistor at the output
section
The power supply for control blocks of OUT pin
drivers is the VREF. The VREF voltage is not
operated at the condition of IC’s power supply VCC
below the UVLO voltage. Therefore, OUT* pins are
unstable at VCC below the UVLO voltage.
If you have this condition of VCC and possibility of
some trouble by unstable OUT* pins, connect pull up
or pull down resistor to OUT* pins. (Fig.12)
（7）Loss Calculation
Since it is difficult to measure IC loss directly, the
calculation to obtain the approximate loss of the IC
connected directly to a MOSFET is described below.
When the supply voltage is VCC, the current
consumption of the IC is ICCOP, the total input gate
charge of the driven MOSFET is Qg and the
switching frequency is fsw, the total loss Pd of the IC
can be calculated by:
Pd ≒ VCC*(ICCop+Qg*fsw).
The value in this expression is influenced by the
effects of the dependency of supply voltage, the
characteristics of temperature, or the tolerance of
parameter. Therefore, evaluate the appropriateness
of IC loss sufficiently considering the range of values
of above parameters under all conditions.
For Nch driven
VIN
VCC
18
17
PVCC
V REF
OUT
CTRL
9
10
PGND
GND
Example)
ICCOP=7mA for VCC=12V in the case of a typical IC
from
the
characteristics
curve.
Qg=10nC,
fsw=560kHz, the IC loss ”Pd” is as follows.
Pd≒12*(7mA+10nC*560kHz)≒151mW
if two MOSFETs are driven under the same
condition for 3 channels, Pd is as follows:
Pd≒12*{7mA+3*(10nC*560kHz)}=286mW
For Pch driven
VIN
VCC
18
17
PVCC
V REF
OUT
CTRL
9
GND
10
PGND
Fig.12
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FA7711V
（8）Attention for driving bipolar transistor
If you use bipolar transistor as a switching device,
connect resistor RB between Base of transistor and
OUT* pin, else there is a possibility of destroy the IC
by over current because OUT* pin driver does not
contain a current limit resistor. (Fig.13) Output current
of OUT* pins are below 40mA (continuous).
The connection of capacitor CB is effective for speed
up the switching.
R55 = R52 = 200k ohm and R56 = R53 = 1M ohm
are selected, base resistor voltage of R52, R53, R55
and R56 are over 370mV and these satisfy “ 300mV
condition ”. Therefore, this condition achieves normal
transistor operation.
Resistance of R57 and R58 should be smaller than
20% of above condition in order to obtain small hFE
（9）ON/OFF control
ON/OFF control using CS pin is not available when
timer latch function is enable. In order to carry out
ON/OFF control with CS pin, CP pin should be
connected to GND so that timer latch function will be
disable as shown in Fig.14.
For ch.1 and ch.3, output pulses are disabled by
lowering CS pin voltage around zero. Ch.1 is
controlled by CS1 pin and ch.3 is controlled by CS3.
For ch.2, pulling up CS2 pin voltage to VREF voltage
disables output pulses.
Each channel will re-start operation with soft-start
function when CS pin is opened.
of “ 20 ” which achieves low saturation voltage of Q**.
In this case, if Vcc = 17V (min.) and voltage drop
of R57 and R58 = Vcc - 2V,
R57 or R58
< 20% * (17V - 2V ) / (1.85 uA + 0.37 uA )
= 1.35 M ohm
VIN
VCC
Fig.15 shows ON/OFF control method for Ch.1 and
Ch.3 when timer latched short protection is used for
all channels.
Please take care of that Ch.2 is not suitable for
ON/OFF control, because the error amplifier of Ch.2
sinks large current ( much larger than 2.7mA ) for
High Voltage of FB2 pin to stop switching of OUT2
pin.
18
17
PVCC
OUT
RB
CB
10
9
PGND
GND
The calculation example of ON/OFF circuit in Fig.15
VIN
is as follows.
VCC
18
17
PVCC
CB
VREF -> CS1 maximum current “ Ics1max ”
= VREF / R18 ( ex. 3.7V / 100k ohm = 37uA )
RB
OUT
VREF -> CS3 maximum current “ Ics3max ”
= VREF / R38 ( ex. 3.7V / 100k ohm = 37uA )
9
Error Amp. Output Source Current “ ISOFB ”
10
PGND
GND
= 185uA ( typ. ) for FB1 pin and FB3 pin
Fig.13
The base current ratio of QFB* and QCS* should be
same as the collector current ratio for each channel.
ON/OFF
CTRL
( above case : collector current ratio = 185 / 37 = 5
ch1
-> Base resistor ratio = R56 / R55 = R53 / R52 = 5 )
C CS1
Base resistor voltage drop should be larger than
ch3
300mV in order to obtain good sharing of base
current for QFB* and QCS*.
C CS3
4
VREF
11
CS1
16
CS3
C CS2
ch2
Here, assuming hFE less than 100 of Q**,
14
CS2
CP
1
each base current are over 1.85uA and over 0.37uA.
If R57 and R58 values to flow current over
Fig.14
( 1.85 uA + 0.37 uA ) are designed and
Timer latched Short Protection : not available
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FA7711V
3.7V
Rcs 3
100k
CS3
0.1u F
ex . 17V
R58 : 100k
23
IN3-
22
FB 3
21
IN2+
20
IN2-
19
FB2
18
VCC
17
PVCC
16
CS3
15
OUT3
14
CS2
ch 3: 1.2V / 0V
13
OUT2
FA7711V
CV : 0.1u F
24
IN3+
Max im u m sou rce
cu rren t :
185u A(typ .)
R54
1k
R55
200k
R56
1M
Q FB3
Q CS3
Q A3
R61: 100k R62: 10k
4.7n
4.7k
R57 : 100k
SE L3
3
VRE F
4
SEL2
5
IN1+
6
IN17
FB 1
8
GND
9
PG ND
10
RT
18k
OUT1
12
Maxim u m
s o u rce
cu rren t :
185u A(typ .)
4.7n
CP
0.1u F
CS1
11
ch 1: 1.2V / 0V
R51
1k
R52
200k
R53
1M
Q FB1
Q CS1
R60: 10k
RT
2
Q A1
4.7k
REF
2.2u F
R59: 100k
IC1
CP
1
3.7V
R cs 1
100K
CS1
0.1u F
Fig.15 ON/OFF Circuit
Note : Channel 2 to control OUT2 pin is not
suitable for ON/OFF control.
QA1, QA3:
R51, R54 :
Assuming base voltage as 0.9 V ( max. ),
The voltage drop should be lower than 0.5 V at FB1
R59, R60, R61 and R62 should be designed so that the
pin or FB3 pin to obtain 0% duty for ON mode of
base current are larger than each collector current /
QFB*.
ex. R51 * ISOFB = 1k ohm * 185 uA
= 0.185 V
< 0.5 V
20.
Here, 20 means fully small hFE in order to
obtain low saturation voltage of QA*.
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FA7711V
（10）Setting of the output voltage of DC-DC
converter
Figure 16,17,18 shows the ways to set each
channel of the output voltage of DC-DC converter.
R REF2
R REF1
*
4
Vout1
V1
R10
*
・ Applications for each channels
Ch1
Buck, Inverting
Ch2
Buck, Boost, Inverting, Fly-back
Ch3
Buck, Boost, Inverting, Fly-back
R11
VREF
V2
R20
R21
Vout3
In the case of a boost, a buck, or a fly-back circuit,
the output voltage can be calculated with:
Vout2
V3
R30
R31
6
IN1+
7
IN1-
8
FB1
21
IN2+
20
IN2-
19
FB2
24
IN3+
23
IN3-
22
FB3
Vout1
VREF
Er.AMP1
OUT1
12
Vout2
Er.AMP2
OUT2
13
SEL2
5
VREF
Vout3
Er.AMP3
OUT3
15
SEL3
3
Fig.16
For Ch1 (Fig.16,Fig.17)
Vout1 =
R10 + R11
×V1
R11
R REF6
R REF4
For Ch2 (Fig.17,Fig.18)
Vout 2 =
R REF2
R 20 + R 21
×V 2
R 21
V1
R 30 + R 31
×V 3
R 31
IN1+
7
IN1-
8
FB1
21
IN2+
20
IN2-
R11
R20
R21
Er.AMP1
OUT1
12
Vout2
19
FB2
24
IN3+
23
IN3-
22
FB3
Er.AMP2
OUT2
13
SEL2
5
VREF
Vout3
VREF
For Ch1 (Fig.18)
R31
R11
R10 + R11
×V 1 −
×VREF
R10
R10
Er.AMP3
OUT3
15
SEL3
3
VREF
Fig.17
Vout3
For Ch2 (Fig.16)
R REF6
R 20 + R 21
R 21
×V 2 −
×VREF
R 20
R 20
R R EF4
R R EF2
R REF5
V3
R R EF3
V2
R R EF1
V1
For Ch3 (Fig.17)
4
R 30 + R 31
R 31
Vout 3 =
×V 3 −
×VREF
R 30
R 30
Vout1
VREF
VREF
R10
The ratio of resistance can be calculated with:
R11
Vout2
R10 VREF − V 1
=
R11 Vout1 + V 1
(Use the absolute value of Vout voltage)
(The same Vout2 and Vout3 as Vout1)
6
Vout1
VREF
Vout2
R30
Vout 2 =
4
R10
An inverting circuit, the output voltage can be
calculated with:
Vout1 =
V2
Vout1
For Ch3 (Fig.16,Fig.18)
Vout 3 =
R REF1
R REF5
V3
R REF3
R20
R21
Vout3
R30
R31
Vout1
6
IN1+
7
IN1-
8
FB1
21
IN2+
20
IN2-
19
FB2
24
IN3+
23
IN3-
22
FB3
Er.AMP1
OUT1
12
Vout2
Er.AMP2
OUT2
13
SEL2
5
Vout3
Er.AMP3
OUT3
15
SEL3
3
VREF
Fig.18
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FA7711V
（12）An error pulse at start up
At start up, if rise time of VCC and PVCC pin is too
short, an error pulse, which is several tens µs of
width, may appear on the OUT pin.
The Internal circuit of IC is not stable before VREF
pin voltage rises to about 1V. Therefore, It may
cause an error pulses that a voltage is applied to
PVCC pin before VREG pin voltage raises enough at
start up.
The error pulse may appear when Vcc rise time
from 0V to 12V is less than about a few hundred µs.
In such a case, check the influence of the error
pulse such as blowout of a fuse.
On the other hand, if rise time of Vcc is not so short,
the error pulse will not appear.
（11）Protection from negative voltage apply
If rather large negative voltage is applied to any
pins of this IC, internal parasitic elements start
operating, and they may cause malfunctions.
Accordingly, the negative voltage, which is applied to
each Pin of the ICs, must be kept above -0.3V.
In the case of the OUT* pin, in particular, the
oscillation of voltage occurring after MOSFET’s
turning off can be applied to the OUT* pin through
MOSFET’s parasitic capacitance. As a result, there is
a possibility that the negative voltage is applied to the
OUT* pin. If this negative voltage reaches -0.3V or
below, connect an Schottky barrier diode between
OUT* pin and GND as shown in Fig. 21. The
Schottky barrier diode’s forward direction voltage
clamps the voltage applied to the OUT* pin. In this
case, use the Schottky barrier diode with low voltage
drop in forward direction. Other pins should be kept
above -0.3 V also based on the same reasons.
12V
In the case of an inverting circuit, the negative
voltage charged on the output capacitor will be
applied to VREF pin just after turning off the input
voltage.
If input voltage is turned on during applying a
negative voltage to VREF pin, the negative voltage
may lead malfunction.
This problem is likely to occur in the case of short
interruption.
In such a case, re-start the converter after the output
capacitor is discharged enough or connect a schottky
barrier diode with low forward voltage between VREF
pin and GND as shown in Fig.20.
about a few hundredμsec
VREF
about 1V
OUT(Nch drive)
Fig.21
（13）Design of phase compensation
A switching power supply supervises output voltage
with error amplifier, constitutes a closed loop, and is
stabilizing voltage by negative feedback.
Phase delay with a smoothing filter and Gain with
the main switching device, etc. is contained in the
negative feedback circuit, and those sum totals
become the phase and the gain in a closed loop.
The phase and the gain have the frequency
characteristic. In a negative feedback circuit, if the
gain remains 0dB or more at the frequency of 180
degrees delayed phase, a circuit will be oscillated.
In order to prevent oscillation, it is necessary to
adjust the phase and the gain of error amplifier.
(Fig.22) Since especially the switching power supply
has repeated ON and OFF at high speed, the minute
high frequency element is contained in the output,
and if you setup the frequency characteristic of the
error amplifier beyond necessity, it has a possibility of
unstable operate and oscillate.
The gain when the phase turns 180 degrees calls
gain margin, the phase when the gain becomes 0dB
calls phase margin. Above 10dB of gain margin and
above 50 degrees of phase margin are desirable
generally and set to this condition in phase
compensation. (Fig.22)
However, gain margin and phase margin against
transient response (sudden change of load, etc.) are
participate as trade-off, therefore when gain margin
and phase margin is larger, transient response
becomes margin-less condition, furthermore over
shoot and under shoot of converter voltage is larger.
VIN
VCC
18
17
PVCC
OUT
SBD
9
GND
10
PGND
Fig.19
Negative
voltge
4 VREF
SBD
IN+
IN9
Vcc
OUT
10
Fig.20
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FA7711V
To determine the value of circuit components, it
cannot decide here since conditions change a lot with
the value of an output filter or others, but generally
adjust the value between 1k Ω and 100k Ω of
resistor RFB and the value between 1nF and 100nF of
capacitor CFB. However the operation of switching
power supply changes by load condition, duty cycle,
temperature, etc., so when determine the value of
components, examine with the real load condition in
actual circuit.
Vout
IN+
INR FB C FB
FB
Gan
Fig.22
Gain m argin
0dB
180
10dB
Phase
°
Phase m argin
0°
50 dgree
Fig.23
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FA7711V
10. Application circuit
SC802-04
4.7 μ H
15V/800mA
Vin
8 ～14V
22 μ F
(O S-CO N)
220 μ F
2k Ω
13k Ω
5.1k Ω
36k Ω
150k Ω 100k Ω
-10V/50mA
0.1 μ F
0.1 μ F
SC802-04
100k Ω 150k Ω
10k Ω
0.01 μ F
24
IN3+
23
IN3-
22
FB3
21
IN2+
4.7 μ F
1μ F
22 μ H
4700pF
4.7k Ω
20
IN2-
47 μ H
19
FB2
18
VCC
17
PVCC
16
CS3
15
OUT3
14
CS2
3.3V/300mA
13
OUT2
FA7711V
CP
1
RT
2
SEL3
3
VREF
4
SEL2
5
IN1+
6
IN17
FB1
8
0.022 μ F
9.1k Ω
GND
9
PGND
10
CS1
11
33 μ F
OUT1
12
4700pF
33k Ω
SC802-04
1μ F
10k Ω
39k Ω
100k Ω
20k Ω
0.1 μ F
13kΩ
Obtained values are not guaranteed.
When determining values and external discrete components, examine under the actual circuit condition.
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