HWD2108 Audio Power Amplifier Dual 105 mW Headphone Amplifier General Description Key Specifications The HWD2108 is a dual audio power amplifier capable of delivering 105mW per channel of continuous average power into a 16Ω load with 0.1% (THD+N) from a 5V power supply. audio power amplifiers were designed specifically to provide high quality output power with a minimal amount of external components using surface mount packaging. Since the HWD2108 does not require bootstrap capacitors or snubber networks, it is optimally suited for low-power portable systems. The unity-gain stable HWD2108 can be configured by external gain-setting resistors. n THD+N at 1kHz at 105mW continuous average output power into 16Ω 0.1% (typ) n THD+N at 1kHz at 70mW continuous average output power into 32Ω 0.1% (typ) n Output power at 0.1% THD+N at 1kHz into 32Ω 70mW (typ) Features n n n n n LLP, MSOP, and SOP surface mount packaging Switch on/off click suppression Excellent power supply ripple rejection Unity-gain stable Minimum external components Applications n Headphone Amplifier n Personal Computers n Portable electronic devices Typical Application *Refer to the Application Information Section for information concerning proper selection of the input and output coupling capacitors. FIGURE 1. Typical Audio Amplifier Application Circuit 1 Connection Diagrams LLP Package Top View Order Number HWD2108LD SOP & MSOP Package Top View Order Number HWD2108M, HWD2108MM Typical Application 2 Absolute Maximum Ratings (Note 3) If Military/Aerospace specified devices are required, please contact the CSMSC Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage 6.0V 56˚C/W θJA (MSOP) 210˚C/W θJC (SOP) 35˚C/W θJA (SOP) 170˚C/W θJC (LLP) 15˚C/W −65˚C to +150˚C θJA (LLP) 117˚C/W (Note 9) −0.3V to VDD + 0.3V θJA (LLP) 150˚C/W (Note 10) Storage Temperature Input Voltage θJC (MSOP) Power Dissipation (Note 4) Internally limited ESD Susceptibility (Note 5) 3500V ESD Susceptibility (Note 6) 250V Junction Temperature Operating Ratings Temperature Range 150˚C TMIN ≤ TA ≤ TMAX Soldering Information (Note 1) −40˚C ≤ T Small Outline Package Vapor Phase (60 seconds) 215˚C Infrared (15 seconds) 220˚C A ≤ 85˚C 2.0V ≤ VDD ≤ 5.5V Supply Voltage Note 1: See AN-450 “Surface Mounting and their Effects on Product Reliability” for other methods of soldering surface mount devices. Thermal Resistance Electrical Characteristics (Notes 2, 3) The following specifications apply for VDD = 5V unless otherwise specified, limits apply to TA = 25˚C. Symbol Parameter Conditions HWD2108 Typ (Note Limit (Note 7) 8) VDD Supply Voltage Units (Limits) 2.0 V (min) 5.5 V (max) 1.2 3.0 mA (max) IDD Supply Current VIN = 0V, IO = 0A Ptot Total Power Dissipation VIN = 0V, IO = 0A 6 16.5 mW (max) VOS Input Offset Voltage VIN = 0V 10 50 mV (max) Ibias Input Bias Current VCM Common Mode Voltage GV Open-Loop Voltage Gain Io Max Output Current RO Output Resistance VO Output Swing PSRR Power Supply Rejection Ratio 10 pA 0 V 4.3 V RL = 5kΩ 67 dB THD+N < 0.1 % 70 mA 0.1 Ω RL = 32Ω, 0.1% THD+N, Min .3 RL = 32Ω, 0.1% THD+N, Max 4.7 Cb = 1.0µF, Vripple = 100mVPP, f = 100Hz 89 dB 75 dB RL = 16Ω, VO =3.5VPP (at 0 dB) 0.05 % 66 dB RL = 32Ω, VO =3.5VPP (at 0 dB) 0.05 % 66 dB Crosstalk Channel Separation RL = 32Ω THD+N Total Harmonic Distortion + Noise f = 1 kHz V SNR Signal-to-Noise Ratio VO = 3.5Vpp (at 0 dB) 105 dB fG Unity Gain Frequency Open Loop, RL = 5kΩ 5.5 MHz Po Output Power THD+N = 0.1%, f = 1 kHz RL = 16Ω 105 RL = 32Ω 70 mW 60 mW THD+N = 10%, f = 1 kHz CI RL = 16Ω 150 mW RL = 32Ω 90 mW 3 pF Input Capacitance 3 Electrical Characteristics (Notes 2, 3) (Continued) The following specifications apply for VDD = 5V unless otherwise specified, limits apply to TA = 25˚C. Symbol Parameter Conditions HWD2108 Typ (Note Limit (Note 7) 8) CL Load Capacitance SR Slew Rate 200 Unity Gain Inverting 3 Units (Limits) pF V/µs Electrical Characteristics (Notes 2, 3) The following specifications apply for VDD = 3.3V unless otherwise specified, limits apply to TA = 25˚C. Symbol Parameter Conditions Conditions Typ (Note Limit (Note 7) 8) IDD Supply Current VIN = 0V, IO = 0A VOS Input Offset Voltage VIN = 0V Po Output Power Units (Limits) 1.0 mA (max) 7 mV (max) RL = 16Ω 40 mW RL = 32Ω 28 mW RL = 16Ω 56 mW RL = 32Ω 38 mW THD+N = 0.1%, f = 1 kHz THD+N = 10%, f = 1 kHz Electrical Characteristics (Notes 2, 3) The following specifications apply for VDD = 2.6V unless otherwise specified, limits apply to TA = 25˚C. Symbol Parameter Conditions Conditions Typ (Note Limit (Note 7) 8) IDD Supply Current VIN = 0V, IO = 0A VOS Input Offset Voltage VIN = 0V Po Output Power THD+N = 0.1%, f = 1 kHz Units (Limits) 0.9 mA (max) 5 mV (max) RL = 16Ω 20 mW RL = 32Ω 16 mW RL = 16Ω 31 mW RL = 32Ω 22 mW THD+N = 10%, f = 1 kHz Note 2: All voltages are measured with respect to the ground pin, unless otherwise specified. Note 3: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit is given, however, the typical value is a good indication of device performance. Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature TA. The maximum allowable power dissipation is P DMAX = (TJMAX − TA) / θJA. For the HWD2108, TJMAX = 150˚C, and the typical junction-to-ambient thermal resistance, when board mounted, is 210˚C/W for package MUA08A and 170˚C/W for package M08A. Note 5: Human body model, 100 pF discharged through a 1.5 kΩ resistor. Note 6: Machine Model, 220 pF–240 pF discharged through all pins. Note 7: Typicals are measured at 25˚C and represent the parametric norm. Note 8: Tested limits are guaranteed to CSMSC’s AOQL (Average Outgoing Quality Level). Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Note 9: The given θJA is for an HWD2108 packaged in an LDA08B with the Exposed-DAP soldered to a printed circuit board copper pad with an area equivalent to that of the Exposed-DAP itself. Note 10: The given θJA is for an HWD2108 packaged in an LDA08B with the Exposed-DAP not soldered to any printed circuit board copper. 4 External Components Description (Figure 1) Components Functional Description 1. Ri The inverting input resistance, along with Rf, set the closed-loop gain. Ri, along with Ci, form a high pass filter with fc = 1/(2πRiCi). 2. Ci The input coupling capacitor blocks DC voltage at the amplifier’s input terminals. Ci, along with Ri, create a highpass filter with fC = 1/(2πRiCi). Refer to the section, Selecting Proper External Components, for an explanation of determining the value of Ci. 3. Rf The feedback resistance, along with Ri, set closed-loop gain. 4. CS This is the supply bypass capacitor. It provides power supply filtering. Refer to the Application Information section for proper placement and selection of the supply bypass capacitor. 5. CB This is the half-supply bypass pin capacitor. It provides half-supply filtering. Refer to the section, Selecting Proper External Components, for information concerning proper placement and selection of CB. 6. CO This is the output coupling capacitor. It blocks the DC voltage at the amplifier’s output and forms a high pass filter with RL at fO = 1/(2πRLCO) 7. RB This is the resistor which forms a voltage divider that provides 1/2 VDD to the non-inverting input of the amplifier. Typical Performance Characteristics THD+N vs Frequency THD+N vs Frequency THD+N vs Frequency THD+N vs Frequency 5 Typical Performance Characteristics (Continued) THD+N vs Frequency THD+N vs Frequency THD+N vs Frequency THD+N vs Frequency THD+N vs Frequency THD+N vs Frequency 6 Typical Performance Characteristics (Continued) THD+N vs Output Power THD+N vs Output Power THD+N vs Output Power THD+N vs Output Power THD+N vs Output Power THD+N vs Output Power 7 Typical Performance Characteristics (Continued) THD+N vs Output Power THD+N vs Output Power THD+N vs Output Power Output Power vs Load Resistance Output Power vs Load Resistance Output Power vs Load Resistance 8 Typical Performance Characteristics (Continued) Output Power vs Supply Voltage Output Power vs Power Supply Output Power vs Power Supply Clipping Voltage vs Supply Voltage Power Dissipation vs Output Power Power Dissipation vs Output Power 9 Typical Performance Characteristics (Continued) Power Dissipation vs Output Power Channel Separation Channel Separation Noise Floor Power Supply Rejection Ratio Open Loop Frequency Response 10 Typical Performance Characteristics (Continued) Open Loop Frequency Response Open Loop Frequency Response Supply Current vs Supply Voltage Frequency Response vs Output Capacitor Size Frequency Response vs Output Capacitor Size Frequency Response vs Output Capacitor Size 11 Typical Performance Characteristics (Continued) Typical Application Frequency Response Typical Application Frequency Response 12 POWER SUPPLY BYPASSING Application Information EXPOSED-DAP PACKAGE PCB MOUNTING CONSIDERATION The HWD2108’s exposed-dap (die attach paddle) package (LD) provides a low thermal resistance between the die and the PCB to which the part is mounted and soldered. This allows rapid heat transfer from the die to the surrounding PCB copper traces, ground plane, and surrounding air. The LD package should have its DAP soldered to a copper pad on the PCB. The DAP’s PCB copper pad may be connected to a large plane of continuous unbroken copper. This plane forms a thermal mass, heat sink, and radiation area. However, since the HWD2108 is designed for headphone applications, connecting a copper plane to the DAP’s PCB copper pad is not required. The HWD2108’s Power Dissipation vs Output Power Curve in the Typical Performance Characteristics shows that the maximum power dissipated is just 45mW per amplifier with a 5V power supply and a 32Ω load. Further detailed and specific information concerning PCB layout, fabrication, and mounting an LD (LLP) package is available from CSMSC Semiconductor’s Package Engineering Group under application note AN1187. POWER DISSIPATION Power dissipation is a major concern when using any power amplifier and must be thoroughly understood to ensure a successful design. Equation 1 states the maximum power dissipation point for a single-ended amplifier operating at a given supply voltage and driving a specified output load. PDMAX = (VDD) 2 / (2π2RL) (1) Since the HWD2108 has two operational amplifiers in one package, the maximum internal power dissipation point is twice that of the number which results from Equation 1. Even with the large internal power dissipation, the HWD2108 does not require heat sinking over a large range of ambient temperature. From Equation 1, assuming a 5V power supply and a 32Ω load, the maximum power dissipation point is 40mW per amplifier. Thus the maximum package dissipation point is 80mW. The maximum power dissipation point obtained must not be greater than the power dissipation that results from Equation 2: PDMAX = (TJMAX − TA) / θJA (2) For package MUA08A, θJA = 210˚C/W. TJMAX = 150˚C for the HWD2108. Depending on the ambient temperature,AT, of the system surroundings, Equation 2 can be used to find the maximum internal power dissipation supported by the IC packaging. If the result of Equation 1 is greater than that of Equation 2, then either the supply voltage must be decreased, the load impedance increased or TA reduced. For the typical application of a 5V power supply, with a 32Ω load, the maximum ambient temperature possible without violating the maximum junction temperature is approximately 133.2˚C provided that device operation is around the maximum power dissipation point. Power dissipation is a function of output power and thus, if typical operation is not around the maximum power dissipation point, the ambient temperature may be increased accordingly. Refer to the Typical Performance Characteristics curves for power dissipation information for lower output powers. As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply rejection. Applications that employ a 5V regulator typically use a 10µF in parallel with a 0.1µF filter capacitors to stabilize the regulator’s output, reduce noise on the supply line, and improve the supply’s transient response. However, their presence does not eliminate the need for a local 0.1µF supply bypass capacitor, CS, connected between the HWD2108’s supply pins and ground. Keep the length of leads and traces that connect capacitors between the HWD2108’s power supply pin and ground as short as possible. Connecting a 1.0µF capacitor, CB, between the IN A(+) / IN B(+) node and ground improves the internal bias voltage’s stability and improves the amplifier’s PSRR. The PSRR improvements increase as the bypass pin capacitor value increases. Too large, however, increases the amplifier’s turn-on time. The selection of bypass capacitor values, especially CB, depends on desired PSRR requirements, click and pop performance (as explained in the section, Selecting Proper External Components), system cost, and size constraints. SELECTING PROPER EXTERNAL COMPONENTS Optimizing the HWD2108’s performance requires properly selecting external components. Though the HWD2108 operates well when using external components with wide tolerances, best performance is achieved by optimizing component values. The HWD2108 is unity-gain stable, giving a designer maximum design flexibility. The gain should be set to no more than a given application requires. This allows the amplifier to achieve minimum THD+N and maximum signal-to-noise ratio. These parameters are compromised as the closed-loop gain increases. However, low gain demands input signals with greater voltage swings to achieve maximum output power. Fortunately, many signal sources such as audio CODECs have outputs of 1VRMS (2.83VP-P). Please refer to the Audio Power Amplifier Design section for more information on selecting the proper gain. Input and Output Capacitor Value Selection Amplifying the lowest audio frequencies requires high value input and output coupling capacitors (CI and CO in Figure 1). A high value capacitor can be expensive and may compromise space efficiency in portable designs. In many cases, however, the speakers used in portable systems, whether internal or external, have little ability to reproduce signals below 150Hz. Applications using speakers with this limited frequency response reap little improvement by using high value input and output capacitors. Besides affecting system cost and size, Ci has an effect on the HWD2108’s click and pop performance. The magnitude of the pop is directly proportional to the input capacitor’s size. Thus, pops can be minimized by selecting an input capacitor value that is no higher than necessary to meet the desired −3dB frequency. As shown in Figure 1, the input resistor, RI and the input capacitor, CI, produce a −3dB high pass filter cutoff frequency that is found using Equation (3). In addition, the output load RL, and the output capacitor CO, produce a -3db high pass filter cutoff frequency defined by Equation (4). 13 fI-3db =1/2πRICI (3) fO-3db =1/2πRLCO (4) Application Information package. Once the power dissipation equations have been addressed, the required gain can be determined from Equation (7). (Continued) Also, careful consideration must be taken in selecting a certain type of capacitor to be used in the system. Different types of capacitors (tantalum, electrolytic, ceramic) have unique performance characteristics and may affect overall system performance. Bypass Capacitor Value Besides minimizing the input capacitor size, careful consideration should be paid to the value of the bypass capacitor, CB. Since CB determines how fast the HWD2108 settles to quiescent operation, its value is critical when minimizing turn-on pops. The slower the HWD2108’s outputs ramp to their quiescent DC voltage (nominally 1/2 VDD), the smaller the turn-on pop. Choosing CB equal to 1.0µF or larger, will minimize turn-on pops. As discussed above, choosing Ci no larger than necessary for the desired bandwith helps minimize clicks and pops. (7) Thus, a minimum gain of 1.497 allows the HWD2108 to reach full output swing and maintain low noise and THD+N perfromance. For this example, let AV =1.5. The amplifiers overall gain is set using the input (Ri ) and feedback (Rf ) resistors. With the desired input impedance set at 20kΩ, the feedback resistor is found using Equation (8). AV = Rf/Ri (8) The value of Rf is 30kΩ. AUDIO POWER AMPLIFIER DESIGN Design a Dual 70mW/32Ω Audio Amplifier Given: Power Output 70mW Load Impedance Input Level 32Ω 1Vrms (max) Input Impedance Bandwidth 20kΩ The last step in this design is setting the amplifier’s −3db frequency bandwidth. To achieve the desired ± 0.25dB pass band magnitude variation limit, the low frequency response must extend to at lease one−fifth the lower bandwidth limit and the high frequency response must extend to at least five times the upper bandwidth limit. The gain variation for both response limits is 0.17dB, well within the ± 0.25dB desired limit. The results are an 100Hz–20kHz ± 0.50dB The design begins by specifying the minimum supply voltage necessary to obtain the specified output power. One way to find the minimum supply voltage is to use the Output Power vs Supply Voltage curve in the Typical Performance Characteristics section. Another way, using Equation (5), is to calculate the peak output voltage necessary to achieve the desired output power for a given load impedance. To account for the amplifier’s dropout voltage, two additional voltages, based on the Dropout Voltage vs Supply Voltage in the Typical Performance Characteristics curves, must be added to the result obtained by Equation (5). For a single-ended application, the result is Equation (6). VDD ≥ (2VOPEAK + (VODTOP + VODBOT)) fL = 100Hz/5 = 20Hz (9) fH = 20kHz*5 = 100kHz (10) and a (5) As stated in the External Components section, both Ri in conjunction with Ci, and Co with RL, create first order highpass filters. Thus to obtain the desired low frequency response of 100Hz within ± 0.5dB, both poles must be taken into consideration. The combination of two single order filters at the same frequency forms a second order response. This results in a signal which is down 0.34dB at five times away from the single order filter −3dB point. Thus, a frequency of 20Hz is used in the following equations to ensure that the response is better than 0.5dB down at 100Hz. (6) Ci ≥ 1 / (2π * 20 kΩ * 20 Hz) = 0.397µF; use 0.39µF. The Output Power vs Supply Voltage graph for a 32Ω load indicates a minimum supply voltage of 4.8V. This is easily met by the commonly used 5V supply voltage. The additional voltage creates the benefit of headroom, allowing the HWD2108 to produce peak output power in excess of 70mW without clipping or other audible distortion. The choice of supply voltage must also not create a situation that violates maximum power dissipation as explained above in the Power Dissipation section. Remember that the maximum power dissipation point from Equation (1) must be multiplied by two since there are two independent amplifiers inside the Co ≥ 1 / (2π * 32Ω * 20 Hz) = 249µF; use 330µF. The high frequency pole is determined by the product of the desired high frequency pole, fH, and the closed-loop gain, AV. With a closed-loop gain of 1.5 and fH = 100kHz, the resulting GBWP = 150kHz which is much smaller than the HWD2108’s GBWP of 900kHz. This figure displays that if a designer has a need to design an amplifier with a higher gain, the HWD2108 can still be used without running into bandwidth limitations. 14 Demonstration Board Layout Recommended LD PC Board Layout: Top Silkscreen Recommended SO PC Board Layout: Top Silkscreen Recommended Recommended SOP PC Board Layout: Top Layer Recommended SOP PC Board Layout: Bottom Layer LD PC Board Layout: Top Layer Recommended LD PC Board Layout: Bottom Layer 15 Physical Dimensions inches (millimeters) unless otherwise noted Order Number HWD2108LD Order Number HWD2108M 16 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Order Number HWD2108MM 17 Chengdu Sino Microelectronics System Co.,Ltd (Http://www.csmsc.com) Headquarters of CSMSC: Beijing Office: Address: 2nd floor, Building D, Science & Technology Industrial Park, 11 Gaopeng Avenue, Chengdu High-Tech Zone,Chengdu City, Sichuan Province, P.R.China PC: 610041 Tel: +86-28-8517-7737 Fax: +86-28-8517-5097 Address: Room 505, No. 6 Building, Zijin Garden, 68 Wanquanhe Rd., Haidian District, Beijing, P.R.China PC: 100000 Tel: +86-10-8265-8662 Fax: +86-10-8265-86 Shenzhen Office: Address: Room 1015, Building B, Zhongshen Garden, Caitian Rd, Futian District, Shenzhen, P.R.China PC: 518000 Tel : +86-775-8299-5149 +86-775-8299-5147 +86-775-8299-6144 Fax: +86-775-8299-6142