HY5118164C,HY5116164C 1Mx16, Extended Data Out mode DESCRIPTION This family is a 16M bit dynamic RAM organized 1,048,576 x 16-bit configuration with Extended Data Out mode CMOS DRAMs. Extended data out mode is a kind of page mode which is useful for the read operation. The circuit and process design allow this device to achieve high performance and low power dissipation. Optional features are access time(60, 70 or 80ns) and refresh cycle(1K ref. or 4K ref.) and power consumption (Normal or Low power with self refresh). Hyundai’s advanced circuit design and process technology allow this device to achieve high bandwidth, low power consumption and high reliability. FEATURES Ÿ Extended data out operation Ÿ Read-modify-write Capability Ÿ TTL compatible inputs and outputs Ÿ /CAS-before-/RAS, /RAS-only, Hidden and Self refresh capability Ÿ JEDEC standard pinout Ÿ 42-pin Plastic SOJ (400mil) 44/50-pin plastic TSOP-II (400mil) Ÿ Single power supply of 5V ± 10% Ÿ Early write or output enable controlled write Ÿ Max. Active power dissipation Ÿ Fast access time and cycle time Speed 1K refresh 4K refresh Speed tRAC tCAC tHPC 60 880mW 550mW 60 60ns 15ns 25ns 70 825mW 495mW 70 70ns 20ns 30ns 80 770mW 440mW 80 80ns 20ns 35ns Ÿ Refresh cycle Part number Refresh Normal HY5118164C 1K 16ms HY5116164C 4K 64ms SL-part 256ms ORDERING INFORMATION Part Name Refresh HY5118164CJC 1K HY5118164CSLJC 1K HY5118164CTC 1K HY5118164CSLTC 1K HY5116164CJC 4K HY5116164CSLJC 4K HY5116164CTC 4K HY5116164CSLTC 4K Power Package 42Pin SOJ SL-part 42Pin SOJ 44/50Pin TSOP-II SL-part 44/50Pin TSOP-II 42Pin SOJ SL-part 42Pin SOJ 44/50Pin TSOP-II SL-part 44/50Pin TSOP-II *SL : Low power with self refresh This document is a general product description and is subject to change without notice. Hyundai electronics does not assume any responsibility for use of circuits described. No patent licences are implied Hyundai Semiconductor Rev.00 / Sep.97 1 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HY5118164C,HY5116164C FUNCTIONAL BLOCK DIAGRAM DQ0 ~ DQ15 8 8 8 Data Input Buffer 8 Data Output Buffer OE DQ0~7 DQ8~15 DQ0~7 DQ8~15 8 8 8 8 WE LCAS UCAS A0 A1 A2 ~ A9 *(A10) *(A11) RAS Address Buffer CAS Clock Generator CAS Clock Generator (10/8)* Cloumn Predecoder (10/8)* Sense Amp I/O Gate Refresh Controller Refresh Counter (10/12)* (10/12)* RAS Clock Generator Memory Array 4,194,304x16 Substrate Bias Generator *(A10) and *(A11) for 4K refresh part (1K Refresh / 4K Refresh)* 1Mx16,EDO DRAM Rev.00 / Sep.97 2 This Material Copyrighted By Its Respective Manufacturer Row Decoder VCC VSS HY5116164C,HY5116164C PIN CONFIGURATION (Marking Side) 44/50Pin Plastic TSOP- II (400mil) 42Pin Plastic SOJ (400mil) *(N.C) : For 1K Refresh product PIN DESCRIPTION Pin Name Parameter /RAS Row Address Strobe /CAS Column Address Strobe /WE Write Enable /OE Output Enable A0~A11 Address Input (4K Refresh Product) A0~A9 Address Input (1K Refresh Product) DQ0~DQ15 Data In/Out Vcc Power (5V) Vss Ground NC No Connection 1Mx16,EDO DRAM Rev.00 / Sep.97 3 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HY5118164C,HY5116164C ABSOLUTE MAXIMUM RATING Symbol Parameter Rating Unit TA Ambient Temperature 0 to 70 °C TSTG Storage Temperature -55 to 150 °C VIN, VOUT Voltage on Any Pin relative to VSS -1.0 to 7.0 V VCC Voltage on VCC relative to VSS -1.0 to 7.0 V IOS Short Circuit Output Current 50 mA PD Power Dissipation 1 W TSOLDER Soldering Temperature Ÿ Time 260 Ÿ 10 °C Ÿ sec Note : Operation at or above Absolute Maximum Ratings can adversely affect device reliability RECOMMENDED DC OPERATING CONDITIONS (TA = 0°C to 70°C ) Symbol Parameter Min Typ Max UNIT VCC Power Supply Voltage 4.5 5.0 5.5 V VIH Input High Voltage 2.4 - VCC+1.0 V VIL Input Low Voltage -1.0 - 0.8 V Note : All voltages are referenced to VSS. DC OPERATING CHARACTERISTIC Symbol Parameter Test condition Min Max Unit ILI Input Leakage Current (Any input) VSS ≤ VIN ≤ VCC + 1.0 All other pins not under test = VSS -10 10 µA ILO Output Leakage Current (Any input) VSS ≤ VOUT ≤ VCC /RAS & /CAS at VIH -10 10 µA VOL Output Low Voltage IOL = 4.2mA - 0.4 V VOH Output High Voltage IOH = -5.0mA 2.4 - V 1Mx16,EDO DRAM Rev.00 / Sep.97 4 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HY5118164C,HY5116164C DC CHARACTERISTICS (TA = 0°C to 70°C , VCC = 5V ± 10%, VSS = 0V, unless otherwise noted.) Symbol Parameter Test condition Speed Max. Current Unit 1K Ref 4K Ref 60 70 80 160 150 140 100 90 80 mA SL-part 2 1 2 1 mA ICC1 Operating Current /RAS, /CAS Cycling tRC = tRC(min.) ICC2 TTL Standby Current /RAS, /CAS ≥ VIH Other inputs ≥ VSS ICC3 /RAS-only Refresh Current /RAS Cycling,/CAS = VIH tRC = tRC(min.) 60 70 80 160 150 140 100 90 80 mA ICC4 EDO mode Current /CAS Cycling, /RAS = VIL tHPC = tHPC(min.) 60 70 80 140 120 100 120 100 80 mA ICC5 CMOS Standby Current /RAS = /CAS ≥ VCC - 0.2V SL-part 1 200 1 200 mA µA ICC6 /CAS-before-/RAS Refresh Current /RAS & /CAS = 0.2V tRC = tRC(min.) 60 70 80 160 150 140 100 90 80 mA ICC7 Battery Back-up Current (SL-part) tRC=250µs (1K Ref), 62.5µs (4K Ref) /CAS = 0.2V /OE & /WE = VCC - 0.2V Address = Vcc-0.2V or 0.2V DQ0~DQ15 = Vcc-0.2, 0.2V or Open tRAS ≤ 300ns 350 350 ICC8 Self Refresh Current (SL-part) tRAS ≤ 1µs /RAS & /CAS = 0.2V Other pins are same as ICC7 µA 450 450 350 350 µA Note 1. ICC1, ICC3, ICC4 and ICC6 depend on output loading and cycle rates(tRC and tHPC). 2. Specified values are obtained with output unloaded. 3. ICC is specified as an average current. In ICC1, ICC3, ICC6, address can be changed only once while /RAS=VIL. In ICC4, address can be changed maximum once while /CAS=VIH within one EDO mode cycle time tHPC. 1Mx16,EDO DRAM Rev.00 / Sep.97 5 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HY5118164C,HY5116164C AC CHARACTERISTICS (TA = 0 °C to 70 °C, VCC = 5V ± 10% , VSS = 0V, unless otherwise noted.) 60ns Symbol 70ns 80ns Unit Parameter Min Max Min Max Min Max Note tRC Random read or write cycle time 105 - 125 - 145 - ns tRWC Read-modify-write cycle time 142 - 167 - 187 - ns tHPC EDO mode cycle time 25 - 30 - 35 - ns 2 tHPRWC EDO mode read-modify-write cycle time 73 - 85 - 100 - ns 2 tRAC Access time from /RAS - 60 - 70 - 80 ns 5,6,7 tCAC Access time from /CAS - 15 - 20 - 20 ns 5,6 tAA Access time from column address - 30 - 35 - 40 ns 5 tCPA Access time from /CAS precharge - 35 - 35 - 40 ns 5 tCLZ /CAS to output low impedance 0 - 0 - 0 - ns 5 tCEZ Output buffer turn-off delay from /CAS 3 15 3 15 3 15 ns 8,12 tT Transition time(rise and fall) 3 50 3 50 3 50 ns 3 tRP /RAS precharge time 40 - 50 - 60 - ns tRAS /RAS pulse width 60 10K 70 10K 80 10K ns tRASP /RAS pulse width(EDO mode) 60 100K 70 100K 80 100K ns tRSH /RAS hold time 13 - 15 - 20 - ns tCSH /CAS hold time 40 - 50 - 60 - ns tCAS /CAS pulse width 13 10K 15 10K 20 10K ns tRCD /RAS to /CAS delay time 20 45 20 50 20 60 ns 6 tRAD /RAS to column address delay time 15 30 15 35 15 40 ns 7 tCRP /CAS to /RAS precharge time 5 - 5 - 5 - ns 11 tCP /CAS precharge time 7 - 10 - 10 - ns 16 tASR Row address set-up time 0 - 0 - 0 - ns tRAH Row address hold time 10 - 10 - 10 - ns tASC Column address set-up time 0 - 0 - 0 - ns tCAH Column address hold time 10 - 15 - 15 - ns tRAL Column address to /RAS lead time 30 - 35 - 40 - ns tRCS Read command set-up time 0 - 0 - 0 - ns tRCH Read command hold time referenced to /CAS 0 - 0 - 0 - ns 9 tRRH Read command hold time referenced to /RAS 0 - 0 - 0 - ns 9 tWCH Write command hold time 10 - 15 - 15 - ns tWP Write command pulse width 10 - 10 - 10 - ns tRWL Write command to /RAS lead time 15 - 15 - 15 - ns tCWL Write command to /CAS lead time 13 - 15 - 20 - ns 1Mx16,EDO DRAM Rev.00 / Sep.97 6 Powered by ICminer.com Electronic-Library Service CopyRight 2003 16 HY5118164C,HY5116164C AC CHARACTERISTICS Continued 60ns Symbol 70ns 80ns Parameter Min Max Min Max Min Max Unit Note tDS Data-in set-up time 0 - 0 - 0 - ns 10 tDH Data-in hold time 10 - 15 - 15 - ns 10 Refresh period(1024 cycles) - 16 - 16 - 16 ms Refresh period(4096 cycles) - 64 - 64 - 64 ms Refresh period(SL-part) - 256 - 256 - 256 ms tWCS Write command set-up time 0 - 0 - 0 - ns 11 tCWD /CAS to /WE delay time 37 - 45 - 45 - ns 11,15 tRWD /RAS to /WE delay time 80 - 95 - 105 - ns 11 tAWD Column address to /WE delay time 50 - 60 - 65 - ns 11 tCSR /CAS set-up time(CBR cycle) 5 - 5 - 5 - ns 17 tCHR /CAS hold time(CBR cycle) 10 - 10 - 10 - ns 18 tRPC /RAS to /CAS precharge time 5 - 5 - 5 - ns tCPT /CAS precharge time(CBR counter test) 30 - 35 - 40 - ns tROH /RAS hold time referenced to /OE 10 - 10 - 10 - ns tOEA /OE access time - 15 - 20 - 20 ns tOED /OE to data delay time 15 - 20 - 20 - ns tOEZ Output buffer turn-off delay time from /OE 3 15 3 15 3 15 ns tOEH /OE command hold time 15 - 20 - 20 - ns tCPWD /WE delay time from /CAS precharge 55 - 65 - 75 - ns tRHCP /RAS hold time from /CAS precharge 40 - 40 - 50 - ns tWRP /WE to /RAS precharge time(CBR cycle) 10 - 10 - 10 - ns tWRH /WE to /RAS hold time(CBR cycle) 10 - 10 - 10 - ns tRASS /RAS pulse width(self refresh) 100K - 100K - 100K - ns tRPS /RAS Precharge Time (Self refresh) 110 - 130 - 150 - ns tCHS /CAS Hold Time (Self refresh) -50 - -50 - -50 - ns tDOH Output Data Hold Time 5 - 5 - 5 - ns tREZ Output Buffer Turn Off Delay Time from /RAS 3 15 3 15 3 15 ns tWEZ Output Buffer Turn Off Delay Time from /WE 3 15 3 15 3 15 ns tWED /WE to Data Delay Time 15 - 15 - 15 - ns tOEP /OE Precharge Time 5 - 5 - 5 - ns tWPE /WE Pulse Width (EDO cycle) 5 - 5 - 5 - ns tOCH /OE to /CAS Hold Time 5 - 5 - 5 - ns tCHO /CAS Hold Time to /OE 5 - 5 - 5 - ns tREF 1Mx16,EDO DRAM Rev.00 / Sep.97 7 Powered by ICminer.com Electronic-Library Service CopyRight 2003 14 8 11 HY5118164C,HY5116164C NOTE 1. An initial pause of 200µs is required after power-up followed by 8 /RAS only refresh cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CBR refresh cycles instead of 8 /RAS-only refresh cycles are required. 2 tASC ≥ tCP(min), assume tT=3ns. 3. VIH(min.) and VIL(max.) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min.) and VIL(max.) 4. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (TA=0 to 70¡ ÆC) is assured. 5. Measured at VOH=2.0V and VOL=0.8V with a load equivalent to 2TTL loads and 100pF. 6. Operation within the tRCD(max.) limit ensures that tRAC(max.) can be met. tRCD(max.) is specified as a reference point only. If tRCD is greater than the specified tRCD(max.) limit, then access time is controlled by tCAC. 7. Operation within the tRAD(max.) limit ensures that tRAC(max.) can be met. tRAD(max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(max.) limit, then access time is controlled by tAA. 8. tWEZ, tREZ, tCEZ and tOEZ define the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 9. Either tRCH or tRRH must be satisfied for a read cycle. 10.These parameters are referenced to /LCAS or /UCAS leading edge in early write cycles and to /WE leading edge in read-modify-write cycles and late write cycle. 11.tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS(min.), the cycle is an early write cycle and data out pin will remain open circuit (high impedance) through the entire cycle. If tRWD ≥ tRWD(min.), tCWD ≥ tCWD(min.), tAWD ≥ tAWD(min), and tCPWD ≥ tCPWD(min.), the cycle is a read-modify-write cycle and data out will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 12.If /RAS goes to high before /CAS high going,the open circuit condition of the output is achieved by /CAS high going. If /CAS goes to high before /RAS high going,the open circuit condition of the output is achieved by /RAS high going. 13.tASC,tCAH are referenced to the earlier /CAS falling edge. 14.tCP and tCPT are measured when both /LCAS and /UCAS are high state. 15.tCWD is referenced to the later /CAS falling edge at word read-modifiy-write cycle. 16.tCWL must be satisfied by both /LCAS and /UCAS for 16-bit access cycles. 17.tCSR is referenced to the earlier /CAS falling before /RAS transition low. 18.tCHR is referenced to the later /CAS rising high after /RAS transition low. 19.tDS, tDH is independently specified for lower byte DQ(0-7), upper byte DQ(8-15). CAPACITANCE (TA = 25°C, VCC = 5V ± 10%, VSS = 0V and f=1MHz, unless otherwise noted.) Symbol Parameter Typ. Max Unit CIN1 Input Capacitance (A0~A11) - 5 pF CIN2 Input Capacitance (/RAS, /LCAS,/UCAS, /WE, /OE) - 7 pF CDQ Data Input / Output Capacitance (DQ0~DQ15) - 7 pF 1Mx16,EDO DRAM Rev.00 / Sep.97 8 Powered by ICminer.com Electronic-Library Service CopyRight 2003