HY57V168010D 2 Banks x 1M X 8 Bit Synchronous DRAM DESCRIPTION The Hyundai HY57V168010D is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V168010D is organized as 2banks of 1,048,576x8. HY57V168010D is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipeline design is not restricted by a `2N` rule.) FEATURES • Single 3.3V ± 0.3V power supply • Auto refresh and self refresh • All device pins are compatible with LVTTL interface • 4096 refresh cycles / 64ms • JEDEC standard 400mil 44pin TSOP-II with 0.8mm of pin pitch • Programmable Burst Length and Burst Type • All inputs and outputs referenced to positive edge of system clock • Data mask function by DQM • Internal two banks operation - 1, 2, 4, 8 and Full Page for Sequence Burst - 1, 2, 4 and 8 for Interleave Burst • Programmable CAS Latency ; 1, 2, 3 Clocks ORDERING INFORMATION Part No. Clock Frequency HY57V168010DTC-8 125MHz HY57V168010DTC-10P 100MHz HY57V168010DTC-10S 100MHz HY57V168010DTC-10 100MHz Organization Interface Package 2Banks x 1Mbits x 8 LVTTL 400mil 44pin TSOP II This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied Rev. 1.5/Dec.98 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HY57V168010D PIN CONFIGURATION VDD DQ0 VSSQ DQ1 VDDQ DQ2 VSSQ DQ3 VDDQ NC NC WE CAS RAS CS BA A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44pin TSOP II 400mil x 725mil 0.8mm pin pitch 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 VSS DQ7 VSSQ DQ6 VDDQ DQ5 VSSQ DQ4 VDDQ NC NC DQM CLK CKE NC A9 A8 A7 A6 A5 A4 VSS PIN DESCRIPTION PIN PIN NAME DESCRIPTION CLK Clock The system clock input. All other inputs are referenced to the SDRAM on the rising edge of CLK. CKE Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh. CS Chip Select Command input enable or mask except CLK, CKE and DQM BA Bank Address Select either one of banks during both RAS and CAS activity. A0 ~ A10 Address Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA8 Auto-precharge flag : A10 RAS, CAS, WE Row Address Strobe, Column Address Strobe, Write Enable RAS, CAS and WE define the operation. Refer function truth table for details DQM Data Input/Output Mask DQM control output buffer in read mode and mask input data in write mode DQ0 ~ DQ7 Data Input/Output Multiplexed data input / output pin VDD/VSS Power Supply/Ground Power supply for internal circuit and input buffer VDDQ/VSSQ Data Output Power/Ground Power supply for DQ NC No Connection No connection Rev. 1.5/Dec.98 Powered by ICminer.com Electronic-Library Service CopyRight 2003 2 HY57V168010D FUNCTIONAL BLOCK DIAGRAM 2Mx8 Synchronous DRAM Self Refresh Counter Refresh Interval Timer Refresh Counter 1Mx8 Bank 0 Address[0:10] Sense AMP & I/O gates Column Decoder CLK CKE Precharge Row Active Address Register DQ0 BA(A11) CS DQ1 RAS CAS Column Addr. Latch & Counter Column Active Burst Length Counter DQ2 DQ3 Overflow DQ4 DQ5 WE DQ6 DQ7 DQM Column Decoder Sense AMP & I/O gates 1Mx8 Bank 1 Mode Register Rev. 1.5/Dec.98 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Test Mode I/O Control 3 HY57V168010D ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Ambient Temperature TA 0 ~ 70 °C Storage Temperature TSTG -55 ~ 125 °C Voltage on Any Pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD relative to VSS VDD -1.0 ~ 4.6 V Short Circuit Output Current IOS 50 mA Power Dissipation PD 1 W Soldering Temperature·Time TSOLDER 260·10 °C ·Sec Note : Operation at above absolute maximun rating can adversely affect device reliability. DC OPERATING CONDITION (TA=0°C to 70°C) Parameter Symbol Min Typ. Max Unit Note Power Supply Voltage VDD, VDDQ 3.0 3.3 3.6 V 1 Input high voltage VIH 2.0 3.0 VDD + 0.3 V 1, 2 Input low voltage VIL -0.5 0 0.8 V 1, 3 Note Note : 1.All voltages are referenced to V SS = 0V. 2.VIH(max) is acceptable 4.6V AC pulse width with ≤ 10ns of duration. 3.VIL(min) is acceptable -1.5V AC pulse width with ≤ 10ns of duration. AC OPERATING CONDITION (TA=0°C to 70°C, VDD=3.3V ± 0.3V, VSS=0V) Parameter Symbol Value Unit AC input high / low level voltage VIH / VIL 2.4/0.4 V Vtrip 1.4 V Input rise / fall time tR / tF 1 ns Output timing measurement reference level Voutref 1.4 V CL 50 pF Input timing measurement reference level voltage Output load capacitance for access time measurement 1 Note : 1. Output load to measure access times (tAC, tOH, etc) varies to clock frequency. A load is equivalent to one TTL gate and one capacitance. Rev. 1.5/Dec.98 Powered by ICminer.com Electronic-Library Service CopyRight 2003 4 HY57V168010D CAPACITANCE (TA=25°C, f=1MHz) Parameter Pin Symbol Min Max Unit CLK CI1 2.5 4 pF Input capacitance A0 ~ A10, BA CKE, CS, RAS, CAS, WE,DQM CI2 2.5 5 pF Data input / output capacitance DQ0 ~ DQ7 CI/O 4 6.5 pF OUTPUT LOAD CIRCUIT Vtt=1.4V RT=250 Ω Output Output 50pF 50pF DC Output Load Circuit AC Output Load Circuit DC CHARACTERISTICS I (TA=0°C to 70°C, VDD=3.3V ± 0.3V) Parameter Symbol Min. Max Unit Note Input leakage current IL -1 1 uA 1 Output leakage current IO -1 1 uA 2 Output high voltage VOH 2.4 - V IOH = -4mA Output low voltage VOL - 0.4 V IOL =+4mA Note : 1.VIN = 0 to 3.6V, All other pins are not under test = 0V 2.DOUT is disabled, V OUT=0 to 3.6V Rev. 1.5/Dec.98 Powered by ICminer.com Electronic-Library Service CopyRight 2003 5 HY57V168010D DC CHARACTERISTICS II (TA=0°C to 70°C, VDD=3.3V ± 0.3V, VSS=0V) Speed Parameter Symbol Test Condition -8 -10P -10S -10 110 110 110 90 IDD1 Burst Length=1, One bank active tRAS ≥ tRAS(min),tRP ≥ tRP(min), IO=0mA IDD2P CKE ≤ VIL(max), tCK = min. 1 IDD2PS CKE ≤ VIL(max), tCK = ∞ 1 IDD2N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = min Input signals are changed one time during 2Clks. All other pins ≥ VDD-0.2V or ≤ 0.2V 20 IDD2NS CKE ≥ VIH(min), tCK = ∞ Input signals are stable. 15 IDD3P CKE ≤ VIL(max), tCK = min 30 IDD3PS CKE ≤ VIL(max), tCK = ∞ 30 IDD3N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = min Input signals are changed one time during 2CLKs. All other pins ≥ VDD-0.2V or ≤ 0.2V 50 IDD3NS CKE ≥ VIH(min), tCK = ∞ Input signals are stable 30 Burst Mode Operating Current IDD4 tCK ≥ tCK(min), tRAS ≥ tRAS(min), IO=0mA All banks active Auto Refresh Current IDD5 tRRC ≥ tRRC(min), All banks active Self Refresh Current IDD6 CKE ≤ 0.2V Operating Current Precharge Standby Current in power down mode Precharge Standby Current in non power down mode Active Standby Current in power down mode Active Standby Current in non power down mode Unit Note mA 1 mA mA mA mA CL=3 110 90 90 75 CL=2 90 75 75 65 110 110 110 90 mA 2 1 mA mA Note : 1.IDD1 and I DD4 depend on output loading and cycle rates. Specified values are measured with the output open. Rev. 1.5/Dec.98 Powered by ICminer.com Electronic-Library Service CopyRight 2003 6 HY57V168010D AC CHARACTERISTICS I (TA=0°C to 70°C, VDD=3.3V ± 0.3V, VSS=0V) -8 Paramter -10P -10S -10 Symbol Unit Min Max Min Max Min Max Min Max Note CAS Latency = 3 tCK3 8 - 10 - 10 - 10 - CAS Latency = 2 tCK2 10 - 10 - 12 - 10 - Clock high pulse width tCHW 3 - 3 - 3 - 3 - ns 1 Clock low pulse width tCLW 3 - 3 - 3 - 3 - ns 1 CAS Latency = 3 tAC3 - 6 - 6 - 6 - 8 CAS Latency = 2 tAC2 - 6 - 6 - 6 - 8 Data-out hold time tOH 3 - 3 - 3 - 3 - ns Data-Input setup time tDS 2 - 2 - 2 - 3 - ns 1 Data-Input hold time tDH 1 - 1 - 1 - 1 - ns 1 Address setup time tAS 2 - 2 - 2 - 3 - ns 1 Address hold time tAH 1 - 1 - 1 - 1 - ns 1 CKE setup time tCKS 2 - 2 - 2 - 3 - ns 1 CKE hold time tCKH 1 - 1 - 1 - 1 - ns 1 Command setup time tCS 2 - 2 - 2 - 3 - ns 1 Command hold time tCH 1 - 1 - 1 - 1 - ns 1 CLK to data output in low Z-time tOLZ 2 - 2 - 2 - 2 - ns CAS Latency = 3 tOHZ3 2 9 3 9 3 9 3 10 ns CAS Latency = 2 tOHZ2 2 9 3 9 3 9 3 10 ns System clock cycle time Access time from clock CLK to data output in high Z-time ns ns Note : 1.Assume tR / tF (input rise and fall time ) is 1ns. 2.Access times to be measured with input signals of 1V/ns edge rate, 0.8V to 2.0V Rev. 1.5/Dec.98 Powered by ICminer.com Electronic-Library Service CopyRight 2003 7 HY57V168010D AC CHARACTERISTICS II (TA=0°C to 70°C, VDD=3.3V ± 0.3V, VSS=0V) -8 Parameter -10P -10S -10 Symbol Unit Min Max Min Max Min Max Min Max Operation tRC 70 - 70 - 70 - 80 - ns Auto Refresh tRRC 70 - 70 - 70 - 80 - ns RAS to CAS delay tRCD 20 - 20 - 20 - 20 - ns RAS active time tRAS 50 100K 50 100K 50 100K 50 100K ns RAS precharge time tRP 20 - 20 - 20 - 30 - ns RAS to RAS bank active delay tRRD 20 - 20 - 20 - 20 - ns CAS to CAS bank active delay tCCD 1 - 1 - 1 - 1 - CLK Write command to data-in delay tWTL 0 - 0 - 0 - 0 - CLK Data-in to precharge command tDPL 1 - 1 - 1 - 1 - CLK Data-in to active command tDAL 4 - 3 - 3 - 3 - CLK DQM to data-in Hi-Z tDQZ 2 - 2 - 2 - 2 - CLK DQM to data mask tDQM 0 - 0 - 0 - 0 - CLK MRS to new command tMRD 2 - 2 - 2 - 2 - CLK CAS Latency = 3 tPROZ3 3 - 3 - 3 - 3 - CLK CAS Latency = 2 tPROZ2 2 - 2 - 2 - 2 - CLK Power down exit time tPDE 1 - 1 - 1 - 1 - CLK Self refresh exit time tSRE 1 - 1 - 1 - 1 - CLK Refresh Time tREF 64 - 64 - 64 - 64 - ms Note RAS cycle time Precharge to data output Hi-Z 1 Note : 1. A new command can be given tRRC after self refresh exit. Rev. 1.5/Dec.98 Powered by ICminer.com Electronic-Library Service CopyRight 2003 8 HY57V168010D DEVICE OPERATING OPTION TABLE HY57V168010D-8 CAS Latency tRCD tRAS tRC tRP tAC tOH 125MHz 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns 100MHz 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 83MHz 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 3ns 66MHz 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 3ns CAS Latency tRCD tRAS tRC tRP tAC tOH 100MHz 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 83MHz 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 3ns 66MHz 2CLKs 2CLKs 3CLKs 5CLKs 2CLKs 6ns 3ns 50MHz 2CLKs 1CLK 3CLKs 4CLKs 1CLK 6ns 3ns CAS Latency tRCD tRAS tRC tRP tAC tOH 100MHz 3CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 83MHz 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 3ns 66MHz 2CLKs 2CLKs 3CLKs 5CLKs 2CLKs 6ns 3ns 50MHz 2CLKs 1CLK 3CLKs 4CLKs 1CLK 6ns 3ns CAS Latency tRCD tRAS tRC tRP tAC tOH 100MHz 3CLKs 3CLKs 5CLKs 8CLKs 3CLKs 8ns 3ns 83MHz 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 8ns 3ns 66MHz 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 8ns 3ns 50MHz 2CLKs 2CLKs 3CLKs 4CLKs 1CLK 8ns 3ns HY57V168010D-10P HY57V168010D-10S HY57V168010D-10 Rev. 1.5/Dec.98 Powered by ICminer.com Electronic-Library Service CopyRight 2003 9 HY57V168010D COMMAND TRUTH TABLE Command CKEn CS RAS CAS WE DQM Mode Register Set H X L L L L X OP code H X X X No Operation H X X X L H H H Row Address Bank Active H X L L H H X H X L H L H X Read Read with Auto precharge Write H X L H L L X Write with Auto precharge A0~A9 A10/ AP CKEn-1 Column Address Column Address Precharge All Bank H X L L H L X Precharge selected Bank Burst Stop H X U/LDQM H Auto Refresh H H L L L Entry H L L L H X Exit L H H H H L V V H L V H H X L V X X V X H X X L H X X X X X L H H H H X X X L H H H H X X X L H H H H X X X L V V V L Precharge power down Note L X X Self Refresh1 Entry L BA X X Exit Entry L H H L Clock Suspend Exit L X H X X X X Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high. 2. X=Do not care, L=Low, H=High, BA=Bank Address, RA= Row Address, CA=Column Address, Opcode=Operand Code, NOP=No Operation. Rev. 1.5/Dec.98 Powered by ICminer.com Electronic-Library Service CopyRight 2003 10 HY57V168010D PACKAGE INFORMATION 400mil 44pin Thin Small Outline Package (TC) 2Mx8 Synchronous DRAM Rev. 1.5/Dec.98 Powered by ICminer.com Electronic-Library Service CopyRight 2003 UNIT : INCH (mm) 11