512Mb DDR SDRAM HY5DU12422C(L)FP HY5DU12822C(L)FP HY5DU121622C(L)FP This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.5 / July 2006 1 1HY5DU12422C(L)FP HY5DU12822C(L)FP HY5DU121622C(L)FP Revision History Revision No. History Draft Date 1.0 First Version Release Mar. 2005 1.1 IDD specification revised July 2005 1.2 IDD6 specification revised Feb. 2006 1.3 State Diagram modified Apr. 2006 1.4 Added CL2 & CL2.5 values to the DDR400B in the AC CHARACTERISTICS June 2006 1.5 Editorial change on IDD5 Test condition July 2006 Rev. 1.5 / July 2006 Remark 2 1HY5DU12422C(L)FP HY5DU12822C(L)FP HY5DU121622C(L)FP DESCRIPTION The HY5DU12422C(L)FP, HY5DU12822C(L)FP and HY5DU121622C(L)FP are a 536,870,912-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. This Hynix 512Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2. FEATURES • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock • Programmable CAS latency 2/2.5 (DDR200, 266, 333) and 3 (DDR400) supported • Programmable burst length 2/4/8 with both sequential and interleave mode Source synchronous - data transaction aligned to bidirectional data strobe (DQS) • Internal four bank operations with single pulsed /RAS • x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O • Auto refresh and self refresh supported • Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) • tRAS lock out function supported • 8192 refresh cycles / 64ms • 60 Ball FBGA Package Type • On chip DLL align DQ and DQS transition with CK transition • Full and Half strength driver option controlled by EMRS • DM mask write data-in at the both rising and falling edges of the data strobe • Lead free (ROHS* Compliant) • VDD, VDDQ = 2.5V ± 0.2V for DDR200, 266, 333 VDD, VDDQ = 2.6V ± 0.1V for DDR400 • All inputs and outputs are compatible with SSTL_2 interface • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • OPERATING FREQUENCY ORDERING INFORMATION Part No. Configuration HY5DU12422C(L)FP-X* 128M x 4 HY5DU12822C(L)FP-X* 64M x 8 HY5DU121622C(L)FP-X* 32M x 16 *X means speed grade *ROHS (Restriction Of Hazardous Substance) Rev. 1.5 / July 2006 Package Grade Clock Rate 60ball FBGA (Lead free) -D43 200MHz@CL3 Remark (CL-tRCD-tRP) DDR400B (3-3-3) -J 133MHz@CL2 [email protected] DDR333 (2.5-3-3) -K 133MHz@CL2 [email protected] DDR266A (2-3-3) -H 100MHz@CL2 [email protected] -L 100MHz@CL2 DDR266B (2.5-3-3) DDR200 (2-2-2) 3 1HY5DU12422C(L)FP HY5DU12822C(L)FP HY5DU121622C(L)FP (X4) 1 2 3 7 8 9 (X8) 1 2 3 9 VDDQ NC VSS A VDD NC VDDQ A NC VDDQ DQ3 B DQ0 VSSQ NC NC VDDQ DQ6 B DQ1 VSSQ NC NC VSSQ NC C NC VDDQ NC NC VSSQ DQ5 C DQ2 VDDQ NC NC VDDQ DQ2 D DQ1 VSSQ NC NC VDDQ DQ4 D DQ3 VSSQ NC NC VSSQ DQS E NC VDDQ NC NC VSSQ DQS E NC VDDQ NC VREF VSS DM F NC VDD NC VREF VSS DM F NC VDD NC CK CK G WE CAS CK CK G WE CAS A12 CKE H RAS CS A12 CKE H RAS CS A11 A9 J BA1 BA0 A11 A9 J BA1 BA0 A8 A7 K A0 A10/AP A8 A7 K A0 A10/AP A6 A5 L A2 A1 A6 A5 L A2 A1 A3 A4 VSS M VDD A3 M VDD x8 Device Ball Pattern x4 Device Ball Pattern (X16) 8 VSSQ VSS VSS DQ0 VDD A4 DQ7 7 VSSQ 1 2 3 7 8 9 A VDD DQ0 VDDQ DQ13 B DQ2 VSSQ DQ1 VSSQ DQ11 C DQ4 VDDQ DQ3 VDDQ DQ9 D DQ6 VSSQ DQ5 VSSQ DQ15 VSS DQ14 VDDQ DQ12 DQ10 : B all E xisting [ F or R eference O nly ] : D epop ulate d B all Top V iew (See th e balls throu gh the P ackage) 1 2 3 4 5 6 7 8 9 A 1.0m m B C DQ8 VSSQ UDQS E LDQS VDDQ DQ7 VREF VSS UDM F LDM VDD NC CK CK G WE CAS A12 CKE H RAS CS D E F 12.0m m G H J K A11 A9 J BA1 BA0 A8 A7 K A0 A10/AP A6 A5 L A2 A1 A4 VSS M VDD A3 L M 10.0m m 0.8m m B G A P ackage B all P attern Top V iew x16 Device Ball Pattern ROW AND COLUMN ADDRESS TABLE ITEMS 128Mx4 64Mx8 32Mx16 Organization 32M x 4 x 4banks 16M x 8 x 4banks 8M x 16 x 4banks Row Address A0 - A12 A0 - A12 A0 - A12 Column Address A0-A9, A11, A12 A0-A9, A11 A0-A9 Bank Address BA0, BA1 BA0, BA1 BA0, BA1 Auto Precharge Flag A10 A10 A10 Refresh 8K 8K 8K Rev. 1.5 / July 2006 4 1HY5DU12422C(L)FP HY5DU12822C(L)FP HY5DU121622C(L)FP PIN DESCRIPTION PIN TYPE CK, /CK Input Clock: CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK (both directions of crossing). CKE Input Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE must be maintained high throughout READ and WRITE accesses. Input buffers, excluding CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after VDD is applied. /CS Input Chip Select: Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All commands are masked when CS is registered high. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. BA0, BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRECHARGE command is being applied. A0 ~ A12 Input Address Inputs: Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op code during a MODE REGISTER SET command. BA0 and BA1 define which mode register is loaded during the MODE REGISTER SET command (MRS or EMRS). /RAS, /CAS, /WE Input Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being entered. DM (LDM,UDM) Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0-Q7; UDM corresponds to the data on DQ8-Q15. DQS (LDQS,UDQS) I/O Data Strobe: Output with read data, input with write data. Edge aligned with read data, centered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-Q7; UDQS corresponds to the data on DQ8-Q15. DQ I/O Data input / output pin: Data bus VDD/VSS Supply Power supply for internal circuits and input buffers. VDDQ/VSSQ Supply Power supply for output buffers for noise immunity. VREF Supply Reference voltage for inputs for SSTL interface. NC NC Rev. 1.5 / July 2006 DESCRIPTION No connection. 5 1HY5DU12422C(L)FP HY5DU12822C(L)FP HY5DU121622C(L)FP FUNCTIONAL BLOCK DIAGRAM (128Mx4) 4Banks x 32Mbit x 4 I/O Double Data Rate Synchronous DRAM Input Buffer 4 Write Data Register 2-bit Prefetch Unit 8 32Mx4/Bank0 32Mx4/Bank2 8 32Mx4/Bank3 Mode Register 4 Output Buffer 32Mx4/Bank1 Command Decoder 2-bit Prefetch Unit Bank Control Sense AMP CLK /CLK CKE /CS /RAS /CAS /WE DM DS DQ [0:3] Row Decoder Column Decoder A0~A12 BA0, BA1 DQS Address Buffer Column Address Counter CLK_DLL DS CLK /CLK Data Strobe Transmitter Data Strobe Receiver DLL Block Mode Register Rev. 1.5 / July 2006 6 1HY5DU12422C(L)FP HY5DU12822C(L)FP HY5DU121622C(L)FP FUNCTIONAL BLOCK DIAGRAM (64Mx8) 4Banks x 16Mbit x 8 I/O Double Data Rate Synchronous DRAM Input Buffer 8 Write Data Register 2-bit Prefetch Unit 16 16Mx8/Bank0 16Mx8/Bank2 16 16Mx8/Bank3 Mode Register 8 Output Buffer 16Mx8/Bank1 Command Decoder 2-bit Prefetch Unit Bank Control Sense AMP CLK /CLK CKE /CS /RAS /CAS /WE DM DS DQ [0:7] Row Decoder Column Decoder A0~A12 BA0,BA1 DQS Address Buffer Column Address Counter CLK_DLL DS CLK /CLK Data Strobe Transmitter Data Strobe Receiver DLL Block Mode Register Rev. 1.5 / July 2006 7 1HY5DU12422C(L)FP HY5DU12822C(L)FP HY5DU121622C(L)FP FUNCTIONAL BLOCK DIAGRAM (32Mx16) 4Banks x 8Mbit x 16 I/O Double Data Rate Synchronous DRAM Input Buffer 16 Write Data Register 2-bit Prefetch Unit 32 8Mx16/Bank0 8Mx16/Bank2 32 8Mx16/Bank3 Mode Register 16 Output Buffer 8Mx16/Bank1 Command Decoder 2-bit Prefetch Unit Bank Control Sense AMP CLK /CLK CKE /CS /RAS /CAS /WE LDM UDM DS DQ[0:15] Row Decoder Column Decoder A0~A12 BA0, BA1 LDQS, UDQS Address Buffer Column Address Counter CLK_DLL LDQS UDQS CLK /CLK Data Strobe Transmitter Data Strobe Receiver DLL Block Mode Register Rev. 1.5 / July 2006 8 1HY5DU12422C(L)FP HY5DU12822C(L)FP HY5DU121622C(L)FP SIMPLIFIED COMMAND TRUTH TABLE Command CKEn-1 CKEn /CS /RAS /CAS /WE H X L L L L OP code H X L L L L OP code H X H X X X L H H H H X L L H H H X L H L H CA H X L H L L CA H X L L H L X Read Burst Stop1 H X L H H L X Auto Refresh1 H H L L L H X Entry H L L L L H Exit L H H X X X Extended Mode Register Set1,2 1,2 Mode Register Set Device Deselect1 No Operation1 Bank Active1 Read1 Read with Autoprecharge 1,3 Write1 Write with Autoprecharge1,4 Precharge All Banks1,5 Precharge selected Bank1 Self Refresh1 Entry H L Exit L H Entry H L Exit L H Precharge Power Down Mode 1 Active Power Down Mode1 L H H H H X X X L H H H H X X X L H H H H X X X L V V V ADDR A10/AP BA X RA V L H L H V V H X L V X X X X ( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation ) Note: 1. LDM/UDM states are Don’t Care. Refer to below Write Mask Truth Table. 2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS. Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP period from Precharge command. 3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+tRP). 4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+1+tWR+tRP). Write Recovery Time(tWR) is needed to guarantee that the last data has been completely written. 5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged. *For more information about Truth Table, refer to “Device Operation” section in Hynix website. Rev. 1.5 / July 2006 9 1HY5DU12422C(L)FP HY5DU12822C(L)FP HY5DU121622C(L)FP WRITE MASK TRUTH TABLE CKEn-1 CKEn /CS, /RAS, /CAS, /WE DM Data Write1 H X X L X Data-In Mask1 H X X H X Function ADDR A10/AP BA Note: 1. Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data. In case of x16 data I/O, LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15) respectively. Rev. 1.5 / July 2006 10 1HY5DU12422C(L)FP HY5DU12822C(L)FP HY5DU121622C(L)FP SIMPLIFIED STATE DIAGRAM Pow er A p p lie d Pow er On P re c h a rg e PREALL S e lf R e fre s h REFS REFSX MRS MRS EM RS REFA Id le A u to R e fre s h CKEL CKEH A c t iv e Pow er Down P re c h a rg e Pow er Down ACT CKEH CKEL B u rs t S to p Row A c t iv e W r it e Read W r it e Read W r it e A Read A W r it e Read Read W r it e A Read A Read A W r it e A Read A PRE PRE PRE PRE P re c h a rg e PREALL A u t o m a t ic S e q u e n c e Com m and Sequence P R E A L L = P r e c h a r g e A ll B a n k s M R S = M o d e R e g is t e r S e t E M R S = E x t e n d e d M o d e R e g is t e r S e t R E F S = E n t e r S e lf R e f r e s h R E F S X = E x it S e lf R e f r e s h R E F A = A u to R e fre s h Rev. 1.5 / July 2006 C K E L = E n te r P o w e r D o w n C K E H = E x it P o w e r D o w n A C T = A c t iv e W r it e A = W r it e w it h A u t o p r e c h a r g e R e a d A = R e a d w it h A u t o p r e c h a r g e P R E = P re c h a rg e 11 1HY5DU12422C(L)FP HY5DU12822C(L)FP HY5DU121622C(L)FP POWER-UP SEQUENCE AND DEVICE INITIALIZATION DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power must first be applied to VDD, then to VDDQ, and finally to VREF (and to the system VTT). VTT must be applied after VDDQ to avoid device latch-up, which may cause permanent damage to the device. VREF can be applied anytime after VDDQ, but is expected to be nominally coincident with VTT. Except for CKE, inputs are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after VDD is applied. Maintaining an LVCMOS LOW level on CKE during power-up is required to guarantee that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal operation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200us delay prior to applying an executable command. Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a EXTENDED MODE REGISTER SET command should be issued for the Extended Mode Register, to enable the DLL, then a MODE REGISTER SET command should be issued for the Mode Register, to reset the DLL, and to program the operating parameters. After the DLL reset, tXSRD(DLL locking time) should be satisfied for read command. After the Mode Register set command, a PRECHARGE ALL command should be applied, placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a MODE REGISTER SET command for the Mode Register, with the reset DLL bit deactivated low (i.e. to program operating parameters without resetting the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation. 1. Apply power - VDD, VDDQ, VTT, VREF in the following power up sequencing and attempt to maintain CKE at LVCMOS low state. (All the other input pins may be undefined.) • VDD and VDDQ are driven from a single power converter output. • VTT is limited to 1.44V (reflecting VDDQ(max)/2 + 50mV VREF variation + 40mV VTT variation. • VREF tracks VDDQ/2. • A minimum resistance of 42 Ohms (22 ohm series resistor + 22 ohm parallel resistor - 5% tolerance) limits the input current from the VTT supply into any pin. • If the above criteria cannot be met by the system design, then the following sequencing and voltage relationship must be adhered to during power up. Voltage description Sequencing Voltage relationship to avoid latch-up VDDQ After or with VDD < VDD + 0.3V VTT After or with VDDQ < VDDQ + 0.3V VREF After or with VDDQ < VDDQ + 0.3V 2. Start clock and maintain stable clock for a minimum of 200usec. 3. After stable power and clock, apply NOP condition and take CKE high. 4. Issue Extended Mode Register Set (EMRS) to enable DLL. 5. Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=high. (An additional 200 cycles(tXSRD) of clock are required for locking DLL) 6. Issue Precharge commands for all banks of the device. 7. Issue 2 or more Auto Refresh commands. 8. Issue a Mode Register Set command to initialize the mode register with bit A8 = Low Rev. 1.5 / July 2006 12 1HY5DU12422C(L)FP HY5DU12822C(L)FP HY5DU121622C(L)FP Power-Up Sequence VDD VDDQ tVTD VTT VREF /CLK CLK tIS tIH CKE LVCMOS Low Level CMD NOP PRE EMRS MRS ADDR CODE A10 BA0, BA1 NOP PRE AREF MRS ACT RD CODE CODE CODE CODE CODE CODE CODE CODE CODE CODE CODE CODE CODE CODE Non-Read Command READ DM DQS DQ'S T=200usec tRP tMRD tMRD tRP tRFC tMRD tXSRD* Power UP VDD and CK stable Precharge All EMRS Set MRS Set Reset DLL (with A8=H) Precharge All 2 or more Auto Refresh MRS Set (with A8=L) * 200 cycle(tXSRD) of CK are required (for DLL locking) before Read Command Rev. 1.5 / July 2006 13 1HY5DU12422C(L)FP HY5DU12822C(L)FP HY5DU121622C(L)FP MODE REGISTER SET (MRS) The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length, burst type, test mode, DLL reset. The mode register is programed via MRS command. This command is issued by the low signals of /RAS, /CAS, /CS, /WE and BA0. This command can be issued only when all banks are in idle state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. Two cycles are required to write the data in mode register. During the MRS cycle, any command cannot be issued. Once mode register field is determined, the information will be held until reset by another MRS command. BA1 BA0 0 0 A12 A11 A10 A9 A8 A7 Operating Mode A6 A5 A4 CAS Latency A3 A2 BT A1 Burst Length BA0 MRS Type A6 A5 A4 CAS Latency A3 Burst Type 0 MRS 0 0 0 Reserved 0 Sequential 1 EMRS 0 0 1 Reserved 1 Interleave 0 1 0 2 0 1 1 3 1 0 0 Reserved 1 0 1 1.5 1 1 0 2.5 1 1 1 Reserved A0 Burst Length A2 A1 A0 Sequential Interleave 0 0 0 Reserved Reserved 0 0 1 2 2 0 1 0 4 4 A12~A9 A8 A7 A6~A0 Operating Mode 0 1 1 8 8 0 0 0 Valid Normal Operation 1 0 0 Reserved Reserved 0 1 0 Valid Normal Operation/ Reset DLL 1 0 1 Reserved Reserved 0 0 1 VS Vendor specific Test Mode 1 1 0 Reserved Reserved - - - - All other states reserved 1 1 1 Reserved Reserved Rev. 1.5 / July 2006 14 1HY5DU12422C(L)FP HY5DU12822C(L)FP HY5DU121622C(L)FP BURST DEFINITION Burst Length Starting Address (A2,A1,A0) Sequential Interleave XX0 0, 1 0, 1 XX1 1, 0 1, 0 X00 0, 1, 2, 3 0, 1, 2, 3 X01 1, 2, 3, 0 1, 0, 3, 2 X10 2, 3, 0, 1 2, 3, 0, 1 X11 3, 0, 1, 2 3, 2, 1, 0 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 2 4 8 BURST LENGTH & TYPE Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column locations that can be accessed for a given Read or Write command. Burst lengths of 2, 4 or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2 -Ai when the burst length is set to four and by A3 -Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both Read and Write bursts. Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Burst Definition Table CAS LATENCY The Read latency or CAS latency is the delay in clock cycles between the registration of a Read command and the availability of the first burst of output data. The latency can be programmed 2 or 2.5 clocks for DDR200/266/333 and 3 clocks for DDR400. If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with clock edge n + m. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Rev. 1.5 / July 2006 15 1HY5DU12422C(L)FP HY5DU12822C(L)FP HY5DU121622C(L)FP DLL RESET The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externally applied clock before an any command can be issued. OUTPUT DRIVER IMPEDANCE CONTROL The normal drive strength for all outputs is specified to be SSTL_2, Class II. Hynix also supports a half strength driver option, intended for lighter load and/or point-to-point environments. Selection of the half strength driver option will reduce the output drive strength by 50% of that of the full strength driver. I-V curves for both the full strength driver and the half strength driver are included in this document. Rev. 1.5 / July 2006 16 1HY5DU12422C(L)FP HY5DU12822C(L)FP HY5DU121622C(L)FP EXTENDED MODE REGISTER SET (EMRS) The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include DLL enable/disable, output driver strength selection(optional). These functions are controlled via the bits shown below. The Extended Mode Register is programmed via the Mode Register Set command (BA0=1 and BA1=0) and will retain the stored information until it is programmed again or the device loses power. The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements will result in unspecified operation. BA1 BA0 0 1 A12 A11 A10 A9 A8 A7 A6 A5 A4 Operating Mode BA0 MRS Type 0 MRS 1 EMRS An~A3 A2~A0 Operating Mode 0 Valid Normal Operation _ _ All other states reserved A3 A2 A1 A0 0* DS DLL A0 DLL enable 0 Enable 1 Disable A1 Output Driver Impedance Control 0 Full Strength Driver 1 Half Strength Driver * This part do not support/QFC function, A2 must be programmed to Zero. Rev. 1.5 / July 2006 17 1HY5DU12422C(L)FP HY5DU12822C(L)FP HY5DU121622C(L)FP ABSOLUTE MAXIMUM RATINGS Parameter Operating Temperature (Ambient) Storage Temperature Voltage on VDD relative to VSS Voltage on VDDQ relative to VSS Voltage on inputs relative to VSS Voltage on I/O pins relative to VSS Output Short Circuit Current Soldering Temperature ⋅ Time Symbol Rating TA 0 ~ 70 Unit o TSTG -55 ~ 150 o VDD VDDQ VINPUT VIO IOS -1.0 ~ 3.6 -1.0 ~ 3.6 -1.0 ~ 3.6 -0.5 ~3.6 50 TSOLDER 260 ⋅ 10 C C V V V V mA o C ⋅ Sec Note: Operation at above absolute maximum rating can adversely affect device reliability DC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V) Parameter Symbol Min Typ. Max Unit Power Supply Voltage (DDR200, 266, 333) VDD 2.3 2.5 2.7 V Power Supply Voltage (DDR200, 266, 333)1 VDDQ 2.3 2.5 2.7 V VDD 2.5 2.6 2.7 V VDDQ 2.5 2.6 2.7 V VIH VREF + 0.15 - VDDQ + 0.3 V Power Supply Voltage (DDR400) 1 Power Supply Voltage (DDR400) Input High Voltage Input Low Voltage2 VIL -0.3 - VREF - 0.15 V Termination Voltage VTT VREF - 0.04 VREF VREF + 0.04 V 3 VREF 0.49*VDDQ 0.5*VDDQ 0.51*VDDQ V Input Voltage Level, CK and CK inputs VIN(DC) -0.3 - VDDQ+0.3 V VID(DC) 0.36 - VDDQ+0.6 V VI(RATIO) 0.71 - 1.4 - ILI -2 - 2 uA ILO -5 - 5 uA IOH -16.8 - - mA IOL 16.8 - - mA IOH -13.6 - - mA IOL 13.6 - - mA Reference Voltage Input Differential Voltage, CK and CK inputs4 V-I Matching: Pullup to Pulldown Current Input Leakage Ratio5 Current6 Output Leakage Current7 Normal Strength Output Driver (VOUT=VTT ± 0.84) Half Strength Output Driver (VOUT=VTT ± 0.68) Output High Current (min VDDQ, min VREF, min VTT) Output Low Current (min VDDQ, max VREF, max VTT) Output High Current (min VDDQ, min VREF, min VTT) Output Low Current (min VDDQ, max VREF, max VTT) Note: 1. VDDQ must not exceed the level of VDD. 2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration. 3. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of the same. Peak to peak noise on VREF may not exceed ± 2% of the DC value. 4. VID is the magnitude of the difference between the input level on CK and the input level on /CK. 5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0. 6. VIN=0 to VDD, All other pins are not tested under VIN =0V. 7. DQs are disabled, VOUT=0 to VDDQ Rev. 1.5 / July 2006 18 1HY5DU12422C(L)FP HY5DU12822C(L)FP HY5DU121622C(L)FP IDD SPECIFICATION AND CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V) Test Conditions Test Condition Symbol Operating Current: One bank; Active - Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle IDD0 Operating Current: One bank; Active - Read - Precharge; Burst Length=2; tRC=tRC(min); tCK=tCK(min); address and control inputs changing once per clock cycle IDD1 Precharge Power Down Standby Current: All banks idle; Power down mode; CKE=Low, tCK=tCK(min) IDD2P Idle Standby Current: Vin>=Vih(min) or Vin=<Vil(max) for DQ, DQS and DM IDD2N Idle Standby Current: /CS=High, All banks idle; tCK=tCK(min); CKE=High; address and control inputs changing once per clock cycle. VIN=VREF for DQ, DQS and DM IDD2F Idle Quiet Standby Current: /CS>=Vih(min); All banks idle; CKE>=Vih(min); Addresses and other control inputs stable, Vin=Vref for DQ, DQS and DM IDD2Q Active Power Down Standby Current: One bank active; Power down mode; CKE=Low, tCK=tCK(min) IDD3P Active Standby Current: /CS=HIGH; CKE=HIGH; One bank; Active-Precharge; tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle IDD3N Operating Current: Burst=2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); IOUT=0mA IDD4R Operating Current: Burst=2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle IDD4W Auto Refresh Current: tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A & DDR266B at 133Mhz; distributed refresh tRC=tRFC(min) - 12*tCK for DDR333 at 166Mhz, 14*tCK for DDR400 at 200Mhz IDD5 Self Refresh Current: CKE =< 0.2V; External clock on; tCK=tCK(min) IDD6 Operating Current - Four Bank Operation: Four bank interleaving with BL=4, Refer to the following page for detailed test condition IDD7 Rev. 1.5 / July 2006 19 1HY5DU12422C(L)FP HY5DU12822C(L)FP HY5DU121622C(L)FP DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7 IDD1: Operating current: One bank operation 1. Typical Case: VDD = 2.5V, T=25 oC for DDR200, 266, 333; VDD = 2.6V, T=25 oC for DDR400 2. Worst Case: VDD = 2.7V, T= 0 oC 3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. lout = 0mA 4. Timing patterns - DDR200(100Mhz, CL=2): tCK = 10ns, CL2, BL=2, tRCD = 2*tCK, tRC = 10*tCK, tRAS = 5*tCK Read: A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing 50% of data changing at every burst - DDR266B(133Mhz, CL=2.5): tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK Read: A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing 50% of data changing at every burst - DDR266A (133Mhz, CL=2): tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK Read: A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing 50% of data changing at every burst - DDR333(166Mhz, CL=2.5): tCK = 6ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 10*tCK, tRAS = 7*tCK Read: A0 N N R0 N N N P0 N N A0 N - repeat the same timing with random address changing 50% of data changing at every burst - DDR400(200Mhz, CL=3): tCK = 5ns, CL=3, BL=4, tRCD = 3*tCK, tRC = 11*tCK, tRAS = 8*tCK Read: A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing 50% of data changing at every burst Legend: A=Activate, R=Read, W=Write, P=Precharge, N=NOP IDD7: Operating current: Four bank operation 1. Typical Case: VDD = 2.5V, T=25 oC for DDR200, 266, 333; VDD = 2.6V, T=25 oC for DDR400 2. Worst Case: VDD = 2.7V, T= 0 oC 3. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not changing. lout = 0mA 4. Timing patterns - DDR200(100Mhz, CL=2): tCK = 10ns, CL2, BL=4, tRRD = 2*tCK, tRCD= 3*tCK, Read with Autoprecharge Read: A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing 50% of data changing at every burst - DDR266B(133Mhz, CL=2.5): tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK Read with autoprecharge Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing 50% of data changing at every burst - DDR266A (133Mhz, CL=2): tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing 50% of data changing at every burst - DDR333(166Mhz, CL=2.5): tCK = 6ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing 50% of data changing at every burst - DDR400(200Mhz, CL=3): tCK = 5ns, CL = 2, BL = 4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing 50% of data changing at every burst Legend: A=Activate, R=Read, W=Write, P=Precharge, N=NOP Rev. 1.5 / July 2006 20 1HY5DU12422C(L)FP HY5DU12822C(L)FP HY5DU121622C(L)FP IDD Specification 128Mx4 Parameter Symbol Speed DDR400B DDR333 DDR266A DDR266B Operating Current IDD0 130 120 100 Operating Current IDD1 170 150 120 Precharge Power Down Standby Current IDD2P DDR200 Unit mA mA 10 mA Idle Standby Current IDD2F 35 mA Idle Quiet Standby Current IDD2Q 30 mA Active Power Down Standby Current IDD3P 45 mA Active Standby Current IDD3N 60 Operating Current IDD4R Operating Current IDD4W 230 210 180 IDD5 260 240 220 Auto Refresh Current Self Refresh Current Normal Low Power Operating Current - Four Bank Operation 210 190 mA 5 IDD6 IDD7 mA 170 mA 3 360 350 DDR400B DDR333 mA 340 mA 64Mx8 Parameter Symbol Speed DDR266A DDR266B Operating Current IDD0 130 120 100 Operating Current IDD1 170 150 120 Precharge Power Down Standby Current IDD2P 10 DDR200 Unit mA mA mA Idle Standby Current IDD2F 35 mA Idle Quiet Standby Current IDD2Q 30 mA Active Power Down Standby Current IDD3P 45 mA Active Standby Current IDD3N 60 Operating Current IDD4R Operating Current IDD4W 230 210 180 IDD5 260 240 220 Auto Refresh Current Self Refresh Current Normal Low Power Operating Current - Four Bank Operation Rev. 1.5 / July 2006 210 190 5 IDD6 IDD7 mA 170 mA 3 360 350 mA mA 340 mA 21 1HY5DU12422C(L)FP HY5DU12822C(L)FP HY5DU121622C(L)FP 32Mx16 Parameter Symbol Speed DDR400B DDR333 DDR266A DDR266B DDR200 Unit Operating Current IDD0 130 120 100 mA Operating Current IDD1 170 150 120 mA Precharge Power Down Standby Current IDD2P 10 mA Idle Standby Current IDD2F 35 mA Idle Quiet Standby Current IDD2Q 30 mA Active Power Down Standby Current IDD3P 45 mA Active Standby Current IDD3N 60 Operating Current IDD4R 210 190 170 Operating Current IDD4W 230 210 180 IDD5 260 240 220 Auto Refresh Current Self Refresh Current Normal Low Power Operating Current - Four Bank Operation Rev. 1.5 / July 2006 5 IDD6 IDD7 mA mA 3 360 350 mA mA 340 mA 22 1HY5DU12422C(L)FP HY5DU12822C(L)FP HY5DU121622C(L)FP AC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V) Parameter Symbol Min Max Unit Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31 - V Input Low (Logic 0) Voltage, DQ, DQS and DM signals VIL(AC) - VREF - 0.31 V Input Differential Voltage, CK and /CK inputs1 VID(AC) 0.7 VDDQ + 0.6 V Input Crossing Point Voltage, CK and /CK inputs2 VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V Note: 1. VID is the magnitude of the difference between the input level on CK and the input on /CK. 2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same. *For more information about AC Overshoot/Undershoot Specifications, refer to “Device Operation” section in hynix website. AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V) Parameter Value Unit Reference Voltage VDDQ x 0.5 V Termination Voltage VDDQ x 0.5 V AC Input High Level Voltage (VIH, min) VREF + 0.31 V AC Input Low Level Voltage (VIL, max) VREF - 0.31 V Input Timing Measurement Reference Level Voltage VREF V Output Timing Measurement Reference Level Voltage VTT V Input Signal maximum peak swing 1.5 V Input minimum Signal Slew Rate 1 V/ns Termination Resistor (RT) 50 Ω Series Resistor (RS) 25 W Output Load Capacitance for Access Time Measurement (CL) 30 pF Rev. 1.5 / July 2006 23 1HY5DU12422C(L)FP HY5DU12822C(L)FP HY5DU121622C(L)FP AC CHARACTERISTICS (note: 1 - 9 / AC operating conditions unless otherwise noted) Parameter Symbol DDR400B DDR333 DDR266A DDR266B DDR200 Min Max Min Max Min Max Min Max Min Max UNIT Row Cycle Time tRC 55 - 60 - 65 - 65 - 70 - ns Auto Refresh Row Cycle Time tRFC 70 - 72 - 75 - 75 - 80 - ns Row Active Time tRAS 40 70K 42 70K 45 120K 45 120K 50 120K ns tRAP tRCD or tRASmin - tRCD or tRASmin - tRCD or tRASmin - tRCD or tRASmin - tRCD or tRASmin - ns Row Address to Column Address Delay tRCD 15 - 18 - 20 - 20 - 20 - ns Row Active to Row Active Delay tRRD 10 - 12 - 15 - 15 - 15 - ns Column Address to Column Address Delay tCCD 1 - 1 - 1 - 1 - 1 - tCK Row Precharge Time tRP 15 - 18 - 20 - 20 - 20 - ns Write Recovery Time tWR 15 - 15 - 15 - 15 - 15 - ns Internal Write to Read Command Delay tWTR 2 - 1 - 1 - 1 - 1 - tCK tDAL (tWR/ tCK) + (tRP/tCK) - (tWR/ tCK) + (tRP/tCK) - (tWR/ tCK) + (tRP/tCK) - (tWR/ tCK) + (tRP/tCK) - (tWR/ tCK) + (tRP/tCK) - tCK 5 10 - - - - - - - - ns 6 12 6 12 7.5 12 7.5 12 8.0 12 ns 7.5 12 7.5 12 7.5 12 10 12 10 12 ns Active to Read with Auto Precharge Delay Auto Precharge Write Recovery + Precharge Time22 CL = 3 System Clock Cycle CL = 2.5 Time24 CL = 2 tCK Clock High Level Width tCH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK Clock Low Level Width tCL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK Data-Out edge to Clock edge Skew tAC -0.7 0.7 -0.7 0.7 -0.75 0.75 -0.75 0.75 -0.75 0.75 ns -0.55 0.55 -0.6 0.6 -0.75 0.75 -0.75 0.75 -0.75 0.75 ns tDQSQ - 0.4 - 0.4 - 0.5 - 0.5 - 0.6 ns tQH tHP -tQHS - tHP -tQHS - tHP -tQHS - tHP -tQHS - tHP -tQHS - ns tHP min (tCL,tCH) - min (tCL,tCH) - min (tCL,tCH) - min (tCL,tCH) - min (tCL,tCH) - ns tQHS - 0.5 - 0.5 - 0.75 - 0.75 - 0.75 ns DQS-Out edge to Clock tDQSCK edge Skew DQS-Out edge to DataOut edge Skew21 Data-Out hold time from DQS20 Clock Half Period19,20 Data Hold Skew Factor20 Valid Data Output Window Rev. 1.5 / July 2006 tDV tQH-tDQSQ tQH-tDQSQ tQH-tDQSQ tQH-tDQSQ tQH-tDQSQ ns 24 1HY5DU12422C(L)FP HY5DU12822C(L)FP HY5DU121622C(L)FP - Continue Parameter Symbol DDR400B DDR333 DDR266A DDR266B DDR200 UNIT Min Max Min Max Min Max Min Max Min Max tHZ -0.7 0.7 -0.7 0.7 -0.75 0.75 -0.75 0.75 -0.8 0.8 ns tLZ -0.7 0.7 -0.7 0.7 -0.75 0.75 -0.75 0.75 -0.8 0.8 ns tIS 0.6 - 0.75 - 0.9 - 0.9 - 1.1 - ns tIH 0.6 - 0.75 - 0.9 - 0.9 - 1.1 - ns tIS 0.7 - 0.8 - 1.0 - 1.0 - 1.1 - ns tIH 0.7 - 0.8 - 1.0 - 1.0 - 1.1 - ns tIPW 2.2 - 2.2 - 2.2 - 2.2 - 2.5 - ns Write DQS High Level Width tDQSH 0.35 - 0.35 - 0.35 - 0.35 - 0.35 - tCK Write DQS Low Level Width tDQSL 0.35 - 0.35 - 0.35 - 0.35 - 0.35 - tCK Clock to First Rising edge of DQSIn tDQSS 0.72 1.25 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tCK DQS falling edge to CK setup time tDSS 0.2 - 0.2 - 0.2 - 0.2 - 0.2 - tCK DQS falling edge hold time from CK tDSH 0.2 - 0.2 - 0.2 - 0.2 - 0.2 - tCK DQ & DM input setup time25 tDS 0.4 - 0.45 - 0.5 - 0.5 - 0.6 - ns DQ & DM input hold time25 tDH 0.4 - 0.45 - 0.5 - 0.5 - 0.6 - ns DQ & DM Input Pulse Width17 tDIPW 1.75 - 1.75 - 1.75 - 1.75 - 2 - ns Read DQS Preamble Time tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCK Read DQS Postamble Time tRPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK 0 - 0 - 0 - 0 - 0 - ns - 0.25 - 0.25 - 0.25 - 0.25 - tCK Data-out high-impedance window from CK,/CK10 Data-out low-impedance window from CK, /CK10 Input Setup Time (fast slew rate)14,16-18 Input Hold Time (fast slew rate)14,16-18 Input Setup Time (slow slew rate)15-18 Input Hold Time (slow slew rate)15-18 Input Pulse Width17 Write DQS Preamble Setup Time12 tWPRES Write DQS Preamble Hold Time tWPREH 0.25 Write DQS Postamble Time11 tWPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK Mode Register Set Delay tMRD 2 - 2 - 2 - 2 - 2 - tCK tXSNR 75 - 75 - 75 - 75 - 80 - ns tXSRD 200 - 200 - 200 - 200 - 200 - tCK tREFI - 7.8 - 7.8 - 7.8 - 7.8 - 7.8 us Exit Self Refresh to non-Read command23 Exit Self Refresh to Read command Average Periodic Refresh Interval13,25 Rev. 1.5 / July 2006 25 1HY5DU12422C(L)FP HY5DU12822C(L)FP HY5DU121622C(L)FP Note: 1. All voltages referenced to Vss. 2. Tests for ac timing, IDD, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Below figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). VDDQ Output (VOUT) 50 Ω 30 pF Figure: Timing Reference Load 4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK, /CK), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between VIL(ac) and VIH(ac). 5. The ac and dc input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above (below) the dc input LOW (HIGH) level. 6. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE < 0.2VDDQ is recognized as LOW. 7. The CK, /CK input reference level (for timing referenced to CK, /CK) is the point at which CK and /CK cross; the input reference level for signals other than CK, /CK is VREF. 8. The output timing reference voltage level is VTT. 9. Operation or timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 10. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ). 11. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 12. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from High-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 13. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. 14. For command/address input slew rate ≥ 1.0 V/ns. 15. For command/address input slew rate ≥ 0.5 V/ns and ＜ 1.0 V/ns 16. For CK & /CK slew rate ≥ 1.0 V/ns (single-ended) 17. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 18. Slew Rate is measured between VOH(ac) and VOL(ac). 19. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). For example, tCL and tCH are = 50% of the period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces. Rev. 1.5 / July 2006 26 1HY5DU12422C(L)FP HY5DU12822C(L)FP HY5DU121622C(L)FP 20.tQH = tHP - tQHS, where: tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push--out of DQS on one transition followed by the worst case pull--in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 21. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle. 22. tDAL = (tWR/tCK) + (tRP/tCK) For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266B at CL=2.5 and tCK=7.5 ns tDAL = ((15 ns / 7.5 ns) + (20 ns / 7.5 ns)) clocks = ((2) + (3)) clocks = 5 clocks 23. In all circumstances, tXSNR can be satisfied using tXSNR = tRFCmin + 1*tCK 24. The only time that the clock frequency is allowed to change is during self-refresh mode. 25. If refresh timing or tDS/tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed. Rev. 1.5 / July 2006 27 1HY5DU12422C(L)FP HY5DU12822C(L)FP HY5DU121622C(L)FP SYSTEM CHARACTERISTICS CONDITIONS for DDR SDRAMS The following tables are described specification parameters that required in systems using DDR devices to ensure proper performance. These characteristics are for system simulation purposes and are guaranteed by design. Input Slew Rate for DQ/DM/DQS AC CHARACTERISTICS (Table a.) DDR400 DDR333 DDR266 DDR200 PARAMETER Symbol min max min max min max min max DQ/DM/DQS input slew rate measured between VIH(DC), VIL(DC) and VIL(DC), VIH(DC) DCSLEW 0.5 4.0 0.5 4.0 0.5 4.0 0.5 4.0 UNIT Note V/ns 1,12 Address & Control Input Setup & Hold Time Derating (Table b.) Input Slew Rate Delta tIS Delta tIH UNIT Note 0.5 V/ns 0 0 ps 9 0.4 V/ns +50 0 ps 9 0.3 V/ns +100 0 ps 9 DQ & DM Input Setup & Hold Time Derating (Table c.) Input Slew Rate Delta tDS Delta tDH UNIT Note 0.5 V/ns 0 0 ps 11 0.4 V/ns +75 0 ps 11 0.3 V/ns +150 0 ps 11 DQ & DM Input Setup & Hold Time Derating for Rise/Fall Delta Slew Rate Input Slew Rate Delta tDS Delta tDH UNIT Note ± 0.0 ns/V 0 0 ps 10 ± 0.25 ns/V +50 +50 ps 10 ± 0.5 ns/V +100 +100 ps 10 Output Slew Rate Characteristics (for x4, x8 Devices) (Table d.) (Table e.) Slew Rate Characteristic Typical Range (V/ns) Minimum (V/ns) Maximum (V/ns) Note Pullup Slew Rate 1.2 - 2.5 1.0 4.5 1,3,4,6,7,8 Pulldown Slew Rate 1.2 - 2.5 1.0 4.5 2,3,4,6,7,8 Output Slew Rate Characteristics (for x16 Device) (Table f.) Slew Rate Characteristic Typical Range (V/ns) Minimum (V/ns) Maximum (V/ns) Note Pullup Slew Rate 1.2 - 2.5 1.0 4.5 1,3,4,6,7,8 Pulldown Slew Rate 1.2 - 2.5 1.0 4.5 2,3,4,6,7,8 Output Slew Rate Matching Ratio Characteristics Slew Rate Characteristic DDR266A (Table g.) DDR266B DDR200 Parameter min max min max min max Output Slew Rate Matching Ratio (Pullup to Pulldown) - - - - 0.71 1.4 Rev. 1.5 / July 2006 Note 5,12 28 1HY5DU12422C(L)FP HY5DU12822C(L)FP HY5DU121622C(L)FP Note: 1. Pullup slew rate is characterized under the test conditions as shown in below Figure. Test Point Output (VOUT) 50 Ω VSSQ Figure: Pullup Slew rate 2. Pulldown slew rate is measured under the test conditions shown in below Figure. VDDQ Output (VOUT) 50Ω Test Point Figure: Pulldown Slew rate 3. Pullup slew rate is measured between (VDDQ/2 - 320 mV ± 250mV) Pulldown slew rate is measured between (VDDQ/2 + 320mV ± 250mV) Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output switching. Example: For typical slew, DQ0 is switching For minimum slew rate, all DQ bits are switching worst case pattern For maximum slew rate, only one DQ is switching from either high to low, or low to high. The remaining DQ bits remain the same as for previous state. 4. Evaluation conditions Typical: 25 oC (Ambient), VDDQ = nominal, typical process Minimum: 70 oC (Ambient), VDDQ = minimum, slow-slow process Maximum: 0 oC (Ambient), VDDQ = Maximum, fast-fast process 5. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. 6. Verified under typical conditions for qualification purposes. 7. TSOP-II package devices only. 8. Only intended for operation up to 256 Mbps per pin. 9. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5 V/ns as shown in Table b. The Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. 10. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables c & d. Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, fall rate. Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(slew Rate2)} For example: If Slew Rate 1 is 0.5 V/ns and Slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is -0.5 ns/V. Using the table given, this would result in the need for an increase in tDS and tDH of 100ps. 11. Table c is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser of the AC-AC slew rate and the DC-DC slew rate. The input slew rate is based on the lesser of the slew rates determined by either VIH(ac) to VIL(AC) or VIH(DC) to VIL(DC), and similarly for rising transitions. 12. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions through the DC region must be monotonic. Rev. 1.5 / July 2006 29 1HY5DU12422C(L)FP HY5DU12822C(L)FP HY5DU121622C(L)FP CAPACITANCE (TA=25oC, f=100MHz) Parameter Pin Symbol Min Max Unit Input Clock Capacitance CK, /CK CI1 1.5 2.5 pF Delta Input Clock Capacitance CK, /CK Delta CI1 - 0.25 pF Input Capacitance All other input-only pins CI1 1.5 2.5 pF Delta Input Capacitance All other input-only pins Delta CI2 - 0.5 pF Input / Output Capacitance DQ, DQS, DM CIO 3.5 4.5 pF Delta Input / Output Capacitance DQ, DQS, DM Delta CIO - 0.5 pF Note: 1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V 2. Pins not under test are tied to GND. 3. These values are guaranteed by design and are tested on a sample basis only. OUTPUT LOAD CIRCUIT V TT R T =50Ω Output Zo=50Ω V REF C L =30pF Rev. 1.5 / July 2006 30 1HY5DU12422C(L)FP HY5DU12822C(L)FP HY5DU121622C(L)FP PACKAGE INFORMATION 10.0±0.10 0.15C (4x) B All dimensions in millimeters A 12.0±0.10 A1 BALL MARK 1.10±0.10 0.34±0.10 C 0.10 60A1 BALL MARK 1 0.80 2 3 0.80 7 8 x8= 6.40 BOTTOM VIEW Rev. 1.5 / July 2006 9 0.45±0.05 0.15 M C A B SEATING PLANE 1.00 1.00 x11= 11.00 A B C D E F G H J K L M TOP VIEW C 31