ETC HY5DU121622AT

HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
512Mb DDR SDRAM
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility
for use of circuits described. No patent licenses are implied.
Rev. 0.3/Jan. 03
1
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
Revision History
1. Rev 0.0 (Nov. 26)
1) Datasheet Release in Preliminary version
2. Rev 0.1 (Dec. 26)
1) Correction of typo in page 3,19,29,31
2) Change IDD value
3. Rev 0.2 (Dec. 30)
1) Correction of tLZ/tHZ in AC Characteristics
4. Rev 0.3 (Jan. 30)
1) Correction of IDD value
2) Insert DC test timing pattern for DDR400/DDR333
Rev. 0.3/Jan. 03
2
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
PRELIMINARY
DESCRIPTION
The HY5DU12422A(L)T, HY5DU12822A(L)T and HY5DU121622A(L)T are a 536,870,912-bit CMOS Double Data Rate(DDR)
Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth.
This Hynix 512Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock.
While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and
Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit
prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2.
FEATURES
•
VDD , VDDQ = 2.5V +/- 0.2V
•
•
All inputs and outputs are compatible with SSTL_2 interface
All addresses and control inputs except data, data strobes
and data masks latched on the rising edges of the clock
•
Programmable /CAS latency 2 / 2.5/3 supported
•
Fully differential clock inputs (CK, /CK) operation
•
•
Double data rate interface
Programmable burst length 2 / 4 / 8 with both sequential
and interleave mode
•
Source synchronous - data transaction aligned to bidirectional data strobe (DQS)
•
Internal four bank operations with single pulsed
/RAS
•
x16 device has two bytewide data strobes (UDQS, LDQS)
per each x8 I/O
•
Auto refresh and self refresh supported
•
tRAS lock out function supported
•
8192 refresh cycles / 64ms
•
JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin
pitch
•
Full and Half strength driver option controlled by EMRS
•
Data outputs on DQS edges when read (edged DQ) Data
inputs on DQS centers when write (centered DQ)
•
On chip DLL align DQ and DQS transition with CK transition
•
DM mask write data-in at the both rising and falling edges
of the data strobe
ORDERING INFORMATION
OPERATING FREQUENCY
Part No.
Configuration
Power
Grade
Freq.
Remark**
HY5DU12422AT-X*
128Mx4
Standard
- D43
200MHz
DDR400 3-3-3
HY5DU12422ALT-X*
128Mx4
Low Power
-J
166Mhz
DDR333
HY5DU12822AT-X*
64Mx8
Standard
-M
133MHz
DDR266 2-2-2
HY5DU12822ALT-X*
64Mx8
Low Power
-K
133MHz
DDR266A
HY5DU121622AT-X*
32Mx16
Standard
-H
133MHz
DDR266B
HY5DU121622ALT-X*
32Mx16
Low Power
* X : speed grade
** JEDEC specification compliant
Rev. 0.3/Jan. 03
3
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
PIN CONFIGURATION
x4
x8
VDD
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
x16
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
400mil X 875mil
66pin TSOP -II
0.65mm pin pitch
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
x16
x8
x4
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
/CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
ROW AND COLUMN ADDRESS TABLE
Rev. 0.3/Jan. 03
ITEMS
128Mx4
64Mx8
32Mx16
Organization
32M x 4 x 4banks
16M x 8 x 4banks
8M x 16 x 4banks
Row Address
A0 - A12
A0 - A12
A0 - A12
Column Address
A0-A9, A11, A12
A0-A9, A11
A0-A9
Bank Address
BA0, BA1
BA0, BA1
BA0, BA1
Auto Precharge Flag
A10
A10
A10
Refresh
8K
8K
8K
4
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
PIN DESCRIPTION
PIN
TYPE
DESCRIPTION
CK, /CK
Input
Clock: CK and /CK are differential clock inputs. All address and control input signals are sampled
on the crossing of the positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK (both directions of crossing).
CKE
Input
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device
input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER DOWN and
SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any
bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF REFRESH entry.
CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE must be maintained
high throughout READ and WRITE accesses. Input buffers, excluding CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are disabled during SELF
REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after Vdd is
applied.
/CS
Input
Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All commands
are masked when CS is registered high. CS provides for external bank selection on systems with
multiple banks. CS is considered part of the command code.
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRECHARGE command is being applied.
A0 ~ A12
Input
Address Inputs: Provide the row address for ACTIVE commands, and the column address and
AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory
array in the respective bank. A10 is sampled during a precharge command to determine whether
the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is
to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op code
during a MODE REGISTER SET command. BA0 and BA1 define which mode register is loaded
during the MODE REGISTER SET command (MRS or EMRS).
/RAS, /CAS, /WE
Input
Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being entered.
DM
(LDM,UDM)
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges
of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For
the x16, LDM corresponds to the data on DQ0-Q7; UDM corresponds to the data on DQ8-Q15.
DQS
(LDQS,UDQS)
I/O
Data Strobe: Output with read data, input with write data. Edge aligned with read data, centered in
write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-Q7;
UDQS corresponds to the data on DQ8-Q15.
DQ
I/O
Data input / output pin : Data bus
VDD /VSS
Supply
Power supply for internal circuits and input buffers.
V DDQ/VSSQ
Supply
Power supply for output buffers for noise immunity.
V REF
Supply
Reference voltage for inputs for SSTL interface.
NC
NC
Rev. 0.3/Jan. 03
No connection.
5
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
FUNCTIONAL BLOCK DIAGRAM (128Mx4)
4Banks x 32Mbit x 4 I/O Double Data Rate Synchronous DRAM
Input Buffer
4
Write Data Register
2-bit Prefetch Unit
8
32Mx4/Bank0
32Mx4/Bank2
8
32Mx4/Bank3
Mode
Register
4
Output Buffer
32Mx4/Bank1
Command
Decoder
2-bit Prefetch Unit
Bank
Control
Sense AMP
CLK
/CLK
CKE
/CS
/RAS
/CAS
/WE
DM
DS
DQ [0:3]
Row
Decoder
Column Decoder
A0~A12
BA0, BA1
DQS
Address
Buffer
Column Address
Counter
Data Strobe
Transmitter
CLK_DLL
DS
CLK
/CLK
Data Strobe
Receiver
DLL
Block
Mode
Register
Rev. 0.3/Jan. 03
6
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
FUNCTIONAL BLOCK DIAGRAM (64Mx8)
4Banks x 16Mbit x 8 I/O Double Data Rate Synchronous DRAM
Input Buffer
8
Write Data Register
2-bit Prefetch Unit
16
16Mx8/Bank0
16Mx8/Bank2
16
16Mx8/Bank3
Mode
Register
8
Output Buffer
16Mx8/Bank1
Command
Decoder
2-bit Prefetch Unit
Bank
Control
Sense AMP
CLK
/CLK
CKE
/CS
/RAS
/CAS
/WE
DM
DS
DQ [0:7]
Row
Decoder
Column Decoder
A0~A12
BA0,BA1
DQS
Address
Buffer
Column Address
Counter
CLK_DLL
DS
CLK
/CLK
Data Strobe
Transmitter
Data Strobe
Receiver
DLL
Block
Mode
Register
Rev. 0.3/Jan. 03
7
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
FUNCTIONAL BLOCK DIAGRAM (32Mx16)
4Banks x 8Mbit x 16 I/O Double Data Rate Synchronous DRAM
Input Buffer
16
Write Data Register
2-bit Prefetch Unit
32
8Mx16/Bank0
8Mx16/Bank2
32
8Mx16/Bank3
Mode
Register
16
Output Buffer
8Mx16/Bank1
Command
Decoder
2-bit Prefetch Unit
Bank
Control
Sense AMP
CLK
/CLK
CKE
/CS
/RAS
/CAS
/WE
LDM
UDM
DS
DQ[0:15]
Row
Decoder
Column Decoder
A0~A12
BA0, BA1
LDQS, UDQS
Address
Buffer
Column Address
Counter
CLK_DLL
LDQS
UDQS
CLK
/CLK
Data Strobe
Transmitter
Data Strobe
Receiver
DLL
Block
Mode
Register
Rev. 0.3/Jan. 03
8
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
SIMPLIFIED COMMAND TRUTH TABLE
A10/
AP
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
Extended Mode Register Set
H
X
L
L
L
L
OP code
1,2
Mode Register Set
H
X
L
L
L
L
OP code
1,2
H
X
X
X
H
X
X
1
L
H
H
H
Device Deselect
No Operation
Bank Active
H
X
L
L
H
H
H
X
L
H
L
H
ADDR
RA
BA
V
Read
L
CA
1
H
Write
1,3
L
X
L
H
L
L
CA
1
V
Write with Autoprecharge
H
Precharge All Banks
H
X
L
L
H
L
1
V
Read with Autoprecharge
H
Note
1,4
H
X
1,5
L
V
1
X
Precharge selected Bank
Read Burst Stop
H
X
L
H
H
L
X
1
Auto Refresh
H
H
L
L
L
H
X
1
Entry
H
L
L
L
L
H
H
X
X
X
Exit
L
H
L
H
H
H
H
X
X
X
L
H
H
H
Self Refresh
Entry
H
X
1
1
L
Precharge Power
Down Mode
1
X
Exit
Active Power
Down Mode
1
Entry
Exit
L
H
L
H
X
X
X
1
L
H
H
H
1
H
X
X
X
1
L
V
V
V
H
L
H
X
X
1
1
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )
Note :
1. LDM/UDM states are Don’t Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Register setting duing Extended MRS or MRS.
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Prechagre command.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+tRP).
4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time
(tWR) is needed to guarantee that the last data has been completely written.
5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be
precharged.
Rev. 0.3/Jan. 03
9
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
WRITE MASK TRUTH TABLE
CKEn-1
CKEn
/CS, /RAS,
/CAS, /WE
DM
Data Write
H
X
X
L
X
1
Data-In Mask
H
X
X
H
X
1
Function
ADDR
A10/
AP
BA
Note
Note :
1.
Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related
with read data. In case of x16 data I/O, LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15)
respectively.
Rev. 0.3/Jan. 03
10
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
OPERATION COMMAND TRUTH TABLE-I
Current State
IDLE
/CS
/RAS
/CAS
/WE
Address
Command
Action
H
X
X
X
X
DSEL
NOP or power down3
L
H
H
H
X
NOP
NOP or power down3
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL4
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL4
L
L
H
H
BA, RA
ACT
Row Activation
L
L
H
L
BA, AP
PRE/PALL
NOP
L
L
L
H
X
AREF/SREF
Auto Refresh or Self Refresh5
L
L
L
L
OPCODE
MRS
Mode Register Set
H
X
X
X
X
DSEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
Begin read : optional AP6
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
Begin write : optional AP6
L
L
H
H
BA, RA
ACT
ILLEGAL4
L
L
H
L
BA, AP
PRE/PALL
Precharge 7
L
L
L
H
X
AREF/SREF
ILLEGAL1 1
L
L
L
L
OPCODE
MRS
ILLEGAL1 1
H
X
X
X
X
DSEL
Continue burst to end
L
H
H
H
X
NOP
Continue burst to end
L
H
H
L
X
BST
Terminate burst
L
H
L
H
BA, CA, AP
READ/READAP
Term burst, new read:optional AP8
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL4
L
L
H
L
BA, AP
PRE/PALL
Term burst, precharge
L
L
L
H
X
AREF/SREF
ILLEGAL1 1
L
L
L
L
OPCODE
MRS
ILLEGAL1 1
H
X
X
X
X
DSEL
Continue burst to end
L
H
H
H
X
NOP
Continue burst to end
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
Term burst, new read:optional AP8
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
Term burst, new write:optional AP
ROW
ACTIVE
READ
WRITE
Rev. 0.3/Jan. 03
11
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
OPERATION COMMAND TRUTH TABLE-II
Current State
/CS
/RAS
/CAS
/WE
Address
Command
Action
L
L
H
H
BA, RA
ACT
ILLEGAL4
L
L
H
L
BA, AP
PRE/PALL
Term burst, precharge
L
L
L
H
X
AREF/SREF
ILLEGAL1 1
L
L
L
L
OPCODE
MRS
ILLEGAL1 1
H
X
X
X
X
DSEL
Continue burst to end
L
H
H
H
X
NOP
Continue burst to end
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL1 0
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL1 0
L
L
H
H
BA, RA
ACT
ILLEGAL4,10
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL4,10
L
L
L
H
X
AREF/SREF
ILLEGAL1 1
L
L
L
L
OPCODE
MRS
ILLEGAL1 1
H
X
X
X
X
DSEL
Continue burst to end
L
H
H
H
X
NOP
Continue burst to end
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL1 0
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL1 0
L
L
H
H
BA, RA
ACT
ILLEGAL4,10
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL4,10
L
L
L
H
X
AREF/SREF
ILLEGAL1 1
L
L
L
L
OPCODE
MRS
ILLEGAL1 1
H
X
X
X
X
DSEL
NOP-Enter IDLE after tRP
L
H
H
H
X
NOP
NOP-Enter IDLE after tRP
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL4,10
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL4,10
L
L
H
H
BA, RA
ACT
ILLEGAL4,10
L
L
H
L
BA, AP
PRE/PALL
NOP-Enter IDLE after tRP
L
L
L
H
X
AREF/SREF
ILLEGAL1 1
L
L
L
L
OPCODE
MRS
ILLEGAL1 1
WRITE
READ
WITH
AUTOPRECHARGE
WRITE
AUTOPRECHARGE
PRECHARGE
Rev. 0.3/Jan. 03
12
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
OPERATION COMMAND TRUTH TABLE-III
Current State
ROW
ACTIVATING
WRITE
RECOVERING
WRITE
RECOVERING WITH
AUTOPRECHARGE
REFRESHING
Rev. 0.3/Jan. 03
/CS
/RAS
/CAS
/WE
Address
Command
Action
H
X
X
X
X
DSEL
NOP - Enter ROW ACT after tRCD
L
H
H
H
X
NOP
NOP - Enter ROW ACT after tRCD
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL4,10
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL4,10
L
L
H
H
BA, RA
ACT
ILLEGAL 4,9,10
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL4,10
L
L
L
H
X
AREF/SREF
ILLEGAL1 1
L
L
L
L
OPCODE
MRS
ILLEGAL1 1
H
X
X
X
X
DSEL
NOP - Enter ROW ACT after tWR
L
H
H
H
X
NOP
NOP - Enter ROW ACT after tWR
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL4,10
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL4,11
L
L
L
H
X
AREF/SREF
ILLEGAL1 1
L
L
L
L
OPCODE
MRS
ILLEGAL1 1
H
X
X
X
X
DSEL
NOP - Enter precharge after tDPL
L
H
H
H
X
NOP
NOP - Enter precharge after tDPL
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL 4,8,10
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL4,10
L
L
H
H
BA, RA
ACT
ILLEGAL4,10
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL4,11
L
L
L
H
X
AREF/SREF
ILLEGAL1 1
L
L
L
L
OPCODE
MRS
ILLEGAL1 1
H
X
X
X
X
DSEL
NOP - Enter IDLE after tRC
L
H
H
H
X
NOP
NOP - Enter IDLE after tRC
L
H
H
L
X
BST
ILLEGAL1 1
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL1 1
13
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
OPERATION COMMAND TRUTH TABLE-IV
Current State
/CS
/RAS
/CAS
/WE
Address
Command
Action
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL1 1
L
L
H
H
BA, RA
ACT
ILLEGAL1 1
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL1 1
L
L
L
H
X
AREF/SREF
ILLEGAL1 1
L
L
L
L
OPCODE
MRS
ILLEGAL1 1
H
X
X
X
X
DSEL
NOP - Enter IDLE after tMRD
L
H
H
H
X
NOP
NOP - Enter IDLE after tMRD
L
H
H
L
X
BST
ILLEGAL1 1
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL1 1
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL1 1
L
L
H
H
BA, RA
ACT
ILLEGAL1 1
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL1 1
L
L
L
H
X
AREF/SREF
ILLEGAL1 1
L
L
L
L
OPCODE
MRS
ILLEGAL1 1
WRITE
MODE
REGISTER
ACCESSING
Note :
1. H - Logic High Level, L - Logic Low Level, X - Don’t Care, V - Valid Data Input,
BA - Bank Address, AP - AutoPrecharge Address, CA - Column Address, RA - Row Address, NOP - NO Operation.
2. All entries assume that CKE was active(high level) during the preceding clock cycle.
3. If both banks are idle and CKE is inactive(low level), then in power down mode.
4. Illegal to bank in specified state. Function may be legal in the bank indicated by Bank Address(BA) depending on the state of
that bank.
5. If both banks are idle and CKE is inactive(low level), then self refresh mode.
6. Illegal if tRCD is not met.
7. Illegal if tRAS is not met.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Illegal if tRRD is not met.
10. Illegal for single bank, but legal for other banks in multi-bank devices.
11. Illegal for all banks.
Rev. 0.3/Jan. 03
14
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
CKE FUNCTION TRUTH TABLE
Current
State
SELF
REFRESH 1
POWER
DOWN2
ALL BANKS
IDLE 4
ANY STATE
OTHER
THAN
ABOVE
CKEn1
CKEn
/CS
/RAS
/CAS
/WE
/ADD
Action
H
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
Exit self refresh, enter idle after tSREX
L
H
L
H
H
H
X
Exit self refresh, enter idle after tSREX
L
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP, continue self refresh
H
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
Exit power down, enter idle
L
H
L
H
H
H
X
Exit power down, enter idle
L
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP, continue power down mode
H
H
X
X
X
X
X
See operation command truth table
H
L
L
L
L
H
X
Enter self refresh
H
L
H
X
X
X
X
Exit power down
H
L
L
H
H
H
X
Exit power down
H
L
L
H
H
L
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
H
X
X
ILLEGAL
H
L
L
L
L
L
X
ILLEGAL
L
L
X
X
X
X
X
NOP
H
H
X
X
X
X
X
See operation command truth table
H
L
X
X
X
X
X
ILLEGAL5
L
H
X
X
X
X
X
INVALID
L
L
X
X
X
X
X
INVALID
Note :
When CKE=L, all DQ and DQS must be in Hi-Z state.
1. CKE and /CS must be kept high for a minimum of 200 stable input clocks before issuing any command.
2. All command can be stored after 2 clocks from low to high transition of CKE.
3. Illegal if CK is suspended or stopped during the power down mode.
4. Self refresh can be entered only from the all banks idle state.
5. Disabling CK may cause malfunction of any bank which is in active state.
Rev. 0.3/Jan. 03
15
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
SIMPLIFIED STATE DIAGRAM
MRS
MODE
REGISTER
SET
SREF
SELF
REFRESH
IDLE
SREX
PDEN
PDEX
AREF
ACT
POWER
DOWN
POWER
DOWN
AUTO
REFRESH
PDEN
BST
PDEX
BANK
ACTIVE
READ
WRITE
READ
WRITE
WRITEAP
WRITE
WITH
AUTOPRECHARGE
PRE(PALL)
READAP
READ
READAP
WITH
AUTOPRECHARGE WRITEAP
READ
WRITE
PRE(PALL)
PRE(PALL)
PRECHARGE
POWER-UP
Command Input
Automatic Sequence
POWER APPLIED
Rev. 0.3/Jan. 03
16
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
POWER-UP SEQUENCE AND DEVICE INITIALIZATION
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may
result in undefined operation. Power must first be applied to VDD, then to VDDQ, and finally to VREF (and to the system VTT).
VTT must be applied after VDDQ to avoid device latch-up, which may cause permanent damage to the device. VREF can be
applied anytime after VDDQ, but is expected to be nominally coincident with VTT. Except for CKE, inputs are not recognized as
valid until after VREF is applied. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after VDD is applied. Maintaining an LVCMOS LOW level on CKE during power-up is required to guarantee that the DQ and DQS outputs will be in the
High-Z state, where they will remain until driven in normal operation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200us delay prior to applying an executable command.
Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be brought HIGH.
Following the NOP command, a PRECHARGE ALL command should be applied. Next a EXTENDED MODE REGISTER SET
command should be issued for the Extended Mode Register, to enable the DLL, then a MODE REGISTER SET command should
be issued for the Mode Register, to reset the DLL, and to program the operating parameters. 200 clock cycles are required between
the DLL reset and any command. During the 200 cycles of CK, for DLL locking, executable commands are disallowed (a DESELECT or NOP command must be applied). After the 200 clock cycles, a PRECHARGE ALL command should be applied, placing
the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a MODE REGISTER SET command for the
Mode Register, with the reset DLL bit deactivated (i.e. to program operating parameters without resetting the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation.
1.
Apply power - VDD, VDDQ, VTT, VREF in the following power up sequencing and attempt to maintain CKE at LVCMOS
low state. (All the other input pins may be undefined.)
• VDD and VDDQ are driven from a single power converter output.
• VTT is limited to 1.44V (reflecting VDDQ(max)/2 + 50mV VREF variation + 40mV VTT variation.
• VREF tracks VDDQ/2.
• A minimum resistance of 42 Ohms (22 ohm series resistor + 22 ohm parallel resistor - 5% tolerance) limits the input current from the VTT supply into any pin.
• If the above criteria cannot be met by the system design, then the following sequencing and voltage relationship must be
adhered to during power up.
Voltage description
Sequencing
Voltage relationship to avoid latch-up
VDDQ
After or with VDD
< VDD + 0.3V
VTT
After or with VDDQ
< VDDQ + 0.3V
VREF
After or with VDDQ
< VDDQ + 0.3V
2.
Start clock and maintain stable clock for a minimum of 200usec.
3.
After stable power and clock, apply NOP condition and take CKE high.
4.
Issue Extended Mode Register Set (EMRS) to enable DLL.
5.
Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=high. (An additional 200 cycles of clock
are required for locking DLL)
6.
Issue Precharge commands for all banks of the device.
Rev. 0.3/Jan. 03
17
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
7.
Issue 2 or more Auto Refresh commands.
8.
Issue a Mode Register Set command to initialize the mode register with bit A8 = Low
Power-Up Sequence
VDD
VDDQ
tVTD
VTT
VREF
BA0,BA1
CODE
T=200usec
Power up
VDD and CK stable
CODE
CODE
CODE
≈ ≈
DQ’s
CODE
≈ ≈
DQS
CODE
MRS
tRP
tMRD
EMRS Set
Precharge All
MRS Set
Reset DLL
(with A8=H)
≈ ≈
A10
EMRS
≈ ≈ ≈ ≈ ≈ ≈ ≈
ADDR
PRE
≈ ≈
DM
NOP
≈ ≈ ≈ ≈ ≈ ≈ ≈
CMD
≈≈ ≈ ≈ ≈ ≈
CKE
≈ ≈
tIS tIH
≈ ≈ ≈ ≈ ≈ ≈ ≈
CLK
≈ ≈ ≈ ≈ ≈ ≈ ≈
≈
/CLK
200 cycles of CK*
tRP
NOP
PRE
AREF
Precharge All
MRS
CODE
CODE
CODE
tRFC
2 or more
Auto Refresh
MRS Set
(with A8=L)
*200 cycles of CK are required (for DLL locking) before any executable command can be applied.
Rev. 0.3/Jan. 03
18
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
MODE REGISTER SET (MRS)
The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length, burst type,
test mode, DLL reset. The mode register is programed via MRS command. This command is issued by the low signals of /RAS, /
CAS, /CS, /WE and BA0. This command can be issued only when all banks are in idle state and CKE must be high at least one
cycle before the Mode Register Set Command can be issued. Two cycles are required to write the data in mode register. During the
MRS cycle, any command cannot be issued. Once mode register field is determined, the information will be held until resetted by
another MRS command.
BA1
BA0
0
0
A12
A11
A10
A9
RFU
A8
A7
DR
TM
A6
A5
A4
CAS Latency
BA0
MRS Type
A8
DLL Reset
A7
Test Mode
0
MRS
0
No
0
Normal
1
EMRS
1
Yes
1
Test
A3
A2
BT
A1
A0
Burst Length
Burst Length
A2
Rev. 0.3/Jan. 03
A1
A0
Sequential
Interleave
A6
A5
A4
CAS Latency
0
0
0
Reserved
Reserved
0
0
0
Reserved
0
0
1
2
2
0
0
1
Reserved
0
1
0
4
4
0
1
0
2
0
1
1
8
8
0
1
1
3
1
0
0
Reserved
Reserved
1
0
0
Reserved
1
0
1
Reserved
Reserved
1
0
1
Reserved
1
1
0
Reserved
Reserved
1
1
0
2.5
1
1
1
Reserved
Reserved
1
1
1
Reserved
A3
Burst Type
0
Sequential
1
Interleave
19
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
BURST DEFINITION
Burst Length
Starting Address (A2,A1,A0)
Sequential
Interleave
XX0
0, 1
0, 1
XX1
1, 0
1, 0
X00
0, 1, 2, 3
0, 1, 2, 3
X01
1, 2, 3, 0
1, 0, 3, 2
X10
2, 3, 0, 1
2, 3, 0, 1
X11
3, 0, 1, 2
3, 2, 1, 0
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
011
3, 4, 5, 6, 7, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1
111
0, 1, 2, 3, 4, 5, 6, 7
7, 6, 5, 4, 3, 2, 1, 0
2
4
8
BURST LENGTH & TYPE
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column locations that can be accessed for a given Read or Write command. Burst lengths of 2, 4 or
8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown
operation or incompatibility with future versions may result.
When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that
burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. The block is uniquely
selected by A1-Ai when the burst length is set to two, by A2 -Ai when the burst length is set to four and by A3 -Ai when the burst
length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both Read
and Write bursts.
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is
selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column
address, as shown in Burst Definitionon Table
Rev. 0.3/Jan. 03
20
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
CAS LATENCY
The Read latency or CAS latency is the delay in clock cycles between the registration of a Read command and the availability of
the first burst of output data. The latency can be programmed 2 or 2.5 clocks.
If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with clock
edge n + m.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
DLL RESET
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically disabled when
entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled,
200 clock cycles must occur to allow time for the internal clock to lock to the externally applied clock before an any command can
be issued.
OUTPUT DRIVER IMPEDANCE CONTROL
The normal drive strength for all outputs is specified to be SSTL_2, Class II. Hynix also supports a half strength driver option,
intended for lighter load and/or point-to-point environments. Selection of the half strength driver option will reduce the output
drive strength by 50% of that of the full strength driver. I-V curves for both the full strength driver and the half strength driver are
included in this document.
Rev. 0.3/Jan. 03
21
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
EXTENDED MODE REGISTER SET (EMRS)
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include
DLL enable/disable, output driver strength selection(optional). These functions are controlled via the bits shown below. The
Extended Mode Register is programmed via the Mode Register Set command ( BA0=1 and BA1=0) and will retain the stored
information until it is programmed again or the device loses power.
The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the
specified time before initiating any subsequent operation. Violating either of these requirements will result in unspecified operation.
BA1
BA0
0
1
A12
A11
A10
A9
A8
A7
RFU*
BA0
MRS Type
0
MRS
1
EMRS
A6
A5
A4
A3
A2
A1
A0
0**
DS
DLL
A0
DLL enable
0
Enable
1
Diable
A1
Output Driver Impedance Control
0
Full Strength Driver
1
Half Strength Driver
* All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage
** This part do not support /QFC function, A2 must be programmed to Zero.
Rev. 0.3/Jan. 03
22
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Ambient Temperature
TA
0 ~ 70
Storage Temperature
TSTG
-55 ~ 125
oC
V IN, VOUT
-0.5 ~ 3.6
V
Voltage on V DD relative to V SS
V DD
-0.5 ~ 3.6
V
Voltage on V DDQ relative to VSS
V DDQ
-0.5 ~ 3.6
V
Output Short Circuit Current
I OS
50
mA
Power Dissipation
PD
1
W
TSOLDER
260 ⋅ 10
Voltage on Any Pin relative to V SS
Soldering Temperature ⋅ Time
Unit
o
C
oC
⋅ sec
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS (TA=0 to 70 o C, Voltage referenced to VS S = 0V)
Parameter
Symbol
Min
Typ.
Max
Unit
Power Supply Voltage
VDD
2.3
2.5
2.7
V
Power Supply Voltage
V DDQ
2.3
2.5
2.7
V
Input High Voltage
V IH
VREF + 0.15
-
V DDQ + 0.3
V
Input Low Voltage
V IL
-0.3
-
V REF - 0.15
V
Termination Voltage
VTT
VREF - 0.04
V REF
VREF + 0.04
V
Reference Voltage
VREF
0.49*VDDQ
0.5*VDDQ
0.51*VDDQ
V
Note
1
2
3
Note :
1. V DDQ must not exceed the level of V DD .
2. V IL (min) is acceptable -1.5V AC pulse width with < 5ns of duration.
3. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of the same.
Peak to peak noise on VREF may not exceed +/- 2% of the DC value.
DC CHARACTERISTICS I
Parameter
(TA=0 to 70°C , Voltage referenced to VSS = 0V)
Symbol
Min.
Max
Unit
Note
Input Leakage Current
I LI
-2
2
uA
1
Output Leakage Current
I LO
-5
5
uA
2
Output High Voltage
VOH
V TT + 0.76
-
V
IOH = -15.2mA
Output Low Voltage
V OL
-
VTT - 0.76
V
IOL = +15.2mA
Note : 1. VIN = 0 to 3.6V, All other pins are not tested under VIN =0V. 2. DOUT is disabled, VOUT=0 to 2.7V
Rev. 0.3/Jan. 03
23
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
DC CHARACTERISTICS II (TA=0 to 70 °C, Voltage referenced to V SS = 0V)
128Mx4
Speed
Parameter
Symbol
Test Condition
Unit Note
-D43
-J
-M
-K
-H
150
140
130
120
120
mA
Operating Current
IDD0
One bank; Active - Precharge ; tRC=tRC(min);
tCK=tCK(min) ; DQ,DM and DQS inputs changing twice
per clock cycle; address and control inputs changing once
per clock cycle
Operating Current
I DD1
One bank; Active - Read - Precharge;
Burst Length=2; tRC=tRC(min); tCK=tCK(min); address
and control inputs changing once per clock cycle
200
180
160
150
150
mA
Precharge Power
Down Standby Current
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
10
10
10
10
10
mA
Idle Standby Current
IDD2N
Vin>=Vih(min) or Vin=<Vil(max) for DQ, DQS and DM
35
mA
Idle Standby Current
IDD2F
/CS=High, All banks idle; tCK=tCK(min);
CKE=High; address and control inputs changing once per
clock cycle.
VIN=VREF for DQ, DQS and DM
35
mA
Idle Quiet Standby
Current
IDD2Q
/CS>=Vih(min); All banks idle; CKE>=Vih(min);
Addresses and other control inputs stable, Vin=Vref for DQ,
DQS and DM
25
mA
Active Power Down
Standby Current
IDD3P
One bank active; Power down mode; CKE=Low,
tCK=tCK(min)
12
mA
Active Standby
Current
IDD3N
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
tRC=tRAS(max); tCK=tCK(min);
DQ, DM and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per clock
cycle
50
45
40
40
40
Operating Current
I DD4R
Burst=2; Reads; Continuous burst; One bank active; Address
and control inputs changing once per clock cycle;
tCK=tCK(min); IOUT=0mA
270
240
200
200
200
IDD4W
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock cycle;
tCK=tCK(min); DQ, DM and DQS inputs changing twice
per clock cycle
270
240
200
200
200
Auto Refresh Current
I DD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK
for DDR266A & DDR266B at 133Mhz; distributed refresh
300
280
260
260
260
Self Refresh Current
I DD6
CKE =< 0.2V; External clock on;
tCK=tCK(min)
Operating Current
mA
mA
Normal
5
mA
Low Power
2.5
mA
Operating Current Four Bank Operation
I DD7
Four bank interleaving with BL=4, Refer to the following
page for detailed test condition
540
460
380
380
380
mA
Random Read Current
IDD7A
4banks active read with activate every 20ns, AP(Auto
Precharge) read every 20ns, BL=4, tRCD=3, IOUT=0 mA,
100% DQ, DM and DQS inputs changing twice per clock
cycle; 100% addresses changing once per clock cycle
540
460
380
380
380
mA
Rev. 0.3/Jan. 03
24
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
DC CHARACTERISTICS II (TA=0 to 70 °C, Voltage referenced to V SS = 0V)
64Mx8
Speed
Parameter
Symbol
Test Condition
Unit Note
-D43
-J
-M
-K
-H
150
140
130
120
120
mA
Operating Current
IDD0
One bank; Active - Precharge ; tRC=tRC(min);
tCK=tCK(min) ; DQ,DM and DQS inputs changing twice
per clock cycle; address and control inputs changing once
per clock cycle
Operating Current
I DD1
One bank; Active - Read - Precharge;
Burst Length=2; tRC=tRC(min); tCK=tCK(min); address
and control inputs changing once per clock cycle
200
180
160
150
150
mA
Precharge Power
Down Standby Current
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
10
10
10
10
10
mA
Idle Standby Current
IDD2N
Vin>=Vih(min) or Vin=<Vil(max) for DQ, DQS and DM
35
mA
Idle Standby Current
IDD2F
/CS=High, All banks idle; tCK=tCK(min);
CKE=High; address and control inputs changing once per
clock cycle.
VIN=VREF for DQ, DQS and DM
35
mA
Idle Quiet Standby
Current
IDD2Q
/CS>=Vih(min); All banks idle; CKE>=Vih(min);
Addresses and other control inputs stable, Vin=Vref for DQ,
DQS and DM
25
mA
Active Power Down
Standby Current
IDD3P
One bank active; Power down mode; CKE=Low,
tCK=tCK(min)
12
mA
Active Standby
Current
IDD3N
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
tRC=tRAS(max); tCK=tCK(min);
DQ, DM and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per clock
cycle
50
45
40
40
40
Operating Current
I DD4R
Burst=2; Reads; Continuous burst; One bank active; Address
and control inputs changing once per clock cycle;
tCK=tCK(min); IOUT=0mA
280
250
210
210
210
IDD4W
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock cycle;
tCK=tCK(min); DQ, DM and DQS inputs changing twice
per clock cycle
280
250
210
210
210
Auto Refresh Current
I DD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK
for DDR266A & DDR266B at 133Mhz; distributed refresh
300
280
260
260
260
Self Refresh Current
I DD6
CKE =< 0.2V; External clock on;
tCK=tCK(min)
Operating Current
Operating Current Four Bank Operation
Random Read Current
Rev. 0.3/Jan. 03
mA
mA
Normal
5
mA
Low Power
2.5
mA
I DD7
Four bank interleaving with BL=4, Refer to the following
page for detailed test condition
540
460
380
380
380
mA
IDD7A
4banks active read with activate every 20ns, AP(Auto
Precharge) read every 20ns, BL=4, tRCD=3, IOUT=0 mA,
100% DQ, DM and DQS inputs changing twice per clock
cycle; 100% addresses changing once per clock cycle
540
460
380
380
380
mA
25
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
DC CHARACTERISTICS II (TA=0 to 70 °C, Voltage referenced to V SS = 0V)
32Mx16
Speed
Parameter
Symbol
Test Condition
Unit Note
-D43
-J
-M
-K
-H
150
140
130
120
120
mA
Operating Current
IDD0
One bank; Active - Precharge ; tRC=tRC(min);
tCK=tCK(min) ; DQ,DM and DQS inputs changing twice
per clock cycle; address and control inputs changing once
per clock cycle
Operating Current
I DD1
One bank; Active - Read - Precharge;
Burst Length=2; tRC=tRC(min); tCK=tCK(min); address
and control inputs changing once per clock cycle
200
180
160
150
150
mA
Precharge Power
Down Standby Current
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
10
10
10
10
10
mA
Idle Standby Current
IDD2N
Vin>=Vih(min) or Vin=<Vil(max) for DQ, DQS and DM
35
mA
Idle Standby Current
IDD2F
/CS=High, All banks idle; tCK=tCK(min);
CKE=High; address and control inputs changing once per
clock cycle.
VIN=VREF for DQ, DQS and DM
35
mA
Idle Quiet Standby
Current
IDD2Q
/CS>=Vih(min); All banks idle; CKE>=Vih(min);
Addresses and other control inputs stable, Vin=Vref for DQ,
DQS and DM
25
mA
Active Power Down
Standby Current
IDD3P
One bank active; Power down mode; CKE=Low,
tCK=tCK(min)
12
mA
Active Standby
Current
IDD3N
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
tRC=tRAS(max); tCK=tCK(min);
DQ, DM and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per clock
cycle
50
45
40
40
40
Operating Current
I DD4R
Burst=2; Reads; Continuous burst; One bank active; Address
and control inputs changing once per clock cycle;
tCK=tCK(min); IOUT=0mA
280
250
210
210
210
IDD4W
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock cycle;
tCK=tCK(min); DQ, DM and DQS inputs changing twice
per clock cycle
280
250
220
220
220
Auto Refresh Current
I DD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK
for DDR266A & DDR266B at 133Mhz; distributed refresh
300
280
260
260
260
Self Refresh Current
I DD6
CKE =< 0.2V; External clock on;
tCK=tCK(min)
Operating Current
Operating Current Four Bank Operation
Random Read Current
Rev. 0.3/Jan. 03
mA
mA
Normal
5
mA
Low Power
2.5
mA
I DD7
Four bank interleaving with BL=4, Refer to the following
page for detailed test condition
540
460
380
380
380
mA
IDD7A
4banks active read with activate every 20ns, AP(Auto
Precharge) read every 20ns, BL=4, tRCD=3, IOUT=0 mA,
100% DQ, DM and DQS inputs changing twice per clock
cycle; 100% addresses changing once per clock cycle
540
460
380
380
380
mA
26
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7
IDD1 : Operating current: One bank operation
1. Typical Case : VDD = 2.5V, T=25 oC
2. Worst Case : VDD = 2.7V, T= 10 oC
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are
changing once per clock cycle. lout = 0mA
4. Timing patterns
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
50% of data changing at every burst
- DDR333(166Mhz, CL=2.5) : tCK = 6ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 10*tCK, tRAS = 7*tCK
Read : A0 N N R0 N N N P0 N N A0 N - repeat the same timing with random address changing
50% of data changing at every burst
- DDR400(200Mhz, CL=3) : tCK = 5ns, CL = 2, BL = 4, tRCD = 3*tCK, tRC = 11*tCK, tRAS = 8*tCK
Read : A0 N N R0 N N N P0 N N A0 N - repeat the same timing with random add
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
IDD7 : Operating current: Four bank operation
1. Typical Case : VDD = 2.5V, T=25 oC
2. Worst Case : VDD = 2.7V, T= 10 oC
3. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not
changing. lout = 0mA
4. Timing patterns
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
- DDR333(166Mhz, CL=2.5) : tCK = 6ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
- DDR400(200Mhz, CL=3) : tCK = 5ns, CL = 2, BL = 4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Rev. 0.3/Jan. 03
27
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
AC OPERATING CONDITIONS (TA=0 to 70 o C, Voltage referenced to VS S = 0V)
Parameter
Symbol
Min
Max
Input High (Logic 1) Voltage, DQ, DQS and DM signals
V IH(AC)
V REF + 0.31
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
VIL(AC)
Input Differential Voltage, CK and /CK inputs
V ID(AC)
Input Crossing Point Voltage, CK and /CK inputs
V IX(AC)
Unit
Note
V
V REF - 0.31
V
0.7
V DDQ + 0.6
V
1
0.5*VDDQ -0.2
0.5*VDDQ+0.2
V
2
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
AC OPERATING TEST CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
Parameter
Value
Unit
Reference Voltage
V DDQ x 0.5
V
Termination Voltage
V DDQ x 0.5
V
AC Input High Level Voltage (V I H, min)
V REF + 0.31
V
AC Input Low Level Voltage (V IL, max)
V REF - 0.31
V
Input Timing Measurement Reference Level Voltage
V REF
V
Output Timing Measurement Reference Level Voltage
VTT
V
Input Signal maximum peak swing
1.5
V
Input minimum Signal Slew Rate
1
V/ns
Termination Resistor (R T )
50
Ω
Series Resistor (R S )
25
Ω
Output Load Capacitance for Access Time Measurement (C L)
30
pF
Rev. 0.3/Jan. 03
28
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
AC CHARACTERISTICS
Parameter
(AC operating conditions unless otherwise noted)
-J
-D43
Symbol
-M
-K
-H
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Row Cycle Time
tRC
TBD
-
60
-
60
-
65
-
65
-
ns
Auto Refresh Row Cycle
Time
tRFC
TBD
-
72
-
75
-
75
-
75
-
ns
Row Active Time
tRAS
TBD
TBD
42
70K
45
120K
45
120K
45
120K
ns
-
tRCD or
tRPmin
-
tRCD or
tRPmin
-
tRCD or
tRPmin
-
ns
Active to Read with Auto
Precharge Delay
tRAP
TBD
-
tRCD or
tRPmin
Row Address to Column
Address Delay
tRCD
TBD
-
18
-
15
-
20
-
20
-
ns
Row Active to Row
Active Delay
tRRD
TBD
-
12
-
15
-
15
-
15
-
ns
Column Address to
Column Address Delay
tCCD
TBD
-
1
-
1
-
1
-
1
-
CK
Row Precharge Time
tRP
TBD
-
18
-
15
-
20
-
20
-
ns
Write Recovery Time
tWR
TBD
-
15
-
15
-
15
-
15
-
ns
Write to Read Command
Delay
tWTR
TBD
-
1
-
1
-
1
-
1
-
CK
Auto Precharge Write
Recovery + Precharge
Time
tDAL
TBD
-
2+
(tRP/
tCK)
-
2+
(tRP/
tCK)
-
5
-
5
-
CK
TBD
TBD
6
12
7.5
12
7.5
12
7.5
12
ns
TBD
TBD
7.5
12
7.5
12
7.5
12
10
12
ns
System Clock
Cycle Time
CL = 2.5
CL = 2
tCK
Note
16
15
Clock High Level Width
tCH
TBD
TBD
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
CK
Clock Low Level Width
tCL
TBD
TBD
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
CK
Data-Out edge to Clock
edge Skew
tAC
TBD
TBD
-0.7
0.7
-0.75
0.75
-0.75
0.75
-0.75
0.75
ns
DQS-Out edge to Clock
edge Skew
tDQSCK
TBD
TBD
-0.6
0.6
-0.75
0.75
-0.75
0.75
-0.75
0.75
ns
DQS-Out edge to DataOut edge Skew
tDQSQ
TBD
TBD
-
0.45
-
0.5
-
0.5
-
0.5
ns
Data-Out hold time from
DQS
tQH
TBD
-
tHP
-t QHS
-
t HP
-tQHS
-
tHPmin
-t QHS
-
tHPmin
-t QHS
-
ns
1, 10
Clock Half Period
tHP
TBD
-
min
(tCL,tC
H)
-
min
(tCL,tC
H)
-
tCH/L
min
-
tCH/L
min
-
ns
1,9
Data Hold Skew Factor
tQHS
TBD
TBD
-
0.55
-
0.75
-
0.75
-
0.75
ns
10
Valid Data Output
Window
tDV
TBD
Data-out high-impedance
window from CK, /CK
tHZ
TBD
TBD
-0.7
0.7
-0.75
0.75
-0.75
0.75
-0.75
0.75
ns
Data-out low-impedance
window from CK, /CK
tLZ
TBD
TBD
-0.7
0.7
-0.75
0.75
-0.75
0.75
-0.75
0.75
ns
Input Setup Time (fast
slew rate)
tIS
TBD
-
0.75
-
0.9
-
0.9
-
0.9
-
ns
Rev. 0.3/Jan. 03
tQH-t DQSQ
tQH-t DQSQ
tQH -t DQSQ
tQH-t DQSQ
ns
2,3,5,6
29
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
Parameter
-J
-D43
Symbol
-M
-K
-H
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Note
Input Hold Time (fast slew
rate)
tIH
TBD
-
0.75
-
0.9
-
0.9
-
0.9
-
ns
2,3,5,6
Input Setup Time (slow
slew rate)
tIS
TBD
-
0.8
-
1.0
-
1.0
-
1.0
-
ns
2,4,5,6
Input Hold Time (slow
slew rate)
tIH
TBD
-
0.8
-
1.0
-
1.0
-
1.0
-
ns
2,4,5,6
Input Pulse Width
2.2
-
2.2
-
2.2
ns
6
tIPW
TBD
Write DQS High Level
Width
2.2
tDQSH
TBD
-
0.35
-
0.35
-
0.35
-
0.35
-
CK
Write DQS Low Level
Width
tDQSL
TBD
-
0.35
-
0.35
-
0.35
-
0.35
-
CK
Clock to First Rising edge
tDQSS
of DQS-In
TBD
TBD
0.75
1.25
0.72
1.28
0.75
1.25
0.75
1.25
CK
Data-In Setup Time to
DQS-In (DQ & DM)
tDS
TBD
-
0.45
-
0.5
-
0.5
-
0.5
-
ns
6,7,
11~13
Data-in Hold Time to
DQS-In (DQ & DM)
tDH
TBD
-
0.45
-
0.5
-
0.5
-
0.5
-
ns
6,7,
11~13
DQ & DM Input Pulse
Width
tDIPW
TBD
-
1.75
-
1.75
-
1.75
-
1.75
-
ns
Read DQS Preamble Time tRPRE
TBD
TBD
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
CK
Read DQS Postamble
Time
tRPST
TBD
TBD
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
CK
Write DQS Preamble
Setup Time
tWPRES
TBD
-
0
-
0
-
0
-
0
-
CK
Write DQS Preamble Hold tWPRE
Time
H
TBD
-
0.25
-
0.25
-
0.25
-
0.25
-
CK
Write DQS Postamble
Time
tWPST
TBD
TBD
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
CK
Mode Register Set Delay
tMRD
TBD
-
2
-
2
-
2
-
2
-
CK
Exit Self Refresh to Any
Execute Command
tXSC
TBD
-
200
-
200
-
200
-
200
-
CK
Average Periodic Refresh
Interval
tREFI
-
TBD
-
7.8
-
7.8
-
7.8
-
7.8
us
8
Note :
1.
This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2.
Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3.
For command/address input slew rate >=1.0V/ns
4.
For command/address input slew rate >=0.5V/ns and <1.0V/ns
This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
Input Setup / Hold Slew-rate
Delta tIS
Delta tIH
V/ns
ps
ps
0.5
0
0
0.4
+50
0
Rev. 0.3/Jan. 03
30
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
0.3
+100
0
5.
CK, /CK slew rates are >=1.0V/ns
6.
These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by
tester correlation.
7.
Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.
8.
Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete S elf
Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
9.
Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for tCL and tCH).
10.
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of tDQSQmax,
the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects and p-channel to n-channe l variation of
the output drivers.
11.
This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
12.
Input Setup / Hold Slew-rate
Delta tDS
Delta tDH
V/ns
ps
ps
0.5
0
0
0.4
+75
+75
0.3
+150
+150
design or
I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is flat below VRE F +/-310mV
for a duration of up to 2ns.
I/O Input Level
13.
Delta tDS
Delta tDH
mV
ps
ps
+280
+50
+50
I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where the DQ and DQS slew rates
differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example, if slew rate 1 = 0.5V/ns and Slew Rate2 =
0.4V/n then the Delta Inverse Slew Rate = -0.5ns/V.
(1/SlewRate1)-(1/SlewRate2)
Delta tDS
Delta tDH
ns/V
ps
ps
0
0
0
+/-0.25
+50
+50
+/- 0.5
+100
+100
14.
DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions
through the DC region must be monotonic.
15.
tDAL = 2 clocks + (tRP / tCK ). For each of the terms above, if not already an integer, round to the next highest integer.
tCK is equal to the actual system clock cycle time.
Example: For DDR266B at CL=2.5 and tCK = 7.5 ns,
tDAL = (15 ns / 7.5 ns) + (20 ns / 7.5 ns) = (2.00) + (2.67)
Round up each non-integer to the next highest integer: = (2) + (3), tDAL = 5 clocks
16. For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be tRAS - BL/2 x tC K.
Rev. 0.3/Jan. 03
31
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
CAPACITANCE
(TA =25 oC, f=100MHz )
Parameter
Pin
Symbol
Min
Max
Unit
Input Clock Capacitance
CK, /CK
C I1
2.0
3.0
pF
Delta Input Clock Capacitance
CK, /CK
Delta CI1
-
0.25
pF
Input Capacitance
All other input-only pins
C I1
2.0
3.0
pF
Delta Input Capacitance
All other input-only pins
Delta CI2
-
0.5
pF
Input / Output Capacitanc
DQ, DQS, DM
C IO
4.0
5.0
pF
Delta Input / Output Capacitance
DQ, DQS, DM
Delta CIO
-
0.5
pF
Note :
1. VDD = min. to max., VDDQ = 2.3V to 2.7V, V ODC = VDDQ/2, V Opeak-to-peak = 0.2V
2. Pins not under test are tied to GND.
3. These values are guaranteed by design and are tested on a sample basis only.
OUTPUT LOAD CIRCUIT
V TT
R T=50Ω
Output
Z o=50Ω
V REF
CL =30pF
Rev. 0.3/Jan. 03
32
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
OUTPUT DRIVE CHARACTERISTICS (FULL STRENGTH DRIVER)
Pull Down Current (mA)
Voltage
Pull Up Current (mA)
Nominal
Low
Nominal
High
Minimum
Maximum
Nominal
Low
Nominal
High
Minimum
Maximum
0.1
6.0
6.8
4.6
9.6
-6.1
-7.6
-4.6
-10
0.2
12.2
13.5
9.2
18.2
-12.2
-14.5
-9.2
-20
0.3
18.1
20.1
13.8
26.0
-18.1
-21.2
-13.8
-29.8
0.4
24.1
26.6
18.4
33.9
-24.0
-27.7
-18.4
-38.8
0.5
29.8
33.0
23.0
41.8
-29.8
-34.1
-23.0
-46.8
0.6
34.6
39.1
27.7
49.4
-34.3
-40.5
-27.7
-54.4
0.7
39.4
44.2
32.2
56.8
-38.1
-46.9
-32.2
-61.8
0.8
43.7
49.8
36.8
63.2
-41.1
-53.1
-36.0
-69.5
0.9
47.5
55.2
39.6
69.9
-43.8
-59.4
-38.2
-77.3
1.0
51.3
60.3
42.6
76.3
-46.0
-65.5
-38.7
-85.2
1.1
54.1
65.2
44.8
82.5
-47.8
-71.6
-39.0
-93.0
1.2
56.2
69.9
46.2
88.3
-49.2
-77.6
-39.2
-100.6
1.3
57.9
74.2
47.1
93.8
-50.0
-83.6
-39.4
-108.1
1.4
59.3
78.4
47.4
99.1
-50.5
-89.7
-39.6
-115.5
1.5
60.1
82.3
47.7
103.8
-50.7
-95.5
-39.9
-123.0
1.6
60.5
85.9
48.0
108.4
-51.0
-101.3
-40.1
-130.4
1.7
61.0
89.1
48.4
112.1
-51.1
-107.1
-40.2
-136.7
1.8
61.5
92.2
48.9
115.9
-51.3
-112.4
-40.3
-144.2
1.9
62.0
95.3
49.1
119.6
-51.5
-118.7
-40.4
-150.5
2.0
62.5
97.2
49.4
123.3
-51.6
-124.0
-40.5
-156.9
2.1
62.8
99.1
49.6
126.5
-51.8
-129.3
-40.6
-163.2
2.2
63.3
100.9
49.8
129.5
-52.0
-134.6
-40.7
-169.6
2.3
63.8
101.9
49.9
132.4
-52.2
-139.9
-40.8
-176.0
2.4
64.1
102.8
50.0
135.0
-52.3
-145.2
-40.9
-181.3
2.5
64.6
103.8
50.2
137.3
-52.5
-150.5
-41.0
-187.6
2.6
64.8
104.6
50.4
139.2
-52.7
-155.3
-41.1
-192.9
2.7
65.0
105.4
50.5
140.8
-52.8
-160.1
-41.2
-198.2
Evaluation conditions:
Typical 25 oC (TAmbient), VDDQ=2.5V, typical process
Minimum 70 o C (TAmbient), VDDQ=2.3V, slow slow process
Maximum 0 o C (TAmbient), VDDQ=2.7V, fast fast process
Rev. 0.3/Jan. 03
33
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
OUTPUT DRIVE CHARACTERISTICS (FULL STRENGTH DRIVER )
Pull Down Characteristics
Iout (mA)
160
Maximum
140
120
Nominal High
100
80
Nominal Low
60
40
Minimum
20
0
0
0.5
1
1.5
2
2.5
2
2.5
Vout to VSSQ (V)
Pull Up Characteristics
Iout (mA)
0
0.5
1
1.5
0
-20
Minimum
-40
-60
Nominal Low
-80
-100
-120
Nominal High
-140
-160
-180
Maximum
-200
-220
VDDQ to Vout (V)
Rev. 0.3/Jan. 03
34
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
OUTPUT DRIVE CHARACTERISTICS (HALF STRENGTH DRIVER)
Pull Down Current (mA)
Voltage
Pull Up Current (mA)
Nominal
Low
Nominal
High
Minimum
Maximum
Nominal
Low
Nominal
High
Minimum
Maximum
0.1
3.4
3.8
2.6
5.0
-3.5
-4.3
-2.6
-5.0
0.2
6.9
7.6
5.2
9.9
-6.9
-7.8
-5.2
-9.9
0.3
10.3
11.4
7.8
14.6
-10.3
-12.0
-7.8
-14.6
0.4
13.6
15.1
10.4
19.2
-13.6
-15.7
-10.4
-19.2
0.5
16.9
18.7
13.0
23.6
-16.9
-19.3
-13.0
-23.6
0.6
19.9
22.1
15.7
28.0
-19.4
-22.9
-15.7
-28.0
0.7
22.3
25.0
18.2
32.2
-21.5
-26.5
-18.2
-32.2
0.8
24.7
28.2
20.8
35.8
-23.3
-30.1
-20.4
-35.8
0.9
26.9
31.3
22.4
39.5
-24.8
-33.6
-21.6
-39.5
1.0
29.0
34.1
24.1
43.2
-26.0
-37.1
-21.9
-43.2
1.1
30.6
36.9
25.4
46.7
-27.1
-40.3
-22.1
-46.7
1.2
31.8
39.5
26.2
50.0
-27.8
-43.1
-22.2
-50.0
1.3
32.8
42.0
26.6
53.1
-28.3
-45.8
-22.3
-53.1
1.4
33.5
44.4
26.8
56.1
-28.6
-48.4
-22.4
-56.1
1.5
34.0
46.6
27.0
58.7
-28.7
-50.7
-22.6
-58.7
1.6
34.3
48.6
27.2
61.4
-28.9
-52.9
-22.7
-61.4
1.7
34.5
50.5
27.4
63.5
-28.9
-55.0
-22.7
-63.5
1.8
34.8
52.2
27.7
65.6
-29.0
-56.8
-22.8
-65.6
1.9
35.1
53.9
27.8
67.7
-29.2
-58.7
-22.9
-67.7
2.0
35.4
55.0
28.0
69.8
-29.2
-60.0
-22.9
-69.8
2.1
35.6
56.1
28.1
71.6
-29.3
-61.2
-23.0
-71.6
2.2
35.8
57.1
28.2
73.3
-29.5
-62.4
-23.0
-73.3
2.3
36.1
57.7
28.3
74.9
-29.5
-63.1
-23.1
-74.9
2.4
36.3
58.2
28.3
76.4
-29.6
-63.8
-23.2
-76.4
2.5
36.5
58.7
28.4
77.7
-29.7
-64.4
-23.2
-77.7
2.6
36.7
59.2
28.5
78.8
-29.8
-65.1
-23.3
-78.8
2.7
36.8
59.6
28.6
79.7
-29.9
-65.8
-23.3
-79.7
Evaluation conditions:
Typical 25 oC (TAmbient), VDDQ=2.5V, typical process
Minimum 70 o C (TAmbient), VDDQ=2.3V, slow slow process
Maximum 0 o C (TAmbient), VDDQ=2.7V, fast fast process
Rev. 0.3/Jan. 03
35
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
OUTPUT DRIVE CHARACTERISTICS (HALF STRENGTH DRIVER)
Pull Down Characteristics
Iout (mA)
100
Maximum
80
Nominal High
60
40
Nominal Low
20
Minimum
0
0
0.5
1
1.5
2
2.5
2
2.5
Vout to VSSQ (V)
Pull Up Characteristics
Iout (mA)
0
0.5
1
1.5
0
Minimum
-20
Nominal Low
-40
Nominal High
-60
-80
Maximum
-100
VDDQ to Vout (V)
Rev. 0.3/Jan. 03
36
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
PACKAGE INFORMATION
400mil 66pin Thin Small Outline Package
Unit : mm(Inch)
11.94 (0.470)
11.79 (0.462)
10.26 (0.404)
10.05 (0.396)
BASE PLANE
22.33 (0.879)
22.12 (0.871)
0.65 (0.0256) BSC
1.194 (0.0470)
0.991 (0.0390)
Rev. 0.3/Jan. 03
0.35 (0.0138)
0.25 (0.0098)
0 ~ 5 Deg.
SEATING PLANE
0.15 (0.0059)
0.05 (0.0020)
0.597 (0.0235)
0.406 (0.0160)
0.210 (0.0083)
0.120 (0.0047)
37