HY5DU564022 4 Banks x 16M x 4Bit Double Data Rate SDRAM PRELIMINARY DESCRIPTION The Hyundai HY5DU564022 is a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY5DU564022 is organized as 4 banks of 16,777,216x4. HY5DU564022 offers fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the clock(falling edges of the CLK), Data(DQ), Data strobes(LDQS/UDQS) and Write data masks(LDM/UDM) inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2. Mode Register set options include the length of pipeline (CAS latency of 2 / 2.5 / 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 2 / 4 / 8), the burst count sequence(sequential or interleave), DQ FET Control (/QFC) and Output Driver types (Full / Half Strength Driver). Because data rate is doubled through reading and writing at both rising and falling edges of the clock, 2X higher data bandwidth can be achieved than that of traditional (single data rate) Synchronous DRAM. FEATURES • 2.5V V DD and VDDQ power suppliy • • All inputs and outputs are compatible with SSTL_2 interface Delay Locked Loop(DLL) installed with DLL reset mode • Write mask byte controlled by LDM and UDM • Bytewide data strobes by LDQS and UDQS • Programmable CAS Latency 2 and 2.5 supported • Write Operations with 1 Clock Write Latency • /QFC & Half Strength Driver controlled by EMRS • Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode • Internal four bank operations with single pulsed RAS • Auto refresh and self refresh supported • 4096 refresh cycles / 64ms • JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch • Fully differential clock operations(CLK & CLK) with 125MHz/133MHz/143MHz • All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock • Data(DQ) and Write masks(LDM/UDM) latched on both rising and falling edges of the Data Stobe • Data outputs on LDQS/UDQS edges when read (edged DQ) Data inputs on LDQS/UDQS centers when write (centered DQ) ORDERING INFORMATION Part No. Power Suppy HY5DU564022T-7 HY5DU564022T-75 HY5DU564022T-8 Clock Frequency Organization Interface Package 4Banks x 16Mbit x 4 SSTL_2 400mil 66pin TSOP II 143MHz (*PC266A) VDD=2.5V VDDQ=2.5V 133MHz (*PC266B) 125MHz (*PC200) * JEDEC Standard compliant This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1/Jan.00 HY5DU564022 PIN CONFIGURATION VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC NC VDDQ NC NC VDD /QFC, NC NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 TOP VIEW 2 3 4 5 6 7 8 9 10 11 12 13 14 15 400mil X 875mil 16 66 Pin TSOP-II 17 0.65mm Pin Pitch 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC NC VSSQ DQS NC VREF VSS DM /CLK CLK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS PIN DESCRIPTION PIN PIN NAME DESCRIPTION CLK, CLK Differential Clock Input The system clock input. All of the inputs are latched on the rising edges of the clock except DQ, LDQS/UDQS and LDM/UDM that are sampled on the both. CKE Clock Enable Controls internal clock signal. When deactivated, the DDR SDRAM will be one of the states among power down, suspend or self refresh. CS Chip Select Enables or disables all inputs except CLK/CLK, CKE, L/UDQS and L/UDM. BA0, BA1 Bank Select Address Selects bank to be activated during either RAS or CAS activity. Selects bank to be read/written during either RAS or CAS activity. A0 ~ A12 Address Row Address : A0 ~ A12, Column Address : A0 ~ A9,A11 AP Flag : A10 RAS, CAS, WE Row Address Strobe, Column Address Strobe, Write Enable Command Inputs, RAS, CAS and WE define command being issued. Refer function truth table for details. LDM, UDM Write Mask Masks input data in write mode. LDQS, UDQS Data Input/Output Strobe Active on the both edges for Data Input and Output. DQ0 ~ DQ3 Data Input/Output Bidirectional Data input / output pin. VDD/VSS Power Supply/Ground Power supply for internal circuits and input buffers. VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers for Noise immunity. VREF Reference Voltage Reference voltage for inputs for SSTL interface. /QFC (optional) DQ FET Switch Control Controls FET Switches on DQs. NC No Connection No connection. Rev. 0.1/Jan.00 2 HY5DU564022 FUNCTIONAL BLOCK DIAGRAM 4banks x 16Mbit x 4 I/O Double data rate Synchronous DRAM 8 1Mx16/Bank0 1Mx16/Bank2 8 1Mx16/Bank3 Mode Register 4 Output Buffer 1Mx16/Bank1 Command Decoder 2-bit Prefetch Unit Bank Control Sense AMP CLK /CLK CKE /CS /RAS /CAS /WE DM LDQS UDQS Input Buffer 4 Write Data Register 2-bit Prefetch Unit DQ[ 0:3] Row Decoder Column Decoder LDQS, UDQS ADD Address Buffer Column Address Counter CLK_DLL LDQS UDQS CLK /CLK Data Strobe Transmitter Data Strobe Receiver DLL Block Mode Register ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Ambient Temperature TA 0 ~ 70 o C Storage Temperature TSTG -55 ~ 125 o C VIN, VOUT -0.5 ~ 3.6 V VDD -0.5 ~ 3.6 V VDDQ -0.5 ~ 3.6 V Output Short Circuit Current IOS 50 mA Power Dissipation PD 1 W TSOLDER 260 ⋅ 10 Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Voltage on VDDQ relative to V SS Soldering Temperature ⋅ Time Unit oC ⋅ Sec Note : Operation at above absolute maximum rating can adversely affect device reliability. Rev. 0.1/Jan.00 3 HY5DU564022 DC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V) Parameter Symbol Min Typ. Max Unit Power Supply Voltage VDD 2.3 2.5 2.7 V Power Supply Voltage VDDQ 2.3 2.5 2.7 V Input High Voltage VIH VREF + 0.15 - VDDQ + 0.3 V Input Low Voltage VIL -0.3 - VREF - 0.15 V Termination Voltage VTT VREF - 0.04 VREF VREF + 0.04 V VREF 1.15 1.25 1.35 V Reference Voltage Note 1 2 3 Note : 1. VDDQ must not exceed the level of V DD. 2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration. 3. The value of VREF is approximately equal to 0.5V DDQ. AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V) Parameter Value Unit Reference Voltage VDDQ x 0.5 V Termination Voltage VDDQ x 0.5 V AC Input High Level Voltage (VIH, min) VREF + 0.31 V AC Input Low Level Voltage (V IL, max) VREF - 0.31 V VREF V Output Timing Measurement Reference Level Voltage VTT V Input Signal maximum peak swing 1.5 V Input minimum Signal Slew Rate 1 V/ns Termination Resistor (R T) 50 Ω Series Resistor (RS) 25 Ω Output Load Capacitance for Access Time Measurement (CL) 30 pF Input Timing Measurement Reference Level Voltage Rev. 0.1/Jan.00 4 HY5DU564022 CAPACITANCE (TA=25oC, f=1MHz ) Parameter Pin Symbol Min Max Unit Input Capacitance A0 ~ A11, BA0 ~ BA1, CKE, CS, RAS, CAS, WE CIN 2.0 3.0 pF Clock Capacitance CLK, CLK C CLK 2.0 3.0 pF Data Input / Output Capacitance DQ0 ~ DQ15, LDQS, UDQS, LDM, UDM CIO 4.0 5.0 pF Note : 1. VDD, VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, V Opeak-to-peak = 0.2V 2. Pins not under test are tied to GND. 3. These values are guaranteed by design and are tested on a sample basis only. OUTPUT LOAD CIRCUIT VTT VTT RT=50Ω RT=50Ω Output R S=25Ω Zo=50Ω VREF C L=30pF Rev. 0.1/Jan.00 5 HY5DU564022 DC CHARACTERISTICS I (TA=0 to 70°C, Voltage referenced to VSS = 0V) Parameter Symbol Min. Max Unit Note Input Leakage Current ILI -5 5 uA 1 Output Leakage Current ILO -5 5 uA 2 Output High Voltage VOH VTT + 0.76 - V IOH = -15.2mA Output Low Voltage VOL - VTT - 0.76 V IOL = +15.2mA Note : 1.VIN = 0 to 2.7V, All other pins are not tested under VIN =0V 2.DOUT is disabled, V OUT=0 to 2.7V DC CHARACTERISTICS II (TA=0 to 70°C, Voltage referenced to VSS = 0V) Speed Parameter Operating Current Symbol IDD1 Test Condition Burst length=2, One bank active tRC ≥ tRC(min), IOL=0mA -7 -75 -8 TBD TBD TBD Unit Not e mA 1 Precharge Standby Current in Power Down Mode IDD2P CKE ≤ VIL(max), tCK = min TBD mA Precharge Standby Current in Non Power Down Mode IDD2N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = min Input signals are changed one time during 2clks TBD mA Active Standby Current in Power Down Mode IDD3P CKE ≤ VIL(max), tCK = min TBD mA Active Standby Current in Non Power Down Mode IDD3N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = min Input signals are changed one time during 2clks TBD mA tCK ≥ tCK(min), I OL=0mA All banks active Burst Mode Operating Current IDD4 Auto Refresh Current IDD5 tRC ≥ tRFC(min), All banks active Self Refresh Current IDD6 CKE ≤ 0.2V CL=2.5 TBD TBD TBD CL=2 TBD TBD TBD mA 1 TBD mA 2 TBD mA Note : 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open. 2. Min. of t RFC (Auto Refresh Row Cycle Time) is shown at AC CHARACTERISTICS. Rev. 0.1/Jan.00 6 HY5DU564022 AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter -7(PC266A) -75(PC266B) -8(PC200) Min Max Min Max Min Max Symbol Unit Row Cycle Time tRC 65 - 65 - 70 - ns Auto Refresh Row Cycle Time tRFC 75 - 75 - 80 - ns Row Active Time tRAS 45 120K 48 120K 50 120K ns Row Address to Column Address Delay tRCD 20 - 20 - 20 - ns Row Active to Row Active Delay tRRD 15 - 15 - 15 - ns Column Address to Column Address Delay tCCD 1 - 1 - 1 - CLK Row Precharge Time tRP 20 - 20 - 20 - ns Write Recovery Time tWR 15 - 15 - 15 - ns Last Data-In to Read Command tDRL 1 - 1 - 1 - CLK Auto Precharge Write Recovery + Precharge Time tDAL 35 - 35 - 35 - ns 7 15 7.5 15 8 15 ns 7.5 15 10 15 10 15 ns CAS Latency = 2.5 Note tCK System Clock Cycle Time CAS Latency = 2 Clock High Level Width tCH 0.45 0.55 0.45 0.55 0.45 0.55 CLK Clock Low Level Width tCL 0.45 0.55 0.45 0.55 0.45 0.55 CLK Data-Out edge to Clock edge Skew tAC -0.75 0.75 -0.75 0.75 -0.8 0.8 ns DQS-Out edge to Clock edge Skew tDQSCK -0.75 0.75 -0.75 0.75 -0.8 0.8 ns DQS-Out edge to Data-Out edge Skew tDQSQA - 0.5 - 0.5 - 0.6 ns Data-Out hold time from DQS tQH tHPmin -0.75ns - tHPmin -0.75ns - tHPmin -0.75ns - ns 1 Clock Half Period tHP tCH/L min - tCH/L min - tCH/L min - ns 1 Input Setup Time (fast slew rate) tIS 0.9 - 0.9 - 1.0 - ns 2,3,5,6 Input Hold Time (fast slew rate) tIH 0.9 - 0.9 - 1.0 - ns 2,3,5,6 Input Setup Time (slow slew rate) tIS 1.1 - 1.1 - 1.1 - ns 2,4,5,6 Input Hold Time (slow slew rate) tIH 1.1 - 1.1 - 1.1 - ns 2,4,5,6 tIPW 2.2 - 2.2 - - - ns 6 Write DQS High Level Width tDQSH 0.4 0.6 0.4 0.6 0.4 0.6 CLK Write DQS Low Level Width tDQSL 0.4 0.6 0.4 0.6 0.4 0.6 CLK CLK to First Rising edge of DQS-In tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 CLK Data-In Setup Time to DQS-In (DQ & DM) tDS 0.5 - 0.5 - 0.6 - ns 7 Data-in Hold Time to DQS-In (DQ & DM) tDH 0.5 - 0.5 - 0.6 - ns 7 Input Pulse Width Rev. 0.1/Jan.00 7 HY5DU564022 AC CHARACTERISTICS - continued - (AC operating conditions unless otherwise noted) Parameter -7(PC266A) -75(PC266B) -8(PC200) Min Max Min Max Min Max Symbol Unit DQ & DM Input Pulse Width tDIPW 1.75 - 1.75 - 2 - ns Read DQS Preamble Time tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 CLK Read DQS Postamble Time tRPST 0.4 0.6 0.4 0.6 0.4 0.6 CLK Write DQS Preamble Setup Time tWPRES 0 - 0- - 0 - CLK Write DQS Preamble Hold Time tWPREH 0.25 - 0.2 - 0.25 - CLK Write DQS Postamble Time tWPST 0.4 0.6 0.4 0.6 0.4 0.6 CLK Mode Register Set Delay tMRD 2 - 2 - 2 - CLK Power Down Exit Time tPDEX 10 - 10 - 10 - ns Exit Self Refresh to Read Cimmand tXSRD 200 - 200 - 200 - CLK Average Periodic Refresh Interval tREFI - 15.6 - 15.6 - 15.6 us Note 8 Note : 1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter. 2. Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, CS, RAS, CAS, WE. 3. For command/address input slew rate >=1.0V/ns 4. For command/address input slew rate >=0.5V/ns and <1.0V/ns 5. CK, /CK slew rates are >=1.0V/ns 6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester correlation. 7. Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM 8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command where CKE is held high, is required to complete Self Refresh Exit and lock the internal DLL operation WRITE MASK TRUTH TABLE Function A10/ AP CKEn-1 CKEn CS, RAS, CAS, WE LDM UDM Data Write H X X L L X 1,2 Data-In Mask H X X H H X 1,2 Lower Byte Write / Upper Byte-In Mask H X X L H X 1,2 Upper Byte Write / Lower Byte-In Mask H X X H L X 1,2 ADDR BA Note Note : 1. Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data. 2. In case of x16 data I/O, LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15) respectively. Rev. 0.1/Jan.00 8 HY5DU564022 SIMPLIFIED COMMAND TRUTH TABLE A10/ AP Command CKEn-1 CKEn CS RAS CAS WE Extended Mode Register Set H X L L L L OP code 1,2 Mode Register Set H X L L L L OP code 1,2 H X X X H X X 1 L H H H Device Deselect No Operation Bank Active H X L L H H H X L H L H ADDR RA Read BA V L CA Read with Autoprecharge 1 1,3 L H X L H L L CA Write with Autoprecharge 1 V H Precharge All Banks H X L L H L Precharge selected Bank 1 V H Write Note 1,4 H X 1,5 L V 1 X Read Burst Stop H X L H H L X 1 Auto Refresh H H L L L H X 1 Entry H L L L L H H X X X Exit L H L H H H H X X X L H H H Self Refresh Entry H X 1 1 L Precharge Power Down Mode 1 X Exit Active Power Down Mode (Clock Suspend) 1 Entry Exit L H L H X X X 1 L H H H 1 H X X X 1 L V V V H L H X X 1 1 ( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation ) Note : 1. LDM/UDM states are “Don’t Care”. Refer to below Write Mask Truth Table. 2. OP Code(Operand Code) consists of A0~A11 and BA 0~BA1 used for Mode Registering duing Extended MRS or MRS. Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP period from Prechagre command. 3. If a Read with Autoprecharge command is detected by memory component in CLK(n), then there will be no command presented to activated bank until CLK(n+BL/2+t RP). 4. If a Write with Autoprecharge command is detected by memory compoment in CLK(n), then there will be no command presented to activated bank until CLK(n+BL/2+1+t DPL+tRP). Last Data-In to Prechage delay(t DPL) which is also called Write Recovery Time (tWR) is needed to guarantee that the last data has been completely written. 5. If A10/AP is “High” when Row Precharge command being issued, BA 0/BA1 are ignored and all banks are selected to be precharged. Rev. 0.1/Jan.00 9 HY5DU564022 PACKAGE INFORMATION 400mil 66pin Thin Small Outline Package Unit : mm(Inch) 11.94 (0.470) 11.79 (0.462) 10.26 (0.404) 10.05 (0.396) BASE PLANE 22.33 (0.879) 22.12 (0.871) 0.65 (0.0256) BSC 1.194 (0.0470) 0.991 (0.0390) Rev. 0.1/Jan.00 0.35 (0.0138) 0.25 (0.0098) 0 ~ 5 Deg. SEATING PLANE 0.15 (0.0059) 0.05 (0.0020) 0.597 (0.0235) 0.406 (0.0160) 0.210 (0.0083) 0.120 (0.0047) 10