HYM5V64404A Q-Series SO DIMM 4Mx64 bit CMOS DRAM MODULE based on 4Mx16 DRAM, EDO, 3.3V, 4K/8K-Refresh DESCRIPTION The HYM5V64404A Q-Series is a 4Mx64-bit EDO mode CMOS DRAM module consisting of four 4Mx16 TSOP and one 2048-bit EEPROM on a 144 pin glass-epoxy printed circuit board. 0.1µF and 0.01µF decoupling capacitors are mounted for each DRAM. The HYM5V64404AQ G-series is gold plated socket type Dual In-line Memory Module suitable for easy interchange and addition of 32M byte memory. FEATURES • Max. Active Power Dissipation • Single power supply of 3.3V ± 10% Speed 8K 4K 50 60 1.58W 1.30W 2.02W 1.73W • Read-Modify-Write Capability • LVTTL compatible inputs and outputs • /CAS-before-/RAS, /RAS-only, Hidden and Self refresh capability • Refresh cycles • Fast access time and cycle time Speed tRAC tCAC tHPC Part No. Ref. 50 50ns 13ns 25ns HYM5V64404A Q-Series 4K 60 60ns 15ns 30ns HYM5V64434A Q-Series 8K£ ª • 144-Pin SO DIMM • Serial Presence Detect with EEPROM £ /ªCAS-before-/RAS refresh, Hidden refresh mode : 4K cycles / 64ms • Extended Data Out Operation PIN DISCRIPTION /RAS0 /CAS0-CAS7, /WE /OE A0 -A12 A0 -A11 DQ0-DQ63 SCL SDA VCC VSS Row Address Strobe Column Address Strobe Write Enable Output Enable Address Input(8K Product) Address Input(4K Product) Data Input / Output Serial PD Clock Input Serial PD Data Input/Output Power (+3.3V) Ground This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.04 / May.98 1998 Hyundai Semiconductor HYM5V64404A Q-Series PIN NAME # NAME # NAME # NAME # NAME 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 Vss DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 Vss /CAS0 /CAS1 Vcc A0 A1 A2 Vss DQ8 DQ9 DQ10 DQ11 Vcc DQ12 DQ13 DQ14 DQ15 Vss NC NC NC Vcc NC /WE /RAS0 NC 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 Vss DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 Vss /CAS4 /CAS5 Vcc A3 A4 A5 Vss DQ40 DQ41 DQ42 DQ43 Vcc DQ44 DQ45 DQ46 DQ47 Vss NC NC NC Vcc NC NC NC NC 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 /OE Vss NC NC Vcc DQ16 DQ17 DQ18 DQ19 Vss DQ20 DQ21 DQ22 DQ23 Vcc A6 A8 Vss A9 A10 Vcc /CAS2 /CAS3 Vss DQ24 DQ25 DQ26 DQ27 Vcc DQ28 DQ29 DQ30 DQ31 Vss SDA Vcc 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 NC Vss NC NC Vcc DQ48 DQ49 DQ50 DQ51 Vss DQ52 DQ53 DQ54 DQ55 Vcc A7 A11 Vss *A12 NC Vcc /CAS6 /CAS7 Vss DQ56 DQ57 DQ58 DQ59 Vcc DQ60 DQ61 DQ62 DQ63 Vss SCL Vcc NOTE : 1.A12 is used for 8K-Refresh Product (HYM5V64434A Q-Series) 2 HYM5V64404A Q-Series SERIAL PRESENCE DETECT BYTE NUMBER FUNCTION DESCRIBED FUNCTION VALUE BYTE0 128 Bytes 80h BYTE1 BYTE2 BYTE3 # of Byte Written into Serial Memory at Module Manufacturer Total # of Bytes of SPD Memory Device Fundamental Memory Type # of Row Addresses on This Assembly BYTE4 # of Column Addresses on This Assembly BYTE5 BYTE6 BYTE7 BYTE8 BYTE9 # of Module Banks on This Assembly Data Width of This Assembly Data Width of This Assembly(Continued) Voltage Interface Standard of This Assembly tRAC 256 Bytes EDO 12(4K Ref) 13(8K Ref) 10(4K Ref) 9(8K Ref) 1 Bank 64 Bits LVTTL 50ns 60ns 08h 02h 0Ch 0Dh 0Ah 09h 01h 40h 00h 01h 32h 3Ch BYTE10 tCAC 13ns 15ns 0Dh 0Fh BYTE11 BYTE12 DIMM Configuration Type Refresh Rate/Type 00h 00h 83h BYTE13 BYTE14 BYTE15-61 BYTE62 BYTE63 Primary DRAM Width Error Checking DRAM Width Undefined SPD Data Revision Code Checksum for Byte 0-62 None 4K/8K Ref, Normal(15.6µs) 4K/8K Ref, SL-Part (31.25µs) x16 None Undefined Initial 4K/8K Ref. 50ns 60ns Normal(15.6µs) 4K/8K Ref. SL-Part(31.25µs) 50ns 60ns 10h 00h FFh 00h 02h 0Eh 85h 91h BYTE64-125 Manufacturer Data Field HYUNDAI MFD BYTE126-127 Reserved Reserved FFh BYTE128-255 Undefined Undefinded FFh NOTE : 1.Serial PD interface is standard IIC architecture. 2.Pull-up resistors(4.7K typical value) are required on all open collector bus devices(SCL and SDA). 3.Current sink capability on SCL and SDA (Iol max) must be at least 3mA to maintain a valid low level. 4.Checksum can be obtained by adding the binary values in Byte 0-62, and eliminate all but low order byte. The low order byte would be the `Checksum`. 5.Refer to HYUNDAI Manufacturer Data SPEC for Byte 64-125. 3 HYM5V64404A Q-Series BLOCK DIAGRAM NOTE : 1.A12 is used for 8K-Refresh Product (HYM5V64434A Q-Series) 4 HYM5V64404A Q-Series ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER RATING UNIT TA Ambient Temperature 0 to 70 °C TSTG Storage Temperature -55 to 150 °C VIN, VOUT Voltage on Any Pin relative to VSS -0.5 to 4.6 V VCC Voltage on VCC relative to VSS -0.5 to 4.6 V IOS Short Circuit Output Current 50 mA PD Power Dissipation 4 W TSOLDER Soldering Temperature•Time 260•10 °C•sec Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (TA=0°C to 70°C ) SYMBOL PARAMETER MIN. TYP. MAX. UNIT VCC Power Supply Voltage 3.0 3.3 3.6 V VIH Input High Voltage 2.0 - VCC+0.3 V VIL Input Low Voltage -0.3 - 0.8 V Note: All voltages are referenced to VSS. 5 HYM5V64404A Q-Series DC CHARACTERISTICS (TA=0°C to 70°C , VCC=3.3V ± 10%, VSS=0V, unless otherwise noted.) Symbol Parameter Test Conditions Speed Unit 8K Product 4K Product 440 360 560 480 mA 4 4 mA ICC1 Operating Current /RAS, /CAS Cycling tRC=tRC (min.) ICC2 LVTTL Standby Current /RAS = /CAS ≥ VIH other inputs ≥ VSS ICC3 /RAS-only Refresh Current /RAS cycling /CAS = VIH tRC = tRC (min.) 50 60 440 360 560 480 mA ICC4 EDO Mode Current /CAS cycling /RAS = VIL tHPC = tHPC (min.) 50 60 480 400 520 440 mA ICC5 CMOS Standby Current /RAS = /CAS ≥ VCC - 0.2V 2 1.2 2 1.2 mA SL-part ICC6 /CAS-before-/RAS Refresh Current tRC=tRC (min.) 50 60 440 360 560 480 mA ICC7 Battery Back-up Current (SL-part) VIH = VCC - 0.2V, VIL = 0.2V /CAS = CBR cycling or 0.2V /OE & /WE = VIH = VCC - 0.2V Address = Don`t care DQs = Open, tRC=31.25 µs 2.2 2.2 mA Self Refresh Current (SL-part) /RAS & /CAS = 0.2V Other pins are same as ICC7 1.8 1.8 mA Test Condition Min. Max Unit ICC8 Symbol Parameter 50 60 Max. Current ILI Input Leakage current(Any Input) VSS ≤ VIN ≤ VCC + 0.3, All other pins not under test=VSS -20 20 µA ILO Output Leakage current(Any Input) VSS ≤ VOUT ≤ VCC /RAS & /CAS at VIH -5 5 µA VOL Output Low Voltage IOL = 2.0mA - 0.4 V VOH Output High Voltage IOH = -2.0mA 2.4 - V NOTE 1. ICC1, ICC3, ICC4 and ICC6 dependent on output loading and cycle rates(tRC and tHPC). 2. Specified values are obtained with outputs unloaded. 3. ICC is specified as an average current. In ICC1, ICC3, ICC6, address can be changed only once while /RAS=VIL. In ICC4, address can be changed maximum once while /CAS=VIH within one EDO mode cycle time tHPC. 4. Only /RAS(max.) = 1µs is applied to refresh of battery backup but tRAS(max.) = 10µs is applied to normal functional operation. 5. ICC5(max.) = 1.2mA, ICC7 and ICC8 are applied to SL-part only. 6. VOH = 2.0V, VOL = 0.8V at AC Functional Test. 6 HYM5V64404A Q-Series AC CHARACTERISTICS (TA=0°C to 70°C , Vcc=3.3V ± 10%, Vss=0V, unless otherwise noted.) HYH5V64404A / HYM5V64434A # SYMBOL PARAMETER -50 -60 -70 UNIT NOTE MIN. MAX. MIN. MAX. MIN. MAX. 1 tRC Random Read or Write Cycle Time 90 - 110 - ns 2 tRWC Read-Modify-Write Cycle Time 128 - 153 - ns 3 tHPC EDO Mode Cycle Time 4 tHPRWC EDO Mode Read-Modify-Write Cycle Time 25 - 30 - ns 67 - 73 - ns 5 tRAC Access Time from /RAS - 50 - 60 ns 4,5,10,11 6 tCAC Access Time from /CAS - 13 - 15 ns 4,5,10 7 tAA Access Time from Column Address - 25 - 30 ns 4,5,11 8 tCPA Access Time from /CAS Precharge - 28 - 35 ns 4 9 tCLZ /CAS to Output Low Impedance 3 - 3 - ns 3 10 tCEZ Output Buffer Turn-off delay from /CAS 3 13 3 13 ns 11 tT Transition Time (Rise and Fall) 2 50 2 50 ns 4 12 tRP /RAS Precharge Time 30 - 40 - ns 13 tRAS /RAS Pulse Width 50 10K 60 10K ns 14 tRASP /RAS Pulse Width (EDO Mode) 50 100K 60 100K ns 15 tRSH /RAS Hold Time 13 - 15 - ns 16 tCSH /CAS Hold Time 40 - 45 - ns 17 tCAS /CAS Pulse Width 8 10K 10 10K ns 18 tRCD /RAS to /CAS Delay 17 37 20 45 ns 10 19 tRAD /RAS to Column Address Delay Time 13 25 15 30 ns 11 20 tCRP /CAS to /RAS Precharge Time 5 - 5 - ns 21 tCP /CAS Precharge Time 8 - 10 - ns 22 tASR Row Address Set-up Time 0 - 0 - ns 23 tRAH Row Address Hold Time 8 - 10 - ns 24 tASC Column Address Set-up Time 0 - 0 - ns 25 tCAH Column Address Hold Time 8 - 10 - ns 26 tAR Column Address Hold Time from /RAS 45 - 50 - ns 27 tRAL Column Address to /RAS Lead Time 25 - 30 - ns 28 tRCS Read Command Set-up Time 0 - 0 - ns 29 tRCH Read Command Hold Time Referenced to /CAS 0 - 0 - ns 7 30 tRRH Read Command Hold Time Referenced to /RAS 0 - 0 - ns 7 31 tWCH Write Command Hold Time 10 - 10 - ns 32 tWCR Write Command Hold Time from /RAS 40 - 45 - ns 33 tWP Write Command Pulse Width 8 - 10 - ns 34 tRWL Write Command to /RAS Lead Time 15 - 15 - ns 35 tCWL Write Command to /CAS Lead Time 8 - 10 - ns 7 HYM5V64404A Q-Series AC CHARACTERISTICS (Continued) HYH5V64404A / HYM5V64434A # SYMBOL PARAMETER -50 -60 -70 UNIT NOTE MIN. MAX. MIN. MAX. MIN. MAX. 36 tDS Data-In Set-up Time 0 - 0 - ns 8 37 tDH Data-In Hold Time 10 - 10 - ns 8 38 tDHR Data-In Hold Time Referenced to /RAS 40 - 45 - ns 39 tREF Refresh Period (8192 cycles) - 64 - 64 ms 12,13 Refresh Period (4096 cycles) - 64 - 64 ms 12 Refresh Period (SL-part) - 128 - 128 ms 12,13 40 tWCS Write Command Set-up Time 0 - 0 - ns 9 41 tCWD /CAS to /WE Delay Time 34 - 36 - ns 9 42 tRWD /RAS to /WE Delay Time 70 - 80 - ns 9 43 tAWD Column Address to /WE Delay Time 45 - 50 - ns 9 44 tCSR /CAS Set-up Time (CBR Cycle) 5 - 5 - ns 45 tCHR /CAS Hold Time (CBR Cycle) 10 - 10 - ns 46 tRPC /RAS to /CAS Precharge Time 5 - 5 - ns 47 tCPT /CAS Precharge Time (CBR Counter Test) 25 - 30 - ns 48 tROH /RAS Hold Time Referenced to /OE 0 - 0 - ns 49 tOEA /OE Access Time - 13 - 15 ns 50 tOED /OE to Data Delay 13 - 15 - ns 51 tOEZ Output Buffer Turn-Off Delay Time from /OE 0 10 0 15 ns 52 tOEH /OE Command Hold Time 13 - 15 - - -- 6 ns 53 tCPWD /WE Delay Time from /CAS Precharge 45 - 54 - ns 54 tRHCP /RAS Hold Time from /CAS Precharge 30 - 35 - ns 55 tWRP /WE to /RAS Precharge Time(CBR cycle) 10 - 10 - ns 56 tWRH /WE to /RAS Hold Time (CBR cycle) 10 - 10 - ns 57 tWTS Write Command Set-up Time (Test Mode In) 10 - 10 - ns 58 tWTH Write Command Hold Time (Test Mode In) 59 tRASS /RAS Pulse Width (Self Refresh) 60 tRPS 9 10 - 10 - ns 100K - 100K - us /RAS Precharge Time (Self Refresh) 100 - 100 - ns 61 tCHS /CAS Hold Time (Self Refresh) -50 - -50 - ns 62 tDOH Output Data Hold Time 5 - 5 - ns 63 tREZ Output Buffer Turn-off Delay from /RAS 0 10 0 15 ns 6 64 tWEZ Output Buffer Turn-off Delay from /WE 0 10 0 15 ns 6 65 tWED /WE to Data Delay Time 15 - 15 - ns 66 tOEP /OE Precharge Time 5 - 5 - ns 67 tWPE /WE Pulse Width (EDO cycle) 5 - 5 - ns 68 tOCH /OE to /CAS Hold Time 5 - 5 - ns 69 tCHO /CAS Hold Time to /OE 5 - 5 - ns 8 HYM5V64404A Q-Series NOTE 1. An initial pause of 200µs is required after power-up followed by 8 /RAS cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 /CAS-before-/RAS initialization cycles instead of 8 /RAS-only refresh cycles are required. The device should be carefully initialized to be prevented from being entered into multi bit test mode during initialization. 2. If /RAS=Vss during power-up, the HYM5V64404A / HYM5V64434A could begin an active cycle. This condition results in higher current than necessary current which is demanded from the power supply during power-up. 3. It is recommended that /RAS and /CAS track with Vcc during power-up or be held at a valid VIH in order to minimize the power-up current. 4. VIH(min.) and VIL(max.) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min.) and VIL(max.), and are assumed to be 5ns for all inputs. 5. Measured at VOH=2.0V and VOL=0.8V with a load equivalent to 1 TTL loads and 100pF. 6. tWEZ, tREZ, tCEZ and tOEZ define the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. Either tRCH or tRRH must be satisfied for a read cycle. 8. These parameters are referenced to /CAS leading edge in early write cycles and to /WE leading edge in Read-Modify-Write cycles and late Write cycle. 9. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS(min.), the cycle is an early write cycle and data out pin will remain open circuit (high impedance) through the entire cycle. If tRWD ≥ tRWD(min.), tCWD ≥ tCWD(min.), tAWD ≥ tAWD(min.), and tCPWD ≥ tCPWD(min.), the cycle is a Read-Modify-Write cycle and data out will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 10.Operation within the tRCD(max.) limit ensures that tRAC(max.) can be met. tRCD(max.) is specified as a reference point only. If tRCD is greater than the specified tRCD(max.) limit, then access time is controlled by tCAC. 11.Operation within the tRAD(max.) limit ensures that tRAC(max.) can be met. tRAD(max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(max.) limit, then access time is controlled by tAA. 12.tREF(max.)=128ms is applied to SL-parts. 13.A burst of 8192 /RAS-only refresh cycles must be executed within 64ms (128ms for SL-parts) after exiting self refresh. (CBR refresh & Hidden refresh : 4K cycle/64ms) CAPACITANCE (TA=0°C to 70°C , Vcc=3.3V ± 10%, Vss=0V, f = 1MHz, unless otherwise noted.) SYMBOL CIN1 CIN2 CIN3 CIN4 CDQ PARAMETER Input Capacitance (A0 - A12) Input Capacitance (/WE, /OE) Input Capacitance (/RAS0) Input Capacitance (/CAS0 - /CAS7) Data Input /Output Capacitance (DQs) TYP. - MAX. 28 38 38 14 14 UNIT pF pF pF pF pF 9 HYM5V64404A Q-Series PACKAGE INFORMATION 10 HYM5V64404A Q-Series ORDERING INFORMATION Part Number HYM5V64404ATQG HYM5V64404ASLTQG HYM5V64434ATQG HYM5V64434ASLTQG Ref. 4K 4K 8K 8K Power Normal SL-part Normal SL-part Package TSOP TSOP TSOP TSOP 11