200pin Unbuffered DDR SDRAM SO-DIMMs based on 512Mb B ver. (TSOP) This Hynix unbuffered Small Outline, Dual In-Line Memory Module (DIMM) series consists of 512Mb B ver. DDR SDRAMs in 400mil TSOP II packages on a 200pin glass-epoxy substrate. This Hynix 512Mb B ver. based unbuffered SO-DIMM series provide a high performance 8 byte interface in 67.60mm width form factor of industry standard. It is suitable for easy interchange and addition. FEATURES • JEDEC Standard 200-pin small outline, dual in-line memory module (SO-DIMM) • Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode • Two ranks 64M x 64 organization • • 2.6V ± 0.1V VDD and VDDQ Power supply for DDR400, 2.5V ± 0.2V for DDR333 and below Edge-aligned DQS with data outs and Center-aligned DQS with data inputs • Auto refresh and self refresh supported • All inputs and outputs are compatible with SSTL_2 interface • 8192 refresh cycles / 64ms • Serial Presence Detect (SPD) with EEPROM • Fully differential clock operations (CK & /CK) with 133/166/200MHz • Built with 512Mb DDR SDRAMs in 400 mil TSOP II packages • DLL aligns DQ and DQS transition with CK transition • • Programmable CAS Latency: DDR266(2, 2.5 clock), DDR333(2.5 clock), DDR400(3 clock) Lead-free product listed for each configuration (RoHS compliant) ADDRESS TABLE 512MB Organization Ranks SDRAMs # of DRAMs # of row/bank/column Address Refresh Method 64M x 64 2 32Mb x 16 8 13(A0~A12)/2(BA0,BA1)/10(A0~A9) 8K / 64ms PERFORMANCE Part-Number Suffix -D431 -J -H Unit Speed Bin DDR400B DDR333 DDR266B - 3-3-3 2.5-3-3 2.5-3-3 CK CL=3 200 - - MHz CL=2.5 166 166 133 MHz CL=2 133 133 133 MHz CL - tRCD- tRP Max Clock Frequency Note: 1. 2.6V ± 0.1V VDD and VDDQ Power supply for DDR400 and 2.5V ± 0.2V for DDR333 and below Rev. 1.1 / May. 2005 1 This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. 200pin Unbuffered DDR SDRAM SO-DIMMs ORDERING INFORMATION Part Number HYMD564M646B[L]6-D43/J/H HYMD564M646B[L]P6-D43/J/H Density Organization 512MB 512MB 32Mb x 16 32Mb x 16 # of DRAMs Material DIMM Dimension ECC Support 8 Normal 67.60 x 31.75 x 3.8 [mm3] None 8 Pb-free1 ↑ None Note: 1. The “Pb-free” products contain Lead less than 0.1% by weight and satisfy RoHS - please contact Hynix for product availability. * These products are built with HY5DU124(8,16)22B[L]T[P], the Hynix DDR SDRAM component. Rev. 1.1 / May. 2005 2 200pin Unbuffered DDR SDRAM SO-DIMMs PIN DESCRIPTION Pin Pin Description CK0~2, /CK0~2 /CS0, /CS1 CKE0, CKE1 /RAS, /CAS, /WE A0 ~ A13 A10/AP BA0, BA1 DQ0~DQ63 CB0~CB7 DQS0~DQS8 DM0~8 Pin Differential Clock Inputs Chip Select Inputs Clock Enable Inputs Commend Sets Inputs Address Inputs Address Input/Autoprecharge Bank Address Data Inputs/Outputs Data Check bits Data Strobes Data-in Masks Pin Description VDD VSS VREF VDDSPD VDDID SA0~SA2 SCL SDA DU NC TEST Power Supply for Core and I/O Ground Input/Output Reference Power Supply for SPD VDD, VDDQ Level Detection SPD Address Inputs SPD Clock Input SPD Data Input/Output Do not Use No Connection Reserved for test equipment use PIN ASSIGNMENT Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name 1 VREF 2 VREF 51 VSS 52 VSS 101 A9 102 A8 151 DQ42 152 DQ46 3 VSS 4 VSS 53 DQ19 54 DQ23 103 VSS 104 VSS 153 DQ43 154 DQ47 5 DQ0 6 DQ4 55 DQ24 56 DQ28 105 A7 106 A6 155 VDD 156 VDD 7 DQ1 8 DQ5 57 VDD 58 VDD 107 A5 108 A4 157 VDD 158 /CK1 9 VDD 10 VDD 59 DQ25 60 DQ29 109 A3 110 A2 159 VSS 160 CK1 11 DQS0 12 DM0 61 DQS3 62 DM3 111 A1 112 A0 161 VSS 162 VSS 13 DQ2 14 DQ6 63 VSS 64 VSS 113 VDD 114 VDD 163 DQ48 164 DQ52 15 VSS 16 VSS 65 DQ26 66 DQ30 115 A10,AP 116 BA1 165 DQ49 166 DQ53 17 DQ3 18 DQ7 67 DQ27 68 DQ31 117 BA0 118 /RAS 167 VDD 168 VDD 19 DQ8 20 DQ12 69 VDD 70 VDD 119 /WE 120 /CAS 169 DQS6 170 DM6 21 VDD 22 VDD 71 CB0 72 CB4 121 /CS0 122 /CS1 171 DQ50 172 DQ54 23 DQ9 24 DQ13 73 CB1 74 CB5 123 NC,A13 124 DU 173 VSS 174 VSS 25 DQS1 26 DM1 75 VSS 76 VSS 125 VSS 126 VSS 175 DQ51 176 DQ55 27 VSS 28 VSS 77 DQS8 78 DM8 127 DQ32 128 DQ36 177 DQ56 178 DQ60 29 DQ10 30 DQ14 79 CB2 80 CB6 129 DQ33 130 DQ37 179 VDD 180 VDD 31 DQ11 32 DQ15 81 VDD 82 VDD 131 VDD 132 VDD 181 DQ57 182 DQ61 33 VDD 34 VDD 83 CB3 84 CB7 133 DQS4 134 DM4 183 DQS7 184 DM7 35 CK0 36 VDD 85 DU 86 DU 135 DQ34 136 DQ38 185 VSS 186 VSS 37 /CK0 38 VSS 87 VSS 88 VSS 137 VSS 138 VSS 187 DQ58 188 DQ62 39 VSS 40 VSS 89 CK2 90 VSS 139 DQ35 140 DQ39 189 DQ59 190 DQ63 41 DQ16 42 DQ20 91 /CK2 92 VDD 141 DQ40 142 DQ44 191 VDD 192 VDD 43 DQ17 44 DQ21 93 VDD 94 VDD 143 VDD 144 VDD 193 SDA 194 SA0 45 VDD 46 VDD 95 CKE1 96 CKE0 145 DQ41 146 DQ45 195 SCL 196 SA1 47 DQS2 48 DM2 97 DU 98 DU 147 DQS5 148 DM5 197 VDDSPD 198 SA2 49 DQ18 50 DQ22 99 A12 100 A11 149 VSS 150 VSS 199 VDDID 200 NC,TEST note: 1. Pins 71, 72, 73, 74,77,78,79, 80, 83, 84 are reserved for x72 variants of this module and are not used on the x64 versions. 2. Pin 86 is reserved for a registered variant of this module and is not used on the unbuffered version. 3. Pin 89, 91 are reserved for x72 modules or registered modules and is not used on the unbuffered version. 4. Pin 95, 122 are not used for single rank module. 5. Pin 123 is “NC” for 256MB, 512MB, and 1GB, or “A13” for 2GB module. Rev. 1.1 / May. 2005 3 200pin Unbuffered DDR SDRAM SO-DIMMs FUNCTIONAL BLOCK DIAGRAM 512MB, 64M x 64 Unbuffered SO-DIMM: HYMD564M646B[L][P]6 /CS1 /CS0 DQS0 DM0 DQ00 DQ01 DQ02 DQ03 DQ04 DQ05 DQ06 DQ07 DQS1 DM1 DQ08 DQ09 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 LDQS /CS LDM LDQS /CS LDM I/O0 I/O1 I/O2 I/O0 I/O1 I/O2 I/O3 I/O4 I/O3 I/O4 I/O5 I/O6 I/O5 I/O6 I/O7 UDQS UDM D0 I/O7 UDQS UDM D4 I/O0 I/O1 I/O2 I/O0 I/O1 I/O2 I/O3 I/O4 I/O3 I/O4 I/O5 I/O6 I/O5 I/O6 I/O7 I/O7 LDQS /CS LDM LDQS /CS LDM I/O0 I/O1 I/O2 I/O0 I/O1 I/O2 I/O3 I/O4 I/O3 I/O4 I/O5 I/O6 I/O5 I/O6 I/O7 UDQS UDM D1 I/O7 UDQS UDM I/O0 I/O1 I/O2 I/O0 I/O1 I/O2 I/O3 I/O4 I/O3 I/O4 I/O5 I/O6 I/O5 I/O6 I/O7 I/O7 D5 DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 LDQS /CS LDM LDQS /CS LDM I/O0 I/O1 I/O2 I/O0 I/O1 I/O2 I/O3 I/O4 I/O3 I/O4 I/O5 I/O6 I/O5 I/O6 I/O7 UDQS UDM D2 I/O7 UDQS UDM D6 I/O0 I/O1 I/O2 I/O0 I/O1 I/O2 I/O3 I/O4 I/O3 I/O4 I/O5 I/O6 I/O5 I/O6 I/O7 I/O7 LDQS /CS LDM LDQS /CS LDM I/O0 I/O1 I/O2 I/O0 I/O1 I/O2 I/O3 I/O4 I/O3 I/O4 I/O5 I/O6 I/O5 I/O6 I/O7 UDQS UDM D3 I/O7 UDQS UDM I/O0 I/O1 I/O2 I/O0 I/O1 I/O2 I/O3 I/O4 I/O3 I/O4 I/O5 I/O6 I/O5 I/O6 I/O7 I/O7 D7 # Unless otherwise noted, resistor values are 22O +- 5% BA0-BA1 SDRAMs D0-D7 A0-AN SDRAMs D0-D7 Serial Presence Detector (SPD) /RAS SDRAMs D0-D7 SCL /CAS SDRAMs D0-D7 SA0 /WE SDRAMs D0-D7 SA1 A1 CKE0 SDRAMs D0-D3 SA2 A2 CKE1 SDRAMs D4-D7 VDD SPD VREF VDD VSS VDDID Rev. 1.1 / May. 2005 SPD SDRAMS DO-D7 SDRAMS DO-D7 VDD and VDDQ SDRAMS DO-D7,SPD Strap:see Note 4 A0 SDA WP CK0 /CK0 4 loads CK1 /CK1 4 loads CK2 /CK2 0 loads Notes : DQ wiring may differ from that described in this drawing : however DQ/DM/DQS relationship are maintained as shown. VDDID strap connections: (for memory device VDD, VDDQ) Strap out (open) : VDD = VDDQ Strap in (closed) : VDD ≠ VDDQ 4 200pin Unbuffered DDR SDRAM SO-DIMMs ABSOLUTE MAXIMUM RATINGS1 Parameter Operating Temperature (Ambient) Storage Temperature Voltage on VDD relative to VSS Symbol Rating Unit TA 0 ~ 70 oC TSTG -55 ~ 150 oC VDD -1.0 ~ 3.6 V Voltage on VDDQ relative to VSS VDDQ -1.0 ~ 3.6 V Voltage on inputs relative to Vss VINPUT -1.0 ~ 3.6 V Voltage on I/O pins relative to Vss VIO -0.5 ~3.6 V Output Short Circuit Current IOS 50 Soldering Temperature ⋅ Time mA oC 260 ⋅ 10 TSOLDER ⋅ Sec Note: 1. Operation at above absolute maximum rating can adversely affect device reliability DC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V) Parameter Power Supply Voltage (DDR 200, 266, 333) Symbol Min Typ. Max Unit VDD 2.3 2.5 2.7 V Note VDD 2.5 2.6 2.7 V Power Supply Voltage (DDR 200, 266, 333) VDDQ 2.3 2.5 2.7 V 1 Power Supply Voltage (DDR 400) VDDQ 2.5 2.6 2.7 V 1,2 Input High Voltage VIH VREF + 0.15 - VDDQ + 0.3 V Input Low Voltage VIL -0.3 - VREF - 0.15 V Termination Voltage VTT VREF - 0.04 VREF VREF + 0.04 V VREF 0.49*VDDQ 0.5*VDDQ 0.51*VDDQ V VIN(DC) -0.3 - VDDQ+0.3 V Power Supply Voltage (DDR 400) Reference Voltage Input Voltage Level, CK and CK inputs Input Differential Voltage, CK and CK inputs 2 3 4 VID(DC) 0.36 - VDDQ+0.6 V 5 VI(RATIO) 0.71 - 1.4 - 6 Input Leakage Current ILI -2 - 2 uA 7 Output Leakage Current ILO -5 - 5 uA 8 IOH -16.8 - - mA IOL 16.8 - - mA IOH -13.6 - - mA IOL 13.6 - - mA V-I Matching: Pullup to Pulldown Current Ratio Output High Current Normal Strength (min VDDQ, min VREF, min VTT) Output Driver (VOUT=VTT ± 0.84) Output Low Current (min VDDQ, max VREF, max VTT) Half Strength Out- Output High Current put Driver (min VDDQ, min VREF, min VTT) (VOUT=VTT ± 0.68) Output Low Current (min VDDQ, max VREF, max VTT) Note: 1. VDDQ must not exceed the level of VDD. 2. For DDR400, VDD=2.6V ± 0.1V, VDDQ=2.6V ± 0.1V 3. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration. 4. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of the same. Peak to peak noise on VREF may not exceed ± 2% of the DC value. 5. VID is the magnitude of the difference between the input level on CK and the input level on /CK. 6. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0. 7. VIN=0 to VDD, All other pins are not tested under VIN =0V. 8. DQs are disabled, VOUT=0 to VDDQ. Rev. 1.1 / May. 2005 5 200pin Unbuffered DDR SDRAM SO-DIMMs IDD SPECIFICATION AND CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V) 512MB, 64M x 64 Unbuffered DIMM: HYMD564M646B[L][P]6 Symbol Test Condition Speed Unit DDR400B DDR333 DDR266B IDD0 One bank; Active - Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 800 740 640 mA IDD1 One bank; Active - Read - Precharge; Burst Length=2; tRC=tRC(min); tCK=tCK(min); address and control inputs changing once per clock cycle 1000 900 760 mA IDD2P All banks idle; Power down mode; CKE=Low, tCK=tCK(min) 80 80 80 mA IDD2F /CS=High, All banks idle; tCK=tCK(min); CKE= High; address and control inputs changing once per clock cycle. VIN=VREF for DQ, DQS and DM 280 280 280 mA IDD3P One bank active ; Power down mode; CKE=Low, tCK=tCK(min) 96 96 96 mA IDD3N /CS=HIGH; CKE=HIGH; One bank; Active-Precharge; tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle 400 360 320 mA IDD4R Burst=2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); IOUT=0mA 1320 1180 1000 mA IDD4W Burst=2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle 1520 1300 1200 mA IDD5 tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A & DDR266B at 133Mhz; distributed refresh 1400 1300 1200 mA IDD6 CKE=<0.2V; External clock on; tCK Normal =tCK(min) Low Power 40 40 40 mA 20 20 20 mA IDD7 Four bank interleaving with BL=4 Refer to the following page for detailed test condition 2360 2020 1680 mA Note * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Rev. 1.1 / May. 2005 6 200pin Unbuffered DDR SDRAM SO-DIMMs AC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V) Parameter Input High (Logic 1) Voltage, DQ, DQS and DM signals Symbol Min Max Unit VIH(AC) VREF + 0.31 - V Note Input Low (Logic 0) Voltage, DQ, DQS and DM signals VIL(AC) - VREF - 0.31 V Input Differential Voltage, CK and /CK inputs VID(AC) 0.7 VDDQ + 0.6 V 1 Input Crossing Point Voltage, CK and /CK inputs VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 2 Note: 1. VID is the magnitude of the difference between the input level on CK and the input on /CK. 2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same. AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V) Value Unit Reference Voltage Parameter VDDQ x 0.5 V Termination Voltage VDDQ x 0.5 V AC Input High Level Voltage (VIH, min) VREF + 0.31 V AC Input Low Level Voltage (VIL, max) VREF - 0.31 V Input Timing Measurement Reference Level Voltage VREF V Output Timing Measurement Reference Level Voltage VTT V Input Signal maximum peak swing 1.5 V 1 V/ns Input minimum Signal Slew Rate Termination Resistor (RT) 50 Ω Series Resistor (RS) 25 Ω Output Load Capacitance for Access Time Measurement (CL) 30 pF OUTPUT LOAD CIRCUIT VTT RT=50Ω Output Zo=50Ω VREF CL=30pF Rev. 1.1 / May. 2005 7 200pin Unbuffered DDR SDRAM SO-DIMMs CAPACITANCE (TA=25oC, f=100MHz) 512MB: HYMD564M646B[L][P]6 Symbol Min Max Unit A0 ~ A12, BA0, BA1 Input/Output Pins CIN1 36 48 pF /RAS, /CAS, /WE CIN2 36 48 pF CKE0, CKE1 CIN3 28 40 pF /CS0, /CS1 CIN4 28 40 pF CK0, /CK0, CK1, /CK1, CK2, /CK2 CIN5 18 27 pF DM0 ~ DM7 CIN6 12 18 pF DQ0 ~ DQ63, DQS0 ~ DQS7 CIO1 12 18 pF Rev. 1.1 / May. 2005 8 200pin Unbuffered DDR SDRAM SO-DIMMs AC CHARACTERISTICS (note: 1 - 9 / AC operating conditions unless otherwise noted) Parameter Symbol DDR400B DDR333 DDR266A DDR266B DDR200 Min Max Min Max Min Max Min Max Min Max UNIT Row Cycle Time tRC 55 - 60 - 65 - 65 - 70 - ns Auto Refresh Row Cycle Time tRFC 70 - 72 - 75 - 75 - 80 - ns Row Active Time tRAS 40 70K 42 70K 45 120K 45 120K 50 120K ns tRAP tRCD or tRASmin - tRCD or tRASmin - tRCD or tRASmin - tRCD or tRASmin - tRCD or tRASmin - ns Row Address to Column Address Delay tRCD 15 - 18 - 20 - 20 - 20 - ns Row Active to Row Active Delay tRRD 10 - 12 - 15 - 15 - 15 - ns Column Address to Column Address Delay tCCD 1 - 1 - 1 - 1 - 1 - tCK Row Precharge Time tRP 15 - 18 - 20 - 20 - 20 - ns Write Recovery Time tWR 15 - 15 - 15 - 15 - 15 - ns Internal Write to Read Command Delay tWTR 2 - 1 - 1 - 1 - 1 - tCK tDAL (tWR/ tCK) + (tRP/tCK) - (tWR/ tCK) + (tRP/tCK) - (tWR/ tCK) + (tRP/tCK) - (tWR/ tCK) + (tRP/tCK) - (tWR/ tCK) + (tRP/tCK) - tCK 5 10 - - - - - - - - - - 6 12 7.5 12 7.5 12 8.0 12 ns - - 7.5 12 7.5 12 10 12 10 12 ns Active to Read with Auto Precharge Delay Auto Precharge Write Recovery + Precharge Time22 CL = 3 System Clock Cycle CL = 2.5 Time24 CL = 2 tCK Clock High Level Width tCH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK Clock Low Level Width tCL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK Data-Out edge to Clock edge Skew tAC -0.7 0.7 -0.7 0.7 -0.75 0.75 -0.75 0.75 -0.75 0.75 ns -0.55 0.55 -0.6 0.6 -0.75 0.75 -0.75 0.75 -0.75 0.75 ns tDQSQ - 0.4 - 0.45 - 0.5 - 0.5 - 0.6 ns tQH tHP -tQHS - tHP -tQHS - tHP -tQHS - tHP -tQHS - tHP -tQHS - ns tHP min (tCL,tCH) - min (tCL,tCH) - min (tCL,tCH) - min (tCL,tCH) - min (tCL,tCH) - ns tQHS - 0.5 - 0.55 - 0.75 - 0.75 - 0.75 ns DQS-Out edge to Clock tDQSCK edge Skew DQS-Out edge to DataOut edge Skew21 Data-Out hold time from DQS20 Clock Half Period19,20 Data Hold Skew Factor20 Valid Data Output Window Rev. 1.1 / May. 2005 tDV tQH-tDQSQ tQH-tDQSQ tQH-tDQSQ tQH-tDQSQ tQH-tDQSQ ns 9 200pin Unbuffered DDR SDRAM SO-DIMMs - Continue Parameter Symbol DDR400B DDR333 DDR266A DDR266B DDR200 UNIT Min Max Min Max Min Max Min Max Min Max tHZ -0.7 0.7 -0.7 0.7 -0.75 0.75 -0.75 0.75 -0.8 0.8 ns tLZ -0.7 0.7 -0.7 0.7 -0.75 0.75 -0.75 0.75 -0.8 0.8 ns tIS 0.6 - 0.75 - 0.9 - 0.9 - 1.1 - ns tIH 0.6 - 0.75 - 0.9 - 0.9 - 1.1 - ns tIS 0.7 - 0.8 - 1.0 - 1.0 - 1.1 - ns tIH 0.7 - 0.8 - 1.0 - 1.0 - 1.1 - ns tIPW 2.2 - 2.2 - 2.2 - 2.2 - 2.5 - ns Write DQS High Level Width tDQSH 0.35 - 0.35 - 0.35 - 0.35 - 0.35 - tCK Write DQS Low Level Width tDQSL 0.35 - 0.35 - 0.35 - 0.35 - 0.35 - tCK Clock to First Rising edge of DQSIn tDQSS 0.72 1.25 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tCK DQS falling edge to CK setup time tDSS 0.2 - 0.2 - 0.2 - 0.2 - 0.2 - tCK DQS falling edge hold time from CK tDSH 0.2 - 0.2 - 0.2 - 0.2 - 0.2 - tCK DQ & DM input setup time25 tDS 0.4 - 0.45 - 0.5 - 0.5 - 0.6 - ns DQ & DM input hold time25 tDH 0.4 - 0.45 - 0.5 - 0.5 - 0.6 - ns DQ & DM Input Pulse Width17 tDIPW 1.75 - 1.75 - 1.75 - 1.75 - 2 - ns Read DQS Preamble Time tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCK Read DQS Postamble Time tRPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK 0 - 0 - 0 - 0 - 0 - ns - 0.25 - 0.25 - 0.25 - 0.25 - tCK Data-out high-impedance window from CK,/CK10 Data-out low-impedance window from CK, /CK10 Input Setup Time (fast slew rate)14,16-18 Input Hold Time (fast slew rate)14,16-18 Input Setup Time (slow slew rate)15-18 Input Hold Time (slow slew rate)15-18 Input Pulse Width17 Write DQS Preamble Setup Time12 tWPRES tWPREH 0.25 Write DQS Preamble Hold Time 11 Write DQS Postamble Time tWPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK Mode Register Set Delay tMRD 2 - 2 - 2 - 2 - 2 - tCK tXSNR 75 - 75 - 75 - 75 - 80 - ns tXSRD 200 - 200 - 200 - 200 - 200 - tCK tREFI - 7.8 - 7.8 - 7.8 - 7.8 - 7.8 us Exit Self Refresh to non-Read command23 Exit Self Refresh to Read command Average Periodic Refresh Interval13,25 Rev. 10 1.1 / May. 2005 200pin Unbuffered DDR SDRAM SO-DIMMs Note: 1. All voltages referenced to Vss. 2. Tests for ac timing, IDD, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Below figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). VDDQ 50 Ω Output (VOUT) 30 pF Figure: Timing Reference Load 4. AC timing and IDD tests may use a VIL to VIHswing of up to 1.5 V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK, /CK), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between VIL(ac) and VIH(ac). 5. The ac and dc input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above (below) the dc input LOW (HIGH) level. 6. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE < 0.2VDDQ is recognized as LOW. 7. The CK, /CK input reference level (for timing referenced to CK, /CK) is the point at which CK and /CK cross; the input reference level for signals other than CK, /CK is VREF. 8. The output timing reference voltage level is VTT. 9. Operation or timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 10. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ). 11. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 12. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from High-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 13. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. 14. For command/address input slew rate ≥ 1.0 V/ns. 15. For command/address input slew rate ≥ 0.5 V/ns and < 1.0 V/ns 16. For CK & /CK slew rate ≥ 1.0 V/ns (single-ended) 17. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 18. Slew Rate is measured between VOH(ac) and VOL(ac). 19. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). For example, tCL and tCH are = 50% of the period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces. Rev. 11 1.1 / May. 2005 200pin Unbuffered DDR SDRAM SO-DIMMs 20.tQH = tHP - tQHS, where: tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push--out of DQS on one transition followed by the worst case pull--in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 21. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle. 22. tDAL = (tWR/tCK) + (tRP/tCK) For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266B at CL=2.5 and tCK=7.5 ns tDAL = ((15 ns / 7.5 ns) + (20 ns / 7.5 ns)) clocks = ((2) + (3)) clocks = 5 clocks 23. In all circumstances, tXSNR can be satisfied using tXSNR = tRFCmin + 1*tCK 24. The only time that the clock frequency is allowed to change is during self-refresh mode. 25. If refresh timing or tDS/tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed. Rev. 12 1.1 / May. 2005 200pin Unbuffered DDR SDRAM SO-DIMMs SYSTEM CHARACTERISTICS CONDITIONS for DDR SDRAMS The following tables are described specification parameters that required in systems using DDR devices to ensure proper performannce. These characteristics are for system simulation purposes and are guaranteed by design. Input Slew Rate for DQ/DM/DQS AC CHARACTERISTICS (Table a.) DDR400 DDR333 DDR266 DDR200 PARAMETER Symbol min max min max min max min max DQ/DM/DQS input slew rate measured between VIH(DC), VIL(DC) and VIL(DC), VIH(DC) DCSLEW 0.5 4.0 0.5 4.0 0.5 4.0 0.5 4.0 UNIT Note V/ns 1,12 Address & Control Input Setup & Hold Time Derating (Table b.) Input Slew Rate Delta tIS Delta tIH UNIT Note 0.5 V/ns 0 0 ps 9 0.4 V/ns +50 0 ps 9 0.3 V/ns +100 0 ps 9 DQ & DM Input Setup & Hold Time Derating (Table c.) Input Slew Rate Delta tDS Delta tDH UNIT Note 0.5 V/ns 0 0 ps 11 0.4 V/ns +75 0 ps 11 0.3 V/ns +150 0 ps 11 DQ & DM Input Setup & Hold Time Derating for Rise/Fall Delta Slew Rate Input Slew Rate Delta tDS Delta tDH UNIT Note ± 0.0 ns/V 0 0 ps 10 ± 0.25 ns/V +50 +50 ps 10 ± 0.5 ns/V +100 +100 ps 10 Output Slew Rate Characteristics (for x4, x8 Devices) Slew Rate Characteristic Typical Range (V/ns) Minimum (V/ns) Maximum (V/ns) (Table d.) (Table e.) Note Pullup Slew Rate 1.2 - 2.5 1.0 4.5 1,3,4,6,7,8 Pulldown Slew Rate 1.2 - 2.5 1.0 4.5 2,3,4,6,7,8 Output Slew Rate Characteristics (for x16 Device) (Table f.) Slew Rate Characteristic Typical Range (V/ns) Minimum (V/ns) Maximum (V/ns) Note Pullup Slew Rate 1.2 - 2.5 1.0 4.5 1,3,4,6,7,8 Pulldown Slew Rate 1.2 - 2.5 1.0 4.5 2,3,4,6,7,8 Output Slew Rate Matching Ratio Characteristics Slew Rate Characteristic DDR266A (Table g.) DDR266B DDR200 Parameter min max min max min max Output Slew Rate Matching Ratio (Pullup to Pulldown) - - - - 0.71 1.4 Rev. 13 1.1 / May. Note 5,12 2005 200pin Unbuffered DDR SDRAM SO-DIMMs Note: 1. Pullup slew rate is characterized under the test conditions as shown in below Figure. Test Point Output (VOUT) 50 Ω VSSQ Figure: Pullup Slew rate 2. Pulldown slew rate is measured under the test conditions shown in below Figure. VDDQ 50Ω Output (VOUT) Test Point Figure: Pulldown Slew rate 3. Pullup slew rate is measured between (VDDQ/2 - 320 mV ± 250mV) Pulldown slew rate is measured between (VDDQ/2 + 320mV ± 250mV) Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output switching. Example: For typical slew, DQ0 is switching For minimum slew rate, all DQ bits are switching worst case pattern For maximum slew rate, only one DQ is switching from either high to low, or low to high. The remaining DQ bits remain the same as for previous state. 4. Evaluation conditions Typical: 25 oC (Ambient), VDDQ = nominal, typical process Minimum: 70 oC (Ambient), VDDQ = minimum, slow-slow process Maximum: 0 oC (Ambient), VDDQ = Maximum, fast-fast process 5. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. 6. Verified under typical conditions for qualification purposes. 7. TSOP-II package devices only. 8. Only intended for operation up to 256 Mbps per pin. 9. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5 V/ns as shown in Table b. The Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. 10. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables c & d. Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, fall rate. Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(slew Rate2)} For example: If Slew Rate 1 is 0.5 V/ns and Slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is -0.5 ns/V. Using the table given, this would result in the need for an increase in tDS and tDH of 100ps. 11. Table c is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser of the AC-AC slew rate and the DC-DC slew rate. The input slew rate is based on the lesser of the slew rates determined by either VIH(ac) to VIL(AC) or VIH(DC) to VIL(DC), and similarly for rising transitions. 12. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions through the DC region must be monotonic. Rev. 14 1.1 / May. 2005 200pin Unbuffered DDR SDRAM SO-DIMMs SIMPLIFIED COMMAND TRUTH TABLE Command CKEn-1 CKEn /CS /RAS /CAS /WE ADDR A10/AP BA Note Extended Mode Register Set H X L L L L OP code 1,2 Mode Register Set H X L L L L OP code 1,2 H X X 1 H Device Deselect No Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Read Burst Stop Auto Refresh Entry Self Refresh Precharge Power Down Mode Active Power Down Mode H X X X L H H H X L L H H H X L H L H CA H X L H L L CA H X L L H L X H X L H H L X 1 H H L L L H X 1 H L L L L H H X X X L H H H Exit L H Entry H L Exit L H Entry H L Exit L H RA V L H L H V V H X L V 1 1 1,3 1 1,4 1,5 1 1 X 1 H X X X 1 L H H H 1 H X X X L H H H H X X X L V V V X 1 1 1 X 1 X 1 ( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation ) Note : 1. DM states are Don’t Care. Refer to below Write Mask Truth Table. 2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Registering during Extended MRS or MRS. Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP period from Prechagre command. 3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+tRP). 4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+1+tWR+tRP). Write Recovery Time(tWR) is needed to guarantee that the last data has been completely written. 5. If A10/AP is High when Row Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged. WRITE MASK TRUTH TABLE CKEn-1 CKEn /CS, /RAS, /CAS, /WE DM Data Write Function H X X L ADDR A10/AP X BA Note 1 Data-In Mask H X X H X 1 Note: 1. Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data. In case of x16 data I/O, LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15) respectively. Rev. 15 1.1 / May. 2005 200pin Unbuffered DDR SDRAM SO-DIMMs PACKAGE DIMENSIONS 512MB, 64M x 64 Unbuffered SO-DIMM: HYMD564M646B[L][P]6 Front Millimeters Inches Unit: 67.60 mm 2.00 mm Component Keepout Area 2.00 mm 31.75 mm 20.00 mm 1 39 41 199 Back 2.0 mm 2 40 Side 2.0 mm 42 200 3.8mm MAX. (Front) 1.1mm MAX. Rev. 16 1.1 / May. 2005 200pin Unbuffered DDR SDRAM SO-DIMMs REVISION HISTORY Revision History Date 1.0 First Version Release - Datasheet coverage is changed from an individual module part to a component based module family Feb. 2005 1.1 Currected PIN DESCRIPTION and PIN ASSIGNMENT Tables May. 2005 Rev. 17 1.1 / May. Remark 2005