INFINEON HYS64D16301GU-6-B

D a t a S he et , V 1. 1, J u l y 2 00 3
HYS[64/72]D64x20GU-x-B
HYS[64/72]D32x00[G/E]U-x-B
HYS64D16301GU-x-B
1 8 4 - P i n U n b u f f er e d D u a l - I n- L i n e M e m o r y M o d u l es
U D IM M
DDR SDRAM
M e m or y P r o du c t s
N e v e r
s t o p
t h i n k i n g .
Edition 2003-07
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2003.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
D a t a S he et , V 1. 1, J u l y 2 00 3
HYS[64/72]D64x20GU-x-B
HYS[64/72]D32x00[G/E]U-x-B
HYS64D16301GU-x-B
1 8 4 - P i n U n b u f f er e d D u a l - I n- L i n e M e m o r y M o d u l es
U D IM M
DDR SDRAM
M e m or y P r o du c t s
N e v e r
s t o p
t h i n k i n g .
HYS[64/72]D64x20GU-x-B, HYS[64/72]D32x00[G/E]U-x-B, HYS64D16301GU-x-B
Revision History:
V1.1
2003-07
Previous Version:
V1.01
2003-01
Page
Subjects (major changes since last revision)
all
new data sheet template
all
replace bank by rank if DIMM related (4 bank SDRAM on 1 or 2 rank DIMM)
10
Table 6: Address Table updated
19ff
Table 10ff: IDD conditions now in seperate table
20ff
Table 11ff: added part numbers to IDD tables
24f
Table 15: split in two tables (now 15 & 16)
26f
Table 16: add –5 (DDR400)
29ff
Chapter 4: added part numbers to SPD tables
41ff
Table 21: set Bytes 47-55 to not used (00hex); set byte 62 to SPD rev. 0.0 (00hex); update
Checksum (TPCR)
8
Table 4: Changed RAS/CAS/WE description to command inputs and amended CLK to CK
9
Table 5: Changed CLK to CK
44ff
Figure 7 - Figure 13 Amended and updated package outline drawings
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
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Template: mp_a4_v2.0_2003-06-06.fm
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
3.1
3.2
3.3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Conditions and Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Data Sheet
5
17
17
19
24
V1.1, 2003-07
184-Pin Unbuffered Dual-In-Line Memory Modules
UDIMM
1
Overview
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
HYS[64/72]D64x20GU-x-B
HYS[64/72]D32x00[G/E]U-x-B
HYS64D16301GU-x-B
184-Pin Unbuffered Dual-In-Line Memory Modules (ECC and non-parity) for PC and Server main memory
applications
One rank 16M x 64, 32M × 64, 32M × 72 and two ranks 64M × 64, 64M × 72 organization
JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) Single +2.5V (±0.2V) power supply
Built with 256 Mbit DDR SDRAM in P-TSOPII-66-1 package
Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_2 compatible
Serial Presence Detect with E2PROM
JEDEC standard MO-206 form factor: 133.35 mm × 31.75 mm × 4.00 mm max.
Jedec standard reference layout
Gold plated contacts
DDR400 Speed Grade supported
Lead- & halogene-free DIMM available
Table 1
Performance
Part Number Speed Code
–5
–6
–7F
–7
–8
Unit
Module Speed Grade
DDR400B
DDR333B
DDR266
DDR266A
DDR200
–
Component Module
PC3200
-3033
PC2700
-2533
PC2100
-2022
PC2100
-2033
PC1600
-2022
–
200
166
–
–
–
MHz
166
166
143
143
125
MHz
133
133
133
133
100
MHz
max. Clock
Frequency
1.2
fCK3
@ CL = 2.5 fCK2.5
@ CL = 2
fCK2
@ CL = 3
Description
The HYS[64/72]D64x20GU-x-B, HYS[64/72]D32x00[G/E]U-x-B, and HYS64D16301GU-x-B are industry standard
184-Pin Unbuffered Dual-In-Line Memory Modules (UDIMM) organized as 32M × 64 and 64M × 64 for non-parity
and 32M × 72 and 64M × 72 for ECC main memory applications. The memory array is designed with 256Mbit
Double Data Rate Synchronous DRAMs. A variety of decoupling capacitors are mounted on the printed
circuit board. The DIMMs feature serial presence detect (SPD) based on a serial E2PROM device using the 2-pin
I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available
to the customer
Data Sheet
6
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Overview
Table 2
Ordering Information
Type
Compliance Code
Description
SDRAM Technology
HYS64D16301GU-5-B
PC3200U-30330-C0
one rank 128MB DIMM
256 Mbit (× 16)
HYS64D32300GU-5-B
PC3200U-30330-A0
one rank 256MB DIMM
256 Mbit (× 8)
HYS72D32300GU-5-B
PC3200U-30330-A0
one rank 256MB ECC-DIMM
256 Mbit (× 8)
256 Mbit (× 8)
PC3200 (CL=3)
HYS64D64320GU-5-B
PC3200U-30330-B0
two ranks 512MB DIMM
HYS72D64320GU-5-B
PC3200U-30330-B0
two ranks 512MB ECC-DIMM 256 Mbit (× 8)
HYS64D16301GU-6-B
PC2700U-25330-C0
one rank 128MB DIMM
256 Mbit (× 16)
HYS64D32300GU-6-B
PC2700U-25330-A0
one rank 256MB DIMM
256 Mbit (× 8)
HYS72D32300GU-6-B
PC2700U-25330-A0
one rank 256MB ECC-DIMM
256 Mbit (× 8)
HYS64D64320GU-6-B
PC2700U-25330-B0
two ranks 512MB DIMM
256 Mbit (× 8)
HYS72D64320GU-6-B
PC2700U-25330-B0
two ranks 512MB ECC-DIMM 256 Mbit (× 8)
HYS64D16301GU-7-B
PC2100U-20330-C2
one rank 128MB DIMM
256 Mbit (× 16)
HYS64D32000GU-7-B
PC2100U-20330-A1
one rank 256MB DIMM
256 Mbit (× 8)
HYS72D32000GU-7F-B
PC2100U-20220-A1
one rank 256MB ECC-DIMM
256 Mbit (× 8)
HYS72D32000GU-7-B
PC2100U-20330-A1
one rank 256MB ECC-DIMM
256 Mbit (× 8)
HYS64D64020GU-7-B
PC2100U-20330-B1
two ranks 512MB DIMM
256 Mbit (× 8)
HYS72D64020GU-7F-B
PC2100U-20220-B1
two ranks 512MB ECC-DIMM 256 Mbit (× 8)
HYS72D64020GU-7-B
PC2100U-20330-B1
two ranks 512MB ECC-DIMM 256 Mbit (× 8)
HYS64D16301GU-8-B
PC1600U-20330-C2
one rank 128MB DIMM
256 Mbit (× 16)
HYS64D32000GU-8-B
PC1600U-20220-A1
one rank 256MB DIMM
256 Mbit (× 8)
HYS72D32000GU-8-B
PC1600U-20220-A1
one rank 256MB ECC-DIMM
256 Mbit (× 8)
HYS64D64020GU-8-B
PC1600U-20220-B1
two ranks 512MB DIMM
256 Mbit (× 8)
HYS72D64020GU-8-B
PC1600U-20220-B1
two ranks 512MB ECC-DIMM 256 Mbit (× 8)
PC2700 (CL=2.5)
PC2100 (CL=2)
PC1600 (CL=2)
Table 3
Lead- and Halogene-Free DIMM
Type
Compliance Code
Description
SDRAM Technology
PC2100U-20330-A1
one rank 256MB DIMM
256 Mbit (× 8)
PC2100 (CL=2)
HYS64D32300EU-7-B
Note: All part numbers end with a place code designating the silicon-die revision. Reference information available
on request. Example: HYS72D32000GU-6-B, indicating rev. B dies are used for SDRAM components. The
Compliance Code is printed on the module labels describing the speed sort (for example “PC2700”), the
latencies and SPD code definition (for example “20330” means CAS latency of 2.0 clocks, RCD1) latency of
3 clocks, Row Precharge latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card
used for this module.
1) RCD: Row-Column-Delay
Data Sheet
7
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Pin Configuration
2
Pin Configuration
Table 4
Pin Definitions and Functions
Symbol
Type1)
Function
A0 - A12
I
Address Inputs
BA0, BA1
I
Bank Selects
DQ0 - DQ63
I/O
Data Input/Output
CB0 - CB7
I/O
Check Bits (× 72 organization only)
RAS, CAS, WE
I
Command Inputs
CKE0 - CKE1
I
Clock Enable
DQS0 - DQS8
I/O
SDRAM low data strobes
CK0 - CK2,
I
SDRAM clock (positive lines)
CK0 - CK2
I
SDRAM clock (negative lines)
DM0 - DM8
DQS9 - DQS17
I
I/O
SDRAM low data mask/
high data strobes
S0, S1
I
Chip Selects for Rank0 and Rank1
VDD
PWR
Power (+2.5 V)
VSS
GND
Ground
VDDQ
PWR
I/O Driver power supply
VDDID
PWR
VDD Indentification flag
VREF
AI
I/O reference supply
VDDSPD
PWR
Serial EEPROM power supply
SCL
I
Serial bus clock
SDA
I/O
Serial bus data line
SA0 - SA2
I
slave address select
NC
NC
Not Connected
1) I: Input; O: Output; I/O: bidirectional In-/Output; AI: Analog Input; PWR: Power Supply; GND: Signal Ground; NC: Not
Connected
Note: S1 and CKE1 are used on two rank modules only
Data Sheet
8
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Pin Configuration
Table 5
Pin Configuration
Frontside
Backside
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
1
VREF
48
A0
93
VSS
140
NC /
DM8/DQS17
2
DQ0
49
NC / CB2
94
DQ4
141
A10
3
VSS
50
VSS
95
DQ5
142
NC / CB6
4
DQ1
51
NC / CB3
96
VDDQD
143
VDDQD
5
DQS0
52
BA1
97
DM0/DQS9
144
NC / CB7
6
DQ2
98
DQ6
7
VDD
99
DQ7
8
DQ3
53
DQ32
100
VSS
145
VSS
9
NC
54
VDDQ
101
NC
146
DQ36
10
NC
55
DQ33
102
NC
147
DQ37
11
VSS
56
DQS4
103
NC
148
VDD
12
DQ8
57
DQ34
104
VDDQ
149
DM4/DQS13
13
DQ9
58
VSS
105
DQ12
150
DQ38
14
DQS1
59
BA0
106
DQ13
151
DQ39
15
VDDQ
60
DQ35
107
DM1/DQS10
152
VSS
16
CK1
61
DQ40
108
VDD
153
DQ44
17
CK1
62
VDDQ
109
DQ14
154
RAS
18
VSS
63
WE
110
DQ15
155
DQ45
19
DQ10
64
DQ41
111
CKE1
156
VDDQ
Key
Key
20
DQ11
65
CAS
112
VDDQ
157
S0
21
CKE0
66
VSS
113
NC (BA2)
158
S1
22
VDDQ
67
DQS5
114
DQ20
159
DM5/DQS14
23
DQ16
68
DQ42
115
NC / A12
160
VSS
24
DQ17
69
DQ43
116
VSS
161
DQ46
25
DQS2
70
VDD
117
DQ21
162
DQ47
26
VSS
71
NC
118
A11
163
NC
27
A9
72
DQ48
119
DM2/DQS11
164
VDDQ
28
DQ18
73
DQ49
120
VDD
165
DQ52
29
A7
74
VSS
121
DQ22
166
DQ53
30
VDDQ
75
CK2
122
A8
167
NC (A13)
31
DQ19
76
CK2
123
DQ23
168
VDD
32
A5
77
VDDQ
124
VSS
169
DM6/DQS15
33
DQ24
78
DQS6
125
A6
170
DQ54
34
VSS
79
DQ50
126
DQ28
171
DQ55
35
DQ25
80
DQ51
127
DQ29
172
VDDQ
36
DQS3
81
VDDQ
173
NC
A4
82
VSS
VDDID
128
37
129
DM3/DQS12
174
DQ60
38
VDD
83
DQ56
130
A3
175
DQ61
39
DQ26
84
DQ57
131
DQ30
176
VSS
Data Sheet
9
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Pin Configuration
Table 5
Pin Configuration (cont’d)
Frontside
Backside
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
40
DQ27
85
VDD
132
VSS
177
DM7/DQS16
41
A2
86
DQS7
133
DQ31
178
DQ62
42
VSS
87
DQ58
134
NC / CB4
179
DQ63
43
A1
88
DQ59
135
NC / CB5
180
VDDQ
44
NC / CB0
89
VSS
136
VDDQ
181
SA0
45
NC / CB1
90
NC
137
CK0
182
SA1
46
VDD
91
SDA
138
CK0
183
SA2
47
NC / DQS8
92
SCL
139
VSS
184
VDDSPD
Note: Pins 44, 45, 47, 49, 51, 134, 135, 140 and 144 are NC (“not connected”) on × 64 organised non-ECC
modules.
Table 6
Density
Address Format
Organization
Memory
Ranks
SDRAMs
# of
SDRAMs
# of row/bank/
columns bits
Refresh
Period
Interval
128MB
16M × 64
1
16M × 16
4
13/2/10
8K
64 ms
7.8 µs
256MB
32M × 64
1
32M × 8
8
13/2/11
8K
64 ms
7.8 µs
256MB
32M × 72
1
32M × 8
9
13/2/11
8K
64 ms
7.8 µs
512MB
64M × 64
2
32M × 8
16
13/2/11
8K
64 ms
7.8 µs
512MB
64M × 72
2
32M × 8
18
13/2/11
8K
64 ms
7.8 µs
Data Sheet
10
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Pin Configuration
S0
DQS1
DM1/DQS10
LDQS
LDM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS0
DM0/DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS3
DM3/DQS12
DQS2
DM2/DQS11
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQS5
DM5/DQS14
S
D0
DQS4
DM4/DQS13
LDQS
LDM
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS7
DM7/DQS16
S
D1
DQS6
DM6/DQS15
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
SCL
SPD
VDD /VDDQ
D0 - D3
VREF
D0 - D3
VSS
D0 - D3
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
D2
S
D3
* Clock Wiring
Clock
SDRAMs
Input
Serial PD
VDD SPD
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
S
SDA
WP
A0
A1
A2
SA0
SA1
SA2
*CK0/CK0
*CK1/CK1
*CK2/CK2
NC
2 SDRAMs
2 SDRAMs
* Wire per Clock Loading
Table/Wiring Diagrams
CAS
CAS: SDRAMs D0 - D3
CKE0
CKE: SDRAMs D0 - D3
Notes:
1. DQ-to-I/O wiring is shown as recommended but may
be changed.
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 ohms ± 5%.
4. VDDID strap connections
(for memory device VDD, VDDQ ):
STRAP OUT (OPEN): V DD = VDDQ
STRAP IN (VSS): V DD ≠ VDDQ
WE
WE: SDRAMs D0 - D3
5. BAx, Ax, RAS, CAS, WE resistors: 7.5 ohms ± 5%
VDDID
BA0 - BA1
A0 - A13
RAS
Figure 1
Data Sheet
Strap: see Note 4
BA0-BA1: SDRAMs D0 - D3
A0-A13: SDRAMs D0 - D3
RAS: SDRAMs D0 - D3
Block Diagram - One Rank 16M × 64 DDR SDRAM DIMM HYS64D16301GU using × 16
organized SDRAMs
11
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Pin Configuration
S0
DQS0
DM0/DQS9
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS4
DM4/DQS13
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
S
D0
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS
S
D1
D4
S
DQS
D5
DQS6
DM6/DQS15
DQS2
DM2/DQS11
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
S
DQS
D2
S
DQS
D6
DQS7
DM7/DQS16
DQS3
DM3/DQS12
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
S
DQS
D3
Serial PD
SCL
SDA
WP
A0
A1
A2
SA0
SA1
SA2
S
DQS
D7
* Clock Wiring
Clock
SDRAMs
Input
*CK0/CK0
*CK1/CK1
*CK2/CK2
2 SDRAMs
3 SDRAMs
3 SDRAMs
* Wire per Clock Loading
Table/Wiring Diagrams
BA0 - BA1
BA0-BA1: SDRAMs D0 - D7
A0 - A13
A0-A13: SDRAMs D0 - D7
RAS
RAS: SDRAMs D0 - D7
CAS
CAS: SDRAMs D0 - D7
VDD SPD
CKE0
CKE: SDRAMs D0 - D7
VDD/VDDQ
D0 - D7
WE
WE: SDRAMs D0 - D7
VREF
D0 - D7
SPD
VSS
D0 - D7
VDDID
Data Sheet
DQS
DQS5
DM5/DQS14
DQS1
DM1/DQS10
Figure 2
S
Strap: see Note 4
Notes:
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 ohms ± 5%
4. VDDID strap connections
(for memory device VDD , V DDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD ≠ VDDQ .
5. BAx, Ax, RAS, CAS, WE resistors: 5.1 ohms
+5%
Block Diagram - One Rank 32M × 64 DDR-I SDRAM DIMM HYS64D32x00GU / HYS64D32300EU
using × 8 organized SDRAMs
12
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Pin Configuration
S1
S0
DQS4
DM4/DQS13
DQS0
DM0/DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D0
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D8
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D1
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D9
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D2
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D10
VDD SPD
VDD/VDDQ
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D3
VSS
D0 - D15
BA0-BA1: SDRAMs D0 - D15
A0 - A13
A0-A13: SDRAMs D0 - D15
CKE: SDRAMs D8 - D15
RAS: SDRAMs D0 - D15
CAS
CAS: SDRAMs D0 - D15
CKE0
CKE: SDRAMs D0 - D7
WE
WE: SDRAMs D0 - D15
Data Sheet
S
DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D11
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
S
DQS
D12
DQS
D5
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D13
DQS
D6
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D14
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
D7
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D15
Serial PD
SCL
Strap: see Note 4
BA0 - BA1
Figure 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0 - D15
D0 - D15
CKE1
RAS
S
D4
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
SPD
VREF
VDDID
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS7
DM7/DQS16
DQS3
DM3/DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
S
DQS6
DM6/DQS15
DQS2
DM2/DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS5
DM5/DQS14
DQS1
DM1/DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
SDA
WP
A0
A1
A2
SA0
SA1
SA2
* Clock Wiring
Clock
SDRAMs
Input
*CK0/CK0
*CK1/CK1
*CK2/CK2
4 SDRAMs
6 SDRAMs
6 SDRAMs
* Wire per Clock Loading
Table/Wiring Diagrams
Notes:
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 ohms ± 5%.
4. VDDID strap connections
(for memory device VDD, V DDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): V DD ≠ VDDQ
5. BAx, Ax, RAS, CAS, WE resistors: 3 ohms
+5%
Block Diagram - Two Rank 64M × 64 DDR-I SDRAM DIMM HYS64D64x20GU using × 8
organized SDRAMs
13
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Pin Configuration
S0
DQS0
DM0/DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS4
DM4/DQS13
S
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
D0
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D1
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D2
S
DQS
D5
S
DQS
D6
DQS7
DM7/DQS16
DQS3
DM3/DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D3
DQS8
DM8/DQS17
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
RAS
D4
DQS6
DM6/DQS15
DQS2
DM2/DQS11
A0 - A13
DQS
DQS5
DM5/DQS14
DQS1
DM1/DQS10
BA0 - BA1
S
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
SCL
D8
RAS: SDRAMs D0 - D8
CAS
CAS: SDRAMs D0 - D8
CKE0
CKE: SDRAMs D0 - D8
WE
WE: SDRAMs D0 - D8
D7
SDA
WP
A0
A1
A2
SA0
SA1
SA2
*CK0/CK0
*CK1/CK1
*CK2/CK2
3 SDRAMs
3 SDRAMs
3 SDRAMs
* Wire per Clock Loading
Table/Wiring Diagrams
Notes:
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/S relationships must be
SPD
maintained as shown.
D0 - D8 3. DQ, DQS, DM/DQS resistors: 22 ohms ± 5%.
4. VDDID strap connections
D0 - D8
(for memory device VDD, V DDQ ):
D0 - D8
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): V DD ≠ VDDQ.
Strap: see Note 4
BA0-BA1: SDRAMs D0 - D8
A0-A13: SDRAMs D0 - D8
DQS
* Clock Wiring
Clock
SDRAMs
Input
Serial PD
DQS
S
VDDSPD
VDD/VDDQ
VREF
VSS
VDDID
5. BAx, Ax, RAS, CAS, WE resistors: 5.1 ohm
+5%
Figure 4
Data Sheet
Block Diagram - One Rank 32M × 72 DDR-I SDRAM DIMM HYS72D32x00GU using × 8
organized SDRAMs
14
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Pin Configuration
S1
S0
DQS4
DM4/DQS13
DQS0
DM0/DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
S
DQS
D9
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D1
DQS
S
D10
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
D2
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D11
A0 - A13
CKE1
RAS
CAS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
S
DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D12
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D5
DQS
D6
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
D8
DQS
S
D17
DQS
D7
D0 - D17
D0 - D17
VSS
D0 - D17
VDDID
Strap: see Note 4
A0-A13: SDRAMs D0 - D17
CAS: SDRAMs D0 - D17
S
VREF
BA0-BA1: SDRAMs D0 - D17
CKE: SDRAMs D9 - D17
RAS: SDRAMs D0 - D17
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
SPD
VDD/VDDQ
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
S
DQS
D13
S
DQS
D14
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D15
DQS7
DM7/DQS16
VDD SPD
DQS8
DM8/DQS17
BA0 - BA1
S
DQS
S
DQS3
DM3/DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D4
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS6
DM6/DQS15
DQS2
DM2/DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS
DQS5
DM5/DQS14
DQS1
DM1/DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
Serial PD
SCL
CKE0
CKE: SDRAMs D0 - D8
WP
A0
A1
A2
WE
WE: SDRAMs D0 - D17
SA0
SA1
SA2
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D16
* Clock Wiring
Clock
SDRAMs
Input
*CK0/CK0
*CK1/CK1
*CK2/CK2
6 SDRAMs
6 SDRAMs
6 SDRAMs
* Wire per Clock Loading
Table/Wiring Diagrams
Notes:
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 ohms ± 5%.
4. VDDID strap connections
SDA
(for memory device VDD, V DDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): V DD ≠ VDDQ
5. BAx, Ax, RAS, CAS, WE resistors: 3 ohms
+5%
Figure 5
Data Sheet
Block Diagram - Two Rank 64M × 72 DDR-I SDRAM DIMM HYS72D64x20GU using × 8
organized SDRAMs
15
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Pin Configuration
6 DRAM Loads
DRAM1
DRAM2
CK R = 120 Ω ± 5%
DIMM
Connector
DRAM3
4 DRAM Loads
DRAM4
CK
DRAM1
DRAM5
DRAM2
R = 120 Ω ± 5%
DRAM6
DIMM
Connector
Cap.
Cap.
3 DRAM Loads
R = 120 Ω ± 5%
DIMM
Connector
DRAM1
DRAM5
Cap.
DRAM6
DRAM3
Cap.
2 DRAM Loads
DRAM5
Cap.
Cap.
1 DRAM Loads
R = 120 Ω ± 5%
DIMM
Connector
Cap.
R = 120 Ω ± 5%
Cap.
Cap.
DRAM5
Cap.
DIMM
Connector
DRAM1
DRAM3
Cap.
Cap.
Cap.
Cap.
Cap. = 1/2 DDR SDRAM input capacitance; 1.0 pF ± 20%
Figure 6
Data Sheet
Clock Net Wiring
16
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
3
Electrical Characteristics
3.1
Operating Conditions
Table 7
Absolute Maximum Ratings
Parameter
Symbol
Voltage on I/O pins relative to VSS
VIN, VOUT
Values
min.
typ.
-0.5
–
max.
Unit Note/ Test
Condition
VDDQ +
V
–
0.5
Voltage on Inputs relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating Temperature (Ambient)
Storage Temperature
Power dissipation (per SDRAM component)
Short Circuit Output Current
VIN
VDD
VDDQ
TA
TSTG
PD
IOUT
-0.5
–
+3.6
V
–
-0.5
–
+3.6
V
–
-0.5
–
+3.6
V
–
0
–
+70
°C
–
-55
–
+150
°C
–
–
1
–
W
–
–
50
–
mA
–
Attention: Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. Functional
operation should be restricted to recommended operation conditions. Exceeding only one of
these values for extended periods of time affect device reliability and may cause irreversible
damage to the integrated circuit.
Table 8
Supply Voltage Levels
Parameter
Device Supply Voltage
Device Supply Voltage
Output Supply Voltage
Output Supply Voltage
Input Reference Voltage
Input Reference Voltage
Symbol Limit Values
VDD
VDD
VDDQ
VDDQ
VREF
VREF
Unit Note/ Test Condition
min.
nom.
max.
2.3
2.5
2.7
V
2.5
2.6
2.7
V
2.3
2.5
2.7
V
2.5
2.6
2.7
V
0.49 × VDDQ
0.5 × VDDQ 0.51 × VDDQ
VDDQ / 2 –50
VDDQ
/2
mV
VDDQ / 2 + 50
V
V
fCK ≤166 MHz
fCK > 166 MHz 1)
fCK ≤166 MHz 2)
fCK > 166 MHz 1)2)
fCK ≤166 MHz 3)
fCK > 166 MHz 1)3)
mV
Termination Voltage
VTT
VREF – 0.04
VREF
VREF + 0.04
V
4)
EEPROM supply voltage
VDDSPD
2.3
2.5
3.6
V
—
1) DDR400 conditions apply for all clock frequencies above 166 MHz
2) Under all conditions, VDDQ must be less than or equal to VDD.
3) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ.
4) VTT of the transmitting device must track VREF of the receiving device.
Data Sheet
17
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Table 9
DC Operating Conditions (SSTL_2 Inputs)
Parameter
DC Input Logic High
DC Input Logic Low
Input Leakage Current
Output Leakage Current
Symbol
VIH (DC)
VIL (DC)
IIL
IOL
Values
Unit
Note/ Test Condition 1)
min.
max.
VREF + 0.15
VDDQ + 0.3
V
2)
– 0.30
VREF – 0.15
V
–
–5
5
µA
3)
–5
5
µA
3)
1) VDDQ = 2.5 V, TA = 70 ° C, Voltage Referenced to VSS
2) The relationship between the VDDQ of the driving device and the VREF of the receiving device is what determines noise
margins. However, in the case of VIH (max.) (input overdrive), it is the VDDQ of the receiving device that is referenced. In the
case where a device is implemented such that it supports SSTL_2 inputs but has no SSTL_2 outputs (such as a translator),
and therefore no VDDQ supply voltage connection, inputs must tolerate input overdrive to 3.0 V (High corner
VDDQ + 300 mV).
3) For any pin under test input of 0 V ≤VIN ≤VDDQ + 0.3 V. Values are shown per DDR SDRAM component
Data Sheet
18
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
3.2
Current Conditions and Specification
Table 10
IDD Conditions
Parameter
Symbol
Operating Current 0
one bank; active/ precharge; tRC = tRC,MIN;
DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
IDD0
Operating Current 1
one bank; active/read/precharge; Burst Length = 4; see component data sheet.
IDD1
Precharge Power-Down Standby Current
all banks idle; power-down mode; CKE ≤VIL,MAX
IDD2P
Precharge Floating Standby Current
CS ≥ VIH,,MIN, all banks idle; CKE ≥ VIH,MIN;
address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM.
IDD2F
Precharge Quiet Standby Current
CS ≥ VIHMIN, all banks idle; CKE ≥ VIH,MIN;
address and other control inputs stable at ≥ VIH,MIN or ≤VIL,MAX; VIN = VREF for DQ, DQS and DM.
IDD2Q
Active Power-Down Standby Current
one bank active; power-down mode; CKE ≤VILMAX; VIN = VREF for DQ, DQS and DM.
IDD3P
Active Standby Current
one bank active; CS ≥ VIH,MIN; CKE ≥ VIH,MIN; tRC = tRAS,MAX;
DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle.
IDD3N
Operating Current Read
one bank active; Burst Length = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA
IDD4R
Operating Current Write
one bank active; Burst Length = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B
IDD4W
Auto-Refresh Current
tRC = tRFCMIN, distributed refresh
IDD5
Self-Refresh Current
CKE ≤0.2 V; external clock on
IDD6
Operating Current 7
four bank interleaving with Burst Length = 4; see component data sheet.
IDD7
Data Sheet
19
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Symbol
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
HYS64D32300GU–8–B
HYS72D32300GU–8–B
HYS64D64320GU–8–B
HYS72D64320GU–8–B
Operating, Standby and Refresh Currents (PC2100, –8)
HYS64D16301GU–8–B
Part Number & Organization
Table 11
128MB × 64
256MB × 64
256MB × 72
512MB × 64
512MB × 72
1 rank
1 rank
1 rank
2 ranks
2 ranks
Unit
Note1)2)
typ.
max.
typ.
max.
typ.
max.
typ.
max.
typ.
max.
288
380
560
720
630
810
880
1080
990
1215
mA
3)
332
420
640
800
720
900
960
1160
1080
1305
mA
3)4)
20
28
40
56
45
63
80
112
90
126
mA
5)
120
140
240
280
270
315
480
560
540
630
mA
5)
72
88
144
176
162
198
288
352
324
396
mA
5)
52
64
104
128
117
144
208
256
234
288
mA
5)
168
200
320
360
360
405
640
720
720
810
mA
5)
356
440
632
760
711
855
952
1120
1071
1260
mA
3)4)
384
480
680
840
765
945
1000
1200
1125
1350
mA
3)
504.8
680
1010
1360
1136
1530
1330
1720
1496
1935
mA
3)
6
10
12
20
13.5
22.5
24
40
27
45
mA
5)
632
880
1200
1680
1350
1890
1520
2040
1710
2295
mA
3)4)
1) DRAM component currents only
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
3) The module IDDx values are calculated from the component IDDx data sheet values as:
m × IDDx[component] + n × IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load
conditions
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]
Data Sheet
20
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
HYS64D32300GU–7–B
HYS64D32300EU–7–B
HYS72D32300GU–7–B
HYS64D64320GU–7–B
HYS64D64320GU–7F–B
HYS72D64320GU–7–B
HYS72D64320GU–7F–B
Operating, Standby and Refresh Currents (PC2100, –7 & –7F)
HYS64D16301GU–7–B
Part Number & Organization
Table 12
128MB
× 64
256MB
× 64
256MB
× 72
512MB
× 64
512MB
× 72
512MB
× 72
512MB
× 72
1 rank
1 rank
1 rank
1 rank
1 rank
2 ranks
2 ranks
typ. max. typ.
max. typ.
max. typ.
max. typ.
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
308 420
600
800
675
900
747
990
376 460
720
880
810
990
882
1080 1120 1320 1260 1485 1332 1575 mA
22
44
64
49.5 72
49.5 72
88
128
99
144
99
144
mA
5)
140 160
280
320
315
360
315
360
560
640
630
720
630
720
mA
5)
80
100
160
200
180
225
180
225
320
400
360
450
360
450
mA
5)
60
72
120
144
135
162
135
162
240
288
270
324
270
324
mA
5)
208 240
400
440
450
495
450
495
800
880
900
990
900
990
mA
5)
428 520
760
920
855
1035 855
1035 1160 1360 1305 1530 1305 1530 mA
3)4)
476 560
840
1000 945
1125 945
1125 1240 1440 1395 1620 1395 1620 mA
3)
540 720
1080 1440 1215 1620 1217 1620 1480 1880 1665 2115 1667 2115 mA
3)
6
12
5)
10
720 940
20
max. typ.
1)2)
Symbol
32
max. typ.
Unit Note
max.
1000 1240 1125 1395 1197 1485 mA
13.5 22.5 13.5 22.5 24
40
27
45
27
45
mA
1369 1800 1540 2025 1540 2025 1769 2240 1990 2520 1990 2520 mA
3)
3)4)
3)4)
1) DRAM component currents only
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
3) The module IDDx values are calculated from the component IDDx data sheet values as:
m × IDDx[component] + n × IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load
conditions
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]
Data Sheet
21
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Symbol
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
HYS64D32300GU–6–B
HYS72D32300GU–6–B
HYS64D64320GU–6–B
HYS72D64320GU–6–B
Operating, Standby and Refresh Currents (PC2700, –6)
HYS64D16301GU–6–B
Part Number & Organization
Table 13
128MB × 64
256MB × 64
256MB × 72
512MB × 64
512MB × 72
1 rank
1 rank
1 rank
2 ranks
2 ranks
Unit Note
1)2)
typ.
max.
typ.
max.
typ.
max.
typ.
max.
typ.
max.
352
460
680
880
765
990
1160
1400
1305
1575
mA
3)
416
500
800
960
900
1080
1280
1480
1440
1665
mA
3)4)
24
36
48
72
54
81
96
144
108
162
mA
5)
180
220
360
440
405
495
720
880
810
990
mA
5)
98.8
112
197.6
224
222.3
252
395.2
448
444.6
504
mA
5)
72
84
144
168
162
189
288
336
324
378
mA
5)
252
280
480
520
540
585
960
1040
1080
1170
mA
5)
496
640
880
1120
990
1260
1360
1640
1530
1845
mA
3)4)
564
660
1000
1160
1125
1305
1480
1680
1665
1890
mA
3)
574
760
1148
1520
1292
1710
1628
2040
1832
2295
mA
3)
6
10
12
20
13.5
22.5
24
40
27
45
mA
5)
872
1140
1662
2160
1870
2430
2142
2680
2410
3015
mA
3)4)
1) DRAM component currents only
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
3) The module IDDx values are calculated from the component IDDx data sheet values as:
m × IDDx[component] + n × IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load
conditions
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]
Data Sheet
22
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Symbol
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
Operating, Standby and Refresh Currents (PC3200, –5)
HYS64D32300GU–5–B
HYS72D32300GU–5–B
HYS64D64320GU–5–B
HYS72D64320GU–5–B
Unit Note1)2)
HYS64D16301GU–5–B
Part Number & Organization
Table 14
128MB × 64
256MB × 64
256MB × 72
512MB × 64
512MB × 72
1 rank
1 rank
1 rank
2 ranks
2 ranks
typ.
max.
typ.
max.
typ.
max.
typ.
max.
typ.
max.
400
480
720
920
810
1035
1176
1472
132
1656
mA
3)
460
540
840
1000
945
1125
1296
1552
1458
1746
mA
3)4)
24
36
48
72
54
81
96
144
108
162
mA
5)
184
224
368
448
414
504
736
896
828
1008
mA
5)
96
136
192
272
216
306
384
544
432
612
mA
5)
68
96
136
192
153
216
272
384
306
432
mA
5)
240
296
456
552
513
621
912
1104
1026
1242
mA
5)
560
700
920
1160
1035
1305
1376
1712
1548
1926
mA
3)4)
600
720
1000
1200
1125
1350
1456
1752
1638
1971
mA
3)
620
780
1240
1560
1395
1755
1696
2112
1908
2376
mA
3)
6.4
10.4
12.8
20.8
14.4
23.4
25.6
41.6
28.8
46.8
mA
5)
1040
1240
1920
2240
2160
2520
2376
2792
2673
3141
mA
3)4)
1) DRAM component currents only
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
3) The module IDDx values are calculated from the component IDDx data sheet values as:
m × IDDx[component] + n × IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load
conditions
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]
Data Sheet
23
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
3.3
AC Characteristics
Table 15
AC Timing - Absolute Specifications –8/–7/–7F
Parameter
Symbol
DQ output access time from tAC
CK/CK
DQS output access time
from CK/CK
tDQSCK
tCH
CK low-level width
tCL
Clock Half Period
tHP
Clock cycle time
tCK3
tCK2.5
tCK2
tCK1.5
DQ and DM input hold time tDH
DQ and DM input setup
tDS
CK high-level width
–8
–7
–7F
DDR200
DDR266A
DDR266
Unit Note/
Test Condition 1)
Min.
Max.
Min.
Max.
Min.
Max.
–0.8
+0.8
–0.75
+0.75
–0.75
+0.75
ns
2)3)4)5)
–0.8
+0.8
–0.75
+0.75
–0.75
+0.75
ns
2)3)4)5)
0.45
0.55
0.45
0.55
0.45
0.55
2)3)4)5)
0.45
0.55
0.45
0.55
0.45
0.55
tCK
tCK
min. (tCL, tCH)
min. (tCL, tCH)
min. (tCL, tCH) ns
2)3)4)5)
2)3)4)5)
8
12
7
12
7
12
ns
CL = 3.0 2)3)4)5)
8
12
7
12
7
12
ns
CL = 2.5 2)3)4)5)
10
12
7.5
12
7.5
12
ns
CL = 2.0 2)3)4)5)
10
12
—
—
—
—
ns
CL = 1.5 2)3)4)5)
0.6
—
0.5
—
0.5
—
ns
2)3)4)5)
0.6
—
0.5
—
0.5
—
ns
2)3)4)5)
time
Control and Addr. input
pulse width (each input)
tIPW
2.5
—
2.2
—
2.2
—
ns
2)3)4)5)6)
DQ and DM input pulse
width (each input)
tDIPW
2.0
—
1.75
—
1.75
—
ns
2)3)4)5)6)
Data-out high-impedance
time from CK/CK
tHZ
–0.8
+0.8
–0.75
+0.75
–0.75
+0.75
ns
2)3)4)5)7)
Data-out low-impedance
time from CK/CK
tLZ
–0.8
+0.8
–0.75
+0.75
–0.75
+0.75
ns
2)3)4)5)7)
0.75
1.25
0.75
1.25
0.75
1.25
tCK
2)3)4)5)
Write command to 1st DQS tDQSS
latching transition
DQS-DQ skew (DQS and
associated DQ signals)
tDQSQ
—
+0.6
—
+0.5
—
+0.5
ns
2)3)4)5)
Data hold skew factor
tQHS
tQH
—
1.0
—
0.75
—
0.75
ns
2)3)4)5)
tHP –
tQHS
—
tHP –
tQHS
—
tHP –
tQHS
—
ns
2)3)4)5)
0.35
—
0.35
—
0.35
—
tCK
2)3)4)5)
tDSS
0.2
—
0.2
—
0.2
—
tCK
2)3)4)5)
DQS falling edge hold time tDSH
from CK (write cycle)
0.2
—
0.2
—
0.2
—
tCK
2)3)4)5)
Mode register set command tMRD
cycle time
2
—
2
—
2
—
tCK
2)3)4)5)
0
—
0
—
0
—
ns
2)3)4)5)8)
0.40
0.60
0.40
0.60
0.40
0.60
2)3)4)5)9)
0.25
—
0.25
—
0.25
—
tCK
tCK
DQ/DQS output hold time
DQS input low (high) pulse tDQSL,H
width (write cycle)
DQS falling edge to CK
setup time (write cycle)
Write preamble setup time
Write postamble
Write preamble
Data Sheet
tWPRES
tWPST
tWPRE
24
2)3)4)5)
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Table 15
AC Timing - Absolute Specifications –8/–7/–7F (cont’d)
Parameter
Address and control input
setup time
Symbol
tIS
–8
–7
–7F
DDR200
DDR266A
DDR266
Min.
Max.
Min.
Max.
Min.
Max.
1.1
—
0.9
—
0.9
—
Unit Note/
Test Condition 1)
ns
fast slew rate
3)4)5)6)10)
1.1
—
1.0
—
1.0
—
ns
slow slew rate
3)4)5)6)10)
Address and control input
hold time
tIH
1.1
—
0.9
—
0.9
—
ns
fast slew rate
3)4)5)6)10)
1.1
—
1.0
—
1.0
—
ns
slow slew rate
3)4)5)6)10)
CL > 1.5 2)3)4)5)
NA
tCK
tCK
NA
ns
2)3)4)5)12)
0.60
tCK
2)3)4)5)
45
120
E+3
ns
2)3)4)5)
—
60
—
ns
2)3)4)5)
75
—
75
—
ns
2)3)4)5)
—
20
—
15
—
ns
2)3)4)5)
20
—
20
—
15
—
ns
2)3)4)5)
tRPRE
tRPRE1.5
tRPRES
tRPST
tRAS
0.9
1.1
0.9
0.9
1.1
NA
1.5
—
NA
0.40
0.60
0.40
0.60
0.40
50
120
E+3
45
120
E+3
tRC
70
—
65
Auto-refresh to Active/Auto- tRFC
refresh command period
80
—
tRCD
20
Read preamble
Read preamble setup time
Read postamble
Active to Precharge
command
Active to Active/Autorefresh command period
Active to Read or Write
delay
Precharge command period tRP
1.1
0.9
1.1
CL = 1.5 2)3)4)5)11)
Active to Autoprecharge
delay
tRAP
20
—
20
—
15
—
ns
2)3)4)5)
Active bank A to Active
bank B command
tRRD
15
—
15
—
15
—
ns
2)3)4)5)
Write recovery time
tWR
tDAL
15
—
15
—
15
—
ns
2)3)4)5)
tCK
2)3)4)5)13)
CL > 1.5 2)3)4)5)
Auto precharge write
recovery + precharge time
tWTR
tWTR1.5
Exit self-refresh to non-read tXSNR
Internal write to read
command delay
(twr/tCK) + (trp/tCK)
1
—
1
—
1
—
2
—
—
—
—
—
tCK
tCK
80
—
75
—
75
—
ns
2)3)4)5)
CL = 1.5 2)3)4)5)
command
Exit self-refresh to read
command
tXSRD
200
—
200
—
200
—
tCK
2)3)4)5)
Average Periodic Refresh
Interval
tREFI
—
7.8
—
7.8
—
7.8
µs
2)3)4)5)14)
1) 0 ° C ≤TA ≤70 ° C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333, DDR266, and = 1 V/ns for DDR200
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
Data Sheet
25
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
measured between VOH(ac) and VOL(ac).
11) CAS Latency 1.5 operation is supported on DDR200 devices only
12) tRPRES is defined for CL = 1.5 operation only
13) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock
cycle time.
14) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Table 16
AC Timing - Absolute Specifications –6/–5
Parameter
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
Clock Half Period
Clock cycle time
DQ and DM input hold time
DQ and DM input setup time
Control and Addr. input pulse width (each
input)
Symbol
tAC
tDQSCK
tCH
tCL
tHP
tCK
tDH
tDS
tIPW
tDIPW
Data-out high-impedance time from CK/CK tHZ
Data-out low-impedance time from CK/CK tLZ
Write command to 1st DQS latching
tDQSS
DQ and DM input pulse width (each input)
–6
–5
DDR333
DDR400B
Unit Note/
Test Condition 1)
Min.
Max.
Min.
Max.
–0.7
+0.7
–0.6
+0.6
ns
2)3)4)5)
–0.6
+0.6
–0.5
+0.5
ns
2)3)4)5)
0.45
0.55
0.45
0.55
2)3)4)5)
0.45
0.55
0.45
0.55
tCK
tCK
min. (tCL, tCH) ns
2)3)4)5)
min. (tCL, tCH)
2)3)4)5)
6
12
5
12
ns
CL = 3.0 2)3)4)5)
6
12
6
12
ns
CL = 2.5 2)3)4)5)
7.5
12
7.5
12
ns
CL = 2.0 2)3)4)5)
0.45
—
0.4
—
ns
2)3)4)5)
0.45
—
0.4
—
ns
2)3)4)5)
2.2
—
tbd
—
ns
2)3)4)5)6)
1.75
—
tbd
—
ns
2)3)4)5)6)
–0.7
+0.7
–0.6
+0.6
ns
2)3)4)5)7)
–0.7
+0.7
–0.6
+0.6
ns
2)3)4)5)7)
0.75
1.25
0.75
1.25
tCK
2)3)4)5)
—
+0.40
—
+0.40
ns
TFBGA 2)3)4)5)
—
+0.45
—
+0.40
ns
TSOPII 2)3)4)5)
—
+0.50
—
+0.50
ns
TFBGA 2)3)4)5)
—
+0.55
—
+0.50
ns
TSOPII 2)3)4)5)
transition
DQS-DQ skew (DQS and associated DQ
signals)
tDQSQ
Data hold skew factor
tQHS
DQ/DQS output hold time
tQH
tHP –
tQHS
—
tHP –
tQHS
—
ns
2)3)4)5)
DQS input low (high) pulse width (write
cycle)
tDQSL,H
0.35
—
0.35
—
tCK
2)3)4)5)
Data Sheet
26
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Table 16
AC Timing - Absolute Specifications –6/–5 (cont’d)
Parameter
Symbol
–6
–5
DDR333
DDR400B
Min.
Max.
Min.
Max.
Unit Note/
Test Condition 1)
DQS falling edge to CK setup time (write
cycle)
tDSS
0.2
—
0.2
—
tCK
2)3)4)5)
DQS falling edge hold time from CK (write
cycle)
tDSH
0.2
—
0.2
—
tCK
2)3)4)5)
Mode register set command cycle time
tMRD
tWPRES
tWPST
tWPRE
tIS
2
—
2
—
tCK
2)3)4)5)
0
—
0
—
ns
2)3)4)5)8)
0.40
0.60
0.40
0.60
2)3)4)5)9)
0.25
—
0.25
—
tCK
tCK
0.75
—
0.6
—
ns
Write preamble setup time
Write postamble
Write preamble
Address and control input setup time
2)3)4)5)
fast slew rate
3)4)5)6)10)
0.8
—
NA
ns
slow slew rate
3)4)5)6)10)
Address and control input hold time
tIH
0.75
—
0.6
—
ns
fast slew rate
3)4)5)6)10)
0.8
—
NA
ns
slow slew rate
3)4)5)6)10)
tCK
tCK
2)3)4)5)
70E+3 40
70E+3 ns
2)3)4)5)
60
—
55
—
ns
2)3)4)5)
tRFC
72
—
65
—
ns
2)3)4)5)
tRCD
Precharge command period
tRP
Active to Autoprecharge delay
tRAP
Active bank A to Active bank B command tRRD
Write recovery time
tWR
Auto precharge write recovery + precharge tDAL
18
—
15
—
ns
2)3)4)5)
18
—
15
—
ns
2)3)4)5)
18
—
15
—
ns
2)3)4)5)
12
—
10
—
ns
2)3)4)5)
15
—
15
—
ns
2)3)4)5)
tCK
2)3)4)5)11)
Read preamble
Read postamble
Active to Precharge command
Active to Active/Auto-refresh command
period
Auto-refresh to Active/Auto-refresh
command period
tRPRE
tRPST
tRAS
tRC
0.9
1.1
0.9
1.1
0.40
0.60
0.40
0.60
42
Active to Read or Write delay
2)3)4)5)
time
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic Refresh Interval
tWTR
tXSNR
tXSRD
tREFI
1
—
1
—
tCK
2)3)4)5)
75
—
75
—
ns
2)3)4)5)
200
—
200
—
tCK
2)3)4)5)
—
7.8
—
7.8
µs
2)3)4)5)12)
1) 0 ° C ≤TA ≤70 ° C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
Data Sheet
27
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
measured between VOH(ac) and VOL(ac).
11) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock
cycle time.
12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
28
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
HYS72D32300GU–8–B
HYS64D64320GU–8–B
HYS72D64320GU–8–B
Operating, Standby and Refresh Currents (PC1600, –8)
HYS64D32300GU–8–B
Table 17
HYS64D16301GU–8–B
SPD Contents
Part Number & Organization
4
128MB
256MB
256MB
512MB
512MB
× 64
× 64
× 72
× 64
× 72
1 rank
1 rank
1 rank
2 ranks
2 ranks
Byte
Description
HEX
HEX
HEX
HEX
HEX
0
Number of SPD Bytes 128
80
80
80
80
80
1
Total Bytes in Serial
PD
256
08
08
08
08
08
2
Memory Type
DDR-SDRAM
07
07
07
07
07
3
Number of Row
Addresses
13
0D
0D
0D
0D
0D
4
Number of Column
Addresses
9/10
09
0A
0A
0A
0A
5
Number of DIMM
Banks
1/2
01
01
01
02
01
6
Module Data Width
× 64/× 72
40
40
48
40
48
7
Module Data Width
(cont’d)
0
00
00
00
00
00
8
Module Interface
Levels
SSTL_2.5
04
04
04
04
04
9
SDRAM Cycle Time at 8 ns
CL = 2.5
80
80
80
80
80
10
Access Time from
Clock at
CL = 2.5
0.8 ns
80
80
80
80
80
11
DIMM config
non-ECC/ECC
00
00
02
00
02
12
Refresh Rate/Type
Self-Refresh 7.8 µs
82
82
82
82
82
13
SDRAM Width,
Primary
× 16/ × 8
10
08
08
08
08
14
Error Checking
SDRAM Data Witdh
na/ × 8
00
00
08
00
08
15
Minimum Clock Delay tCCD = 1 CLK
for Back-to-Back
Random Column
Address
01
01
01
01
01
16
Burst Length
Supported
0E
0E
0E
0E
0E
Data Sheet
2, 4 & 8
29
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
HYS64D16301GU–8–B
HYS64D32300GU–8–B
HYS72D32300GU–8–B
HYS64D64320GU–8–B
HYS72D64320GU–8–B
Operating, Standby and Refresh Currents (PC1600, –8) (cont’d)
Part Number & Organization
Table 17
128MB
256MB
256MB
512MB
512MB
× 64
× 64
× 72
× 64
× 72
1 rank
1 rank
1 rank
2 ranks
2 ranks
HEX
HEX
HEX
HEX
HEX
Byte
Description
17
Number of SDRAM
Banks
4
04
04
04
04
04
18
Supported CAS
Latencies
CAS latency = 2 & 2.5 0C
0C
0C
0C
0C
19
CS Latencies
CS latency = 0
01
01
01
01
01
20
WE Latencies
Write latency = 1
02
02
02
02
02
21
SDRAM DIMM
Module Attributes
unbuffered
20
20
20
20
20
22
SDRAM Device
Attributes: General
−
C0
C0
C0
C0
C0
23
Min. Clock Cycle Time 10 ns
at CAS Latency = 2
A0
A0
A0
A0
A0
24
Access Time from
Clock for
CL = 2
80
80
80
80
80
25
Minimum Clock Cycle not supported
Time for CL = 1.5
00
00
00
00
00
26
Access Time from
Clock at
CL = 1.5
not supported
00
00
00
00
00
27
Minimum Row
Precharge Time
20 ns
50
50
50
50
50
28
Minimum Row Act. to 15 ns
Row Act. Delay tRRD
3C
3C
3C
3C
3C
29
Minimum RAS to CAS 20 ns
Delay tRCD
50
50
50
50
50
30
Minimum RAS Pulse
Width tRAS
32
32
32
32
32
31
Module Bank Density 256 MByte
(per Bank)
20
40
40
40
40
32
Addr. and Command
Setup Time
1.1 ns
B0
B0
B0
B0
B0
33
Addr. and Command 1.1 ns
Hold Time
B0
B0
B0
B0
B0
Data Sheet
0.8 ns
50 ns
30
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
HYS64D16301GU–8–B
HYS64D32300GU–8–B
HYS72D32300GU–8–B
HYS64D64320GU–8–B
HYS72D64320GU–8–B
Operating, Standby and Refresh Currents (PC1600, –8) (cont’d)
Part Number & Organization
Table 17
128MB
256MB
256MB
512MB
512MB
× 64
× 64
× 72
× 64
× 72
1 rank
1 rank
1 rank
2 ranks
2 ranks
Byte
Description
HEX
HEX
HEX
HEX
HEX
34
Data Input Setup Time 0.6 ns
60
60
60
60
60
35
Data Input Hold Time 0.6 ns
60
60
60
60
60
36 to 40
Superset Information
00
00
00
00
00
41
Minimum Core Cycle 70 ns
Time tRC
46
46
46
46
46
42
Min. Auto Refresh 80 ns
Cmd Cycle Time tFRC
50
50
50
48
50
43
Maximum Clock Cycle 12 ns
Time tCK
30
30
30
30
30
Max. DQS-DQ Skew 0.6 ns
3C
3C
3C
3C
3C
44
–
tDQSQ
45
X-Factor tQHS
1.0 ns
A0
A0
A0
A0
A0
46 to 61
Superset Information
–
00
00
00
00
00
62
SPD Revision
Revision 0.0
00
00
00
00
00
63
Checksum for Bytes 0 –
- 62
E8
A7
B9
A8
B9
64
Manufacturers
JEDEC ID Codes
–
C1
C1
C1
C1
C1
65 to 71
Manufacturer
–
Infineon
Infineon
Infineon
Infineon
Infineon
72
Module
Location
–
–
–
–
–
73 to 90
Module Part Number
–
–
–
–
–
–
91 to 92
Module
Code
Revision –
–
–
–
–
–
93 to 94
Module
Manufacturing Date
–
–
–
–
–
95 to 98
Module Serial Number –
–
–
–
–
–
99 to 127
–
–
–
–
–
–
–
Customer –
–
–
–
–
–
128 to 255 open
use
Data Sheet
for
Assembly –
–
31
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
HYS64D16301GU–7–B
HYS64D32300GU–7–B
HYS64D32300EU–7–B
HYS72D32300GU–7–B
HYS64D64320GU–7–B
HYS72D64320GU–7–B
SPD Codes for PC2100 Modules “–7”
Part Number & Organization
Table 18
128MB
256MB
256MB
512MB
512MB
× 64
× 64
× 72
× 64
× 72
1 rank
1 rank
1 rank
2 ranks
2 ranks
Byte
Description
HEX
HEX
HEX
HEX
HEX
0
Number of SPD Bytes 128
80
80
80
80
80
1
Total Bytes in Serial
PD
256
08
08
08
08
08
2
Memory Type
DDR-SDRAM
07
07
07
07
07
3
Number of Row
Addresses
13
0D
0D
0D
0D
0D
4
Number of Column
Addresses
9/10
09
0A
0A
0A
0A
5
Number of DIMM
Banks
1/2
01
01
01
02
01
6
Module Data Width
× 64/× 72
40
40
48
40
48
7
Module Data Width
(cont’d)
0
00
00
00
00
00
8
Module Interface
Levels
SSTL_2.5
04
04
04
04
04
9
SDRAM Cycle Time at 7 ns
CL = 2.5
70
70
70
70
70
10
Access Time from
Clock at
CL = 2.5
0.75 ns
75
75
75
75
75
11
DIMM config
non-ECC/ECC
00
00
02
00
02
12
Refresh Rate/Type
Self-Refresh 7.8 µs
82
82
82
82
82
13
SDRAM Width,
Primary
× 16/ × 8
10
08
08
08
08
14
Error Checking
SDRAM Data Witdh
na/ × 8
00
00
08
00
08
15
Minimum Clock Delay tCCD = 1 CLK
for Back-to-Back
Random Column
Address
01
01
01
01
01
16
Burst Length
Supported
2, 4 & 8
0E
0E
0E
0E
0E
17
Number of SDRAM
Banks
4
04
04
04
04
04
Data Sheet
32
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
HYS64D16301GU–7–B
HYS64D32300GU–7–B
HYS64D32300EU–7–B
HYS72D32300GU–7–B
HYS64D64320GU–7–B
HYS72D64320GU–7–B
SPD Codes for PC2100 Modules “–7” (cont’d)
Part Number & Organization
Table 18
128MB
256MB
256MB
512MB
512MB
× 64
× 64
× 72
× 64
× 72
1 rank
1 rank
1 rank
2 ranks
2 ranks
HEX
HEX
HEX
HEX
HEX
Byte
Description
18
Supported CAS
Latencies
CAS latency = 2 & 2.5 0C
0C
0C
0C
0C
19
CS Latencies
CS latency = 0
01
01
01
01
01
20
WE Latencies
Write latency = 1
02
02
02
02
02
21
SDRAM DIMM
Module Attributes
unbuffered
20
20
20
20
20
22
SDRAM Device
Attributes: General
−
C0
C0
C0
C0
C0
23
Min. Clock Cycle Time 7.5 ns
at CAS Latency = 2
75
75
75
75
75
24
Access Time from
Clock for
CL = 2
75
75
75
75
75
25
Minimum Clock Cycle not supported
Time for CL = 1.5
00
00
00
00
00
26
Access Time from
Clock at
CL = 1.5
not supported
00
00
00
00
00
27
Minimum Row
Precharge Time
20 ns
50
50
50
50
50
28
Minimum Row Act. to
Row Act. Delay tRRD
15 ns
3C
3C
3C
3C
3C
29
Minimum RAS to CAS 20 ns
Delay tRCD
50
50
50
50
50
30
Minimum RAS Pulse
Width tRAS
45 ns
2D
2D
2D
2D
2D
31
Module Bank Density
(per Bank)
128 MByte/256 MByte 20
40
40
40
40
32
Addr. and Command
Setup Time
0.9 ns
90
90
90
90
90
33
Addr. and Command 0.9 ns
Hold Time
90
90
90
90
90
34
Data Input Setup Time 0.5 ns
50
50
50
50
50
35
Data Input Hold Time
50
50
50
50
50
Data Sheet
0.75 ns
0.5 ns
33
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
HYS64D16301GU–7–B
HYS64D32300GU–7–B
HYS64D32300EU–7–B
HYS72D32300GU–7–B
HYS64D64320GU–7–B
HYS72D64320GU–7–B
SPD Codes for PC2100 Modules “–7” (cont’d)
Part Number & Organization
Table 18
128MB
256MB
256MB
512MB
512MB
× 64
× 64
× 72
× 64
× 72
1 rank
1 rank
1 rank
2 ranks
2 ranks
HEX
HEX
HEX
HEX
HEX
00
00
00
00
00
Byte
Description
36 to 40
Superset Information
41
Minimum Core Cycle 65 ns
Time tRC
41
41
41
41
41
42
Min. Auto Refresh 75 ns
Cmd Cycle Time tFRC
4B
4B
4B
4B
4B
43
Maximum Clock Cycle 12 ns
Time tCK
30
30
30
30
30
Max. DQS-DQ Skew 0.5 ns
32
32
32
32
32
44
–
tDQSQ
45
X-Factor tQHS
0.75 ns
75
75
75
75
75
46 to 61
Superset Information
–
00
00
00
00
00
62
SPD Revision
Revision 0.0
00
00
00
00
00
63
Checksum for Bytes 0 –
- 62
99
B2
C4
B3
C4
64
Manufacturers
JEDEC ID Codes
–
C1
C1
C1
C1
C1
65 to 71
Manufacturer
–
Infineon
Infineon
Infineon
Infineon
Infineon
72
Module
Location
–
–
–
–
–
73 to 90
Module Part Number
–
–
–
–
–
–
91 to 92
Module
Code
Revision –
–
–
–
–
–
93 to 94
Module Manufacturing –
Date
–
–
–
–
–
95 to 98
Module Serial Number –
–
–
–
–
–
99 to 127
–
–
–
–
–
–
–
Customer –
–
–
–
–
–
128 to 255 open
use
Data Sheet
for
Assembly –
34
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
HYS72D32300GU–7F–B
HYS64D64320GU–7F–B
SPD Codes for PC2100 Modules “–7F”
Part Number & Organization
Table 19
256MB
512MB
× 72
× 72
1 rank
1 rank
HEX
HEX
Byte
Description
0
Number of SPD Bytes
128
80
80
1
Total Bytes in Serial PD
256
08
08
2
Memory Type
DDR-SDRAM
07
07
3
Number of Row Addresses
13
0D
0D
4
Number of Column
Addresses
9/10
0A
0A
5
Number of DIMM Banks
1/2
01
02
6
Module Data Width
× 64/× 72
48
48
7
Module Data Width (cont’d)
0
00
00
8
Module Interface Levels
SSTL_2.5
04
04
9
SDRAM Cycle Time at
CL = 2.5
7 ns
70
70
10
Access Time from Clock at
CL = 2.5
0.75 ns
75
75
11
DIMM config
non-ECC/ECC
02
02
12
Refresh Rate/Type
Self-Refresh 7.8 µs
82
82
× 16/ × 8
08
08
08
08
13
SDRAM Width, Primary
14
Error Checking SDRAM Data na/ × 8
Witdh
15
Minimum Clock Delay for
Back-to-Back Random
Column Address
tCCD = 1 CLK
01
01
16
Burst Length Supported
2, 4 & 8
0E
0E
17
Number of SDRAM Banks
4
04
04
18
Supported CAS Latencies
CAS latency = 2 & 2.5
0C
0C
19
CS Latencies
CS latency = 0
01
01
20
WE Latencies
Write latency = 1
02
02
21
SDRAM DIMM Module
Attributes
unbuffered
20
20
22
SDRAM Device Attributes:
General
−
C0
C0
Data Sheet
35
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
HYS72D32300GU–7F–B
HYS64D64320GU–7F–B
SPD Codes for PC2100 Modules “–7F” (cont’d)
Part Number & Organization
Table 19
256MB
512MB
× 72
× 72
1 rank
1 rank
HEX
HEX
Byte
Description
23
Min. Clock Cycle Time at
CAS Latency = 2
7.5 ns
75
75
24
Access Time from Clock for
CL = 2
0.75 ns
75
75
25
Minimum Clock Cycle Time
for CL = 1.5
not supported
00
00
26
Access Time from Clock at
CL = 1.5
not supported
00
00
27
Minimum Row Precharge
Time
15 ns
3C
3C
28
Minimum Row Act. to Row
Act. Delay tRRD
15 ns
3C
3C
Minimum RAS to CAS Delay 15 ns
3C
3C
45 ns
2D
2D
29
tRCD
30
Minimum RAS Pulse Width
tRAS
31
Module Bank Density (per
Bank)
128 MByte/256 MByte
40
40
32
Addr. and Command Setup
Time
0.9 ns
90
90
33
Addr. and Command Hold 0.9 ns
Time
90
90
34
Data Input Setup Time
0.5 ns
50
50
35
Data Input Hold Time
0.5 ns
50
50
36 to 40
Superset Information
–
41
Minimum Core Cycle Time 60 ns
00
00
3C
3C
tRC
42
Min. Auto Refresh Cmd Cycle 75 ns
Time tFRC
4B
4B
43
Maximum Clock Cycle Time 12 ns
30
30
tCK
44
Max. DQS-DQ Skew tDQSQ
0.5 ns
32
32
45
X-Factor tQHS
0.75 ns
75
75
Data Sheet
36
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
HYS72D32300GU–7F–B
HYS64D64320GU–7F–B
SPD Codes for PC2100 Modules “–7F” (cont’d)
Part Number & Organization
Table 19
256MB
512MB
× 72
× 72
1 rank
1 rank
HEX
HEX
Byte
Description
46 to 61
Superset Information
–
00
00
62
SPD Revision
Revision 0.0
00
00
63
Checksum for Bytes 0 - 62
–
97
98
64
Manufactures
Codes
ID –
C1
C1
65 to 71
Manufacturer
Infineon
Infineon
72
Module Assembly Location
–
–
–
73 to 90
Module Part Number
–
–
–
91 to 92
Module Revision Code
–
–
–
93 to 94
Module Manufacturing Date
–
–
–
95 to 98
Module Serial Number
–
–
–
99 to 127
–
–
–
–
–
–
–
JEDEC
128 to 255 open for Customer use
Data Sheet
–
37
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
HYS64D16301GU–6–B
HYS64D32300GU–6–B
HYS72D32300GU–6–B
HYS64D64320GU–6–B
HYS72D64320GU–6–B
SPD Codes for PC2700 Modules “–6”
Part Number & Organization
Table 20
128MB
256MB
256MB
512MB
512MB
× 64
× 64
× 72
× 64
× 72
1 rank
1 rank
1 rank
2 ranks
2 ranks
Byte
Description
HEX
HEX
HEX
HEX
HEX
0
Number of SPD Bytes 128
80
80
80
80
80
1
Total Bytes in Serial
PD
256
08
08
08
08
08
2
Memory Type
DDR-SDRAM
07
07
07
07
07
3
Number of Row
Addresses
13
0D
0D
0D
0D
0D
4
Number of Column
Addresses
9/10
09
0A
0A
0A
0A
5
Number of DIMM
Banks
1/2
01
01
01
02
01
6
Module Data Width
× 64/× 72
40
40
48
40
48
7
Module Data Width
(cont’d)
0
00
00
00
00
00
8
Module Interface
Levels
SSTL_2.5
04
04
04
04
04
9
SDRAM Cycle Time at 6 ns
CL = 2.5
60
60
60
60
60
10
Access Time from
Clock at
CL = 2.5
0.75 ns
70
70
70
70
70
11
DIMM config
non-ECC/ECC
00
00
02
00
02
12
Refresh Rate/Type
Self-Refresh 7.8 µs
82
82
82
82
82
13
SDRAM Width,
Primary
× 16/ × 8
10
08
08
08
08
14
Error Checking
SDRAM Data Witdh
na/ × 8
00
00
08
00
08
15
Minimum Clock Delay tCCD = 1 CLK
for Back-to-Back
Random Column
Address
01
01
01
01
01
16
Burst Length
Supported
2, 4 & 8
0E
0E
0E
0E
0E
17
Number of SDRAM
Banks
4
04
04
04
04
04
Data Sheet
38
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
HYS64D16301GU–6–B
HYS64D32300GU–6–B
HYS72D32300GU–6–B
HYS64D64320GU–6–B
HYS72D64320GU–6–B
SPD Codes for PC2700 Modules “–6” (cont’d)
Part Number & Organization
Table 20
128MB
256MB
256MB
512MB
512MB
× 64
× 64
× 72
× 64
× 72
1 rank
1 rank
1 rank
2 ranks
2 ranks
HEX
HEX
HEX
HEX
HEX
Byte
Description
18
Supported CAS
Latencies
CAS latency = 2 & 2.5 0C
0C
0C
0C
0C
19
CS Latencies
CS latency = 0
01
01
01
01
01
20
WE Latencies
Write latency = 1
02
02
02
02
02
21
SDRAM DIMM Module unbuffered
Attributes
20
20
20
20
20
22
SDRAM Device
Attributes: General
C0
C0
C0
C0
C0
23
Min. Clock Cycle Time 7.5 ns
at CAS Latency = 2
75
75
75
75
75
24
Access Time from
Clock for
CL = 2
0.70 ns
70
70
70
70
70
25
Minimum Clock Cycle
Time for CL = 1.5
not supported
00
00
00
00
00
26
Access Time from
Clock at
CL = 1.5
not supported
00
00
00
00
00
27
Minimum Row
Precharge Time
18 ns
48
48
48
48
48
28
Minimum Row Act. to
Row Act. Delay tRRD
12 ns
30
30
30
30
30
29
Minimum RAS to CAS 18 ns
Delay tRCD
48
48
48
48
48
30
Minimum RAS Pulse
Width tRAS
42 ns
2A
2A
2A
2A
2A
31
Module Bank Density
(per Bank)
128 MByte/256 MByte 20
40
40
40
40
32
Addr. and Command
Setup Time
0.75 ns
75
75
75
75
75
33
Addr. and Command 0.75 ns
Hold Time
75
75
75
75
75
34
Data Input Setup Time 0.45 ns
45
45
45
45
45
35
Data Input Hold Time
45
45
45
45
45
Data Sheet
−
0.45 ns
39
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
HYS64D16301GU–6–B
HYS64D32300GU–6–B
HYS72D32300GU–6–B
HYS64D64320GU–6–B
HYS72D64320GU–6–B
SPD Codes for PC2700 Modules “–6” (cont’d)
Part Number & Organization
Table 20
128MB
256MB
256MB
512MB
512MB
× 64
× 64
× 72
× 64
× 72
1 rank
1 rank
1 rank
2 ranks
2 ranks
HEX
HEX
HEX
HEX
HEX
00
00
00
00
00
Byte
Description
36 to 40
Superset Information
41
Minimum Core Cycle 60 ns
Time tRC
3C
3C
3C
3C
3C
42
Min. Auto Refresh 72 ns
Cmd Cycle Time tFRC
48
48
48
48
48
43
Maximum Clock Cycle 12 ns
Time tCK
30
30
30
30
30
Max. DQS-DQ Skew 0.45 ns
2D
2D
2D
2D
2D
44
–
tDQSQ
45
X-Factor tQHS
0.55 ns
55
55
55
55
55
46 to 61
Superset Information
–
00
00
00
00
00
62
SPD Revision
Revision 0.0
00
00
00
00
00
63
Checksum for Bytes 0 –
- 62
E7
00
12
01
12
64
Manufacturers JEDEC –
ID Codes
C1
C1
C1
C1
C1
65 to 71
Manufacturer
Infineon
Infineon
Infineon
Infineon
Infineon
72
Module
Location
–
–
–
–
–
73 to 90
Module Part Number
–
–
–
–
–
–
91 to 92
Module Revision Code –
–
–
–
–
–
93 to 94
Module Manufacturing –
Date
–
–
–
–
–
95 to 98
Module Serial Number –
–
–
–
–
–
99 to 127
–
–
–
–
–
–
–
128 to 255 open for Customer use –
–
–
–
–
–
Data Sheet
–
Assembly –
40
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
Byte
HYS72D64320GU–5–B
HYS64D64320GU–5–B
HYS72D32300GU–5–B
HYS64D32300GU–5–B
HYS64D16301GU–5–B
SPD Codes for PC3200 Modules “–5”
Part Number & Organization
Table 21
128MB 256MB 256MB 512MB 512MB
× 64
× 64
× 72
× 64
× 72
1 rank 1 rank 1 rank 2 ranks 2 ranks
Description
HEX
HEX
HEX
HEX
HEX
0
Programmed SPD Bytes in E2PROM
128
80
80
80
80
80
1
Total number of Bytes in E2PROM
256
08
08
08
08
08
2
Memory Type DDR-I = 07h
DDR-SDRAM
07
07
07
07
07
3
# of Row Addresses
13
0D
0D
0D
0D
0D
4
# Number of Column Addresses
9/10
09
0A
0A
0A
0A
5
# of DIMM Banks
1/2
01
01
01
02
02
6
Data Width (LSB)
× 64/× 72
40
40
48
40
48
7
Data Width (MSB)
0
00
00
00
00
00
8
Interface Voltage Levels
SSTL_2.5
04
04
04
04
04
9
tCK @ CLmax (Byte 18) [ns]
5 ns
50
50
50
50
50
10
tAC SDRAM @ CLmax (Byte 18) [ns]
0.50 ns
50
50
50
50
50
11
DIMM Configuration Type (non- / ECC) non-ECC/ECC
00
00
02
00
02
12
Refresh Rate
Self-Refresh
7.8 µs
82
82
82
82
82
13
Primary SDRAM width
× 16/ × 8
10
08
08
08
08
14
Error Checking SDRAM width
na/ × 8
00
00
08
00
08
15
tCCD [cycles]
tCCD = 1 CLK
01
01
01
01
01
16
Burst Length Supported
2, 4 & 8
0E
0E
0E
0E
0E
17
Number of Banks on SDRAM
4
04
04
04
04
04
18
CAS Latency
CAS latency = 2, 1C
2.5, 3
1C
1C
1C
1C
19
CS Latency
CS latency = 0
01
01
01
01
01
20
WE (Write) Latency
Write latency = 1 02
02
02
02
02
21
DIMM Attributes
unbuffered
20
20
20
20
20
22
Component Attributes
−
C1
C1
C1
C1
C1
23
tCK @ CLmax -0.5 (Byte 18) [ns]
6.0 ns
60
60
60
60
60
24
tAC SDRAM @ CLmax -0.5 [ns]
0.50 ns
50
50
50
50
50
25
tCK @ CLmax -1 (Byte 18) [ns]
7.5 ns
75
75
75
75
75
26
tAC SDRAM @ CLmax -1 [ns]
not supported
50
50
50
50
50
27
tRPmin (ns)
15 ns
3C
3C
3C
3C
3C
28
tRRDmin [ns]
10 ns
28
28
28
28
28
Data Sheet
41
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
Byte
Description
29
tRCDmin [ns]
30
31
32
HYS72D64320GU–5–B
HYS64D64320GU–5–B
HYS72D32300GU–5–B
HYS64D32300GU–5–B
HYS64D16301GU–5–B
SPD Codes for PC3200 Modules “–5” (cont’d)
Part Number & Organization
Table 21
128MB 256MB 256MB 512MB 512MB
× 64
× 64
× 72
× 64
× 72
1 rank 1 rank 1 rank 2 ranks 2 ranks
HEX
HEX
HEX
HEX
HEX
15 ns
3C
3C
3C
3C
3C
tRASmin [ns]
40 ns
28
28
28
28
28
Module Density per Bank
128 MByte/
256 MByte
20
40
40
40
40
tAS, tCS [ns]
0.60 ns
60
60
60
60
60
33
tAH, TCH [ns]
0.60 ns
60
60
60
60
60
34
tDS [ns]
0.40 ns
40
40
40
40
40
35
tDH [ns]
0.40 ns
40
40
40
40
40
36 40
not used
–
00
00
00
00
00
41
tRCmin [ns]
55 ns
37
37
37
37
37
42
tRFCmin [ns]
65 ns
41
41
41
41
41
43
tCKmax [ns]
10 ns
28
28
28
28
28
44
tDQSQmax [ns]
0.40 ns
28
28
28
28
28
45
tQHSmax [ns]
0.50 ns
50
50
50
50
50
46 61
not used
–
00
00
00
00
00
62
SPD Revision
Revision 0.0
00
00
00
00
00
63
Checksum of Byte 0-62 (LSB only)
–
E4
FD
0F
FE
10
64
JEDEC ID Code for Infineon
–
C1
C1
C1
C1
C1
65
JEDEC ID Code for Infineon
“I”
49
49
49
49
49
66
JEDEC ID Code for Infineon
“N”
4E
4E
4E
4E
4E
67
JEDEC ID Code for Infineon
“F”
46
46
46
46
46
68
JEDEC ID Code for Infineon
“I”
49
49
49
49
49
69
JEDEC ID Code for Infineon
“N”
4E
4E
4E
4E
4E
70
JEDEC ID Code for Infineon
“E”
45
45
45
45
45
71
JEDEC ID Code for Infineon
“O”
4F
4F
4F
4F
4F
72
Module Manufacturer Location
–
xx
xx
xx
xx
xx
73
Module Part Number, Char 1
–
36
36
37
36
37
74
Module Part Number, Char 2
–
34
34
32
34
32
75
Module Part Number, Char 3
–
44
44
44
44
44
Data Sheet
42
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
Byte
HYS72D64320GU–5–B
HYS64D64320GU–5–B
HYS72D32300GU–5–B
HYS64D32300GU–5–B
HYS64D16301GU–5–B
SPD Codes for PC3200 Modules “–5” (cont’d)
Part Number & Organization
Table 21
128MB 256MB 256MB 512MB 512MB
× 64
× 64
× 72
× 64
× 72
1 rank 1 rank 1 rank 2 ranks 2 ranks
Description
HEX
HEX
HEX
HEX
HEX
76
Module Part Number, Char 4
–
31
33
33
36
36
77
Module Part Number, Char 5
–
36
32
32
34
34
78
Module Part Number, Char 6
–
33
33
33
33
33
79
Module Part Number, Char 7
–
30
30
30
32
32
80
Module Part Number, Char 8
–
31
30
30
30
30
81
Module Part Number, Char 9
–
47
47
47
47
47
82
Module Part Number, Char 10
–
55
55
55
55
55
83
Module Part Number, Char 11
–
35
35
35
35
35
84
Module Part Number, Char 12
–
42
42
42
42
42
85
Module Part Number, Char 13
–
20
20
20
20
20
86
Module Part Number, Char 14
–
20
20
20
20
20
87
Module Part Number, Char 15
–
20
20
20
20
20
88
Module Part Number, Char 16
–
20
20
20
20
20
89
Module Part Number, Char 17
–
20
20
20
20
20
90
Module Part Number, Char 18
–
20
20
20
20
20
91
Module Revision Code
–
xx
xx
xx
xx
xx
92
Test Program Revision Code
–
xx
xx
xx
xx
xx
93
Module Manufacturing Date Year
–
xx
xx
xx
xx
xx
94
Module Manufacturing Date Week
–
xx
xx
xx
xx
xx
95
Module Serial Number
–
xx
xx
xx
xx
xx
96
Module Serial Number
–
xx
xx
xx
xx
xx
97
Module Serial Number
–
xx
xx
xx
xx
xx
98
Module Serial Number
–
xx
xx
xx
xx
xx
99 127
not used
–
00
00
00
00
00
Data Sheet
43
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Package Outlines
5
Package Outlines
0.1 A B C
133.35
0.15 A B C
128.95
2.7 MAX.
A
31.75 ±0.13
4 ±0.1
1)
1
2.36 ±0.1
ø0.1 A B C
92
6.62
B
2.175
0.4
6.35
64.77
C
1.27 ±0.1
49.53
0.1 A B C
93
184
17.8
1.8 ±0.1
10
3.8 ±0.13
95 x 1.27 = 120.65
3 MIN.
0.2
2.5 ±0.2
Detail of contacts
1.27
1 ±0.05
0.1 A B C
1) On ECC modules only
Burr max. 0.4 allowed
Figure 7
Data Sheet
L-DIM-184-18
Package Outline - Raw Card C (128 MByte, 1 Rank Module)
44
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Package Outlines
0.1 A B C
133.35
0.15 A B C
128.95
2.7 MAX.
A
31.75 ±0.13
4 ±0.1
1)
1
2.36 ±0.1
ø0.1 A B C
92
6.62
B
2.175
0.4
6.35
64.77
C
1.27 ±0.1
49.53
0.1 A B C
93
184
17.8
1.8 ±0.1
10
3.8 ±0.13
95 x 1.27 = 120.65
3 MIN.
0.2
2.5 ±0.2
Detail of contacts
1.27
1 ±0.05
0.1 A B C
1) On ECC modules only
Burr max. 0.4 allowed
Figure 8
Data Sheet
L-DIM-184-29
Package Outline - Raw Card A (256 MByte, 1 Rank Module, –7 and –8)
45
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Package Outlines
0.1 A B C
133.35
0.15 A B C
128.95
4 MAX.
A
31.75 ±0.13
4 ±0.1
1)
1
2.36 ±0.1
ø0.1 A B C
92
6.62
B C
2.175
0.4
6.35
64.77
1.27 ±0.1
49.53
0.1 A B C
93
184
17.8
1.8 ±0.1
10
3.8 ±0.13
95 x 1.27 = 120.65
1)
3 MIN.
0.2
2.5 ±0.2
Detail of contacts
1.27
1 ±0.05
0.1 A B C
1) On ECC modules only
Burr max. 0.4 allowed
Figure 9
Data Sheet
L-DIM-184-9
Package Outline - Raw Card B (512 MByte, 2 Rank Module, –7 and –8)
46
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Package Outlines
0.1 A B C
133.35
0.15 A B C
128.95
2.7 MAX.
A
31.75 ±0.13
4 ±0.1
1)
1
2.36 ±0.1
ø0.1 A B C
92
6.62
B
2.175
0.4
6.35
64.77
C
1.27 ±0.1
49.53
0.1 A B C
93
184
17.8
1.8 ±0.1
10
3.8 ±0.13
95 x 1.27 = 120.65
3 MIN.
0.2
2.5 ±0.2
Detail of contacts
1.27
1 ±0.05
0.1 A B C
1) On ECC modules only
Burr max. 0.4 allowed
Figure 10
Data Sheet
L-DIM-184-30
Package Outline - Raw Card A (256 MByte, 1 Rank Module, –5 and –6, ECC)
47
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Package Outlines
0.1 A B C
133.35
0.15 A B C
128.95
4 MAX.
A
31.75 ±0.13
4 ±0.1
1)
1
2.36 ±0.1
ø0.1 A B C
92
6.62
B C
2.175
0.4
6.35
64.77
1.27 ±0.1
49.53
0.1 A B C
93
184
17.8
1.8 ±0.1
10
3.8 ±0.13
95 x 1.27 = 120.65
3 MIN.
0.2
2.5 ±0.2
Detail of contacts
1.27
1 ±0.05
0.1 A B C
1) On ECC modules only
Burr max. 0.4 allowed
Figure 11
Data Sheet
L-DIM-184-31
Package Outline - Raw Card B (512 MByte, 2 Rank Module, –5 and –6, ECC)
48
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Package Outlines
0.1 A B C
133.35
0.15 A B C
128.95
2.7 MAX.
31.75 ±0.13
4 ±0.1
A
1
2.36 ±0.1
ø0.1 A B C
92
6.62
B
2.175
0.4
6.35
64.77
C
1.27 ±0.1
49.53
1.8 ±0.1
0.1 A B C
93
184
17.8
10
3.8 ±0.13
95 x 1.27 = 120.65
3 MIN.
0.2
2.5 ±0.2
Detail of contacts
1.27
1 ±0.05
0.1 A B C
Burr max. 0.4 allowed
L-DIM-184-32
Figure 12
Package Outline - Raw Card A (256 MByte, 1 Rank Module, –5 and –6, Non ECC)
Data Sheet
49
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Package Outlines
0.1 A B C
133.35
0.15 A B C
128.95
4 MAX.
31.75 ±0.13
4 ±0.1
A
1
2.36 ±0.1
ø0.1 A B C
92
6.62
B C
2.175
0.4
6.35
64.77
1.27 ±0.1
49.53
1.8 ±0.1
0.1 A B C
93
184
17.8
10
3.8 ±0.13
95 x 1.27 = 120.65
3 MIN.
0.2
2.5 ±0.2
Detail of contacts
1.27
1 ±0.05
0.1 A B C
Burr max. 0.4 allowed
L-DIM-184-33
Figure 13
Package Outline - Raw Card B (512 MByte, 2 Rank Module, –5 and –6, Non ECC)
Data Sheet
50
V1.1, 2003-07
www.infineon.com
Published by Infineon Technologies AG