ICSI IC80LV52

IC80LV52
IC80LV32
IC80LV52
IC80LV32
CMOS SINGLE CHIP
LOW VOLTAGE
8-BIT MICROCONTROLLER
FEATURES
GENERAL DESCRIPTION
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The ICSI IC80LV52 and IC80LV32 are high-performance
microcontrollers fabricated using high-density CMOS
technology. The CMOS IC80LV52/32 is functionally
compatible with the industry standard 8052/32
microcontrollers.
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80C51 based architecture
8K x 8 ROM (IC80LV52 only)
256 x 8 RAM
Three 16-bit Timer/Counters
Full duplex serial channel
Boolean processor
Four 8-bit I/O ports, 32 I/O lines
Memory addressing capability
– 64K ROM and 64K RAM
Program memory lock
– Encrypted verify (32 bytes)
– Lock bits (2)
Power save modes:
– Idle and power-down
Eight interrupt sources
Most instructions execute in 0.5 µs
CMOS and TTL compatible
Maximum speed: 24 MHz @ Vcc = 3.3V
Packages available:
– 40-pin DIP
– 44-pin PLCC
– 44-pin PQFP
The IC80LV52/32 is designed with 8K x 8 ROM (IC80LV52
only); 256 x 8 RAM; 32 programmable I/O lines; a serial
I/O port for either multiprocessor communications, I/O
expansion or full duplex UART; three 16-bit timer/counters;
an eight-source, two-priority-level, nested interrupt
structure; and an on-chip oscillator and clock circuit. The
IC80LV52/32 can be expanded using standard TTL
compatible memory.
T2/P1.0
1
40
VCC
T2EX/P1.1
2
39
P0.0/AD0
P1.2
3
38
P0.1/AD1
P1.3
4
37
P0.2/AD2
P1.4
5
36
P0.3/AD3
P1.5
6
35
P0.4/AD4
P1.6
7
34
P0.5/AD5
P1.7
8
33
P0.6/AD6
RST
9
32
P0.7/AD7
RxD/P3.0
10
31
EA
TxD/P3.1
11
30
ALE
INT0/P3.2
12
29
PSEN
INT1/P3.3
13
28
P2.7/A15
T0/P3.4
14
27
P2.6/A14
T1/P3.5
15
26
P2.5/A13
WR/P3.6
16
25
P2.4/A12
RD/P3.7
17
24
P2.3/A11
XTAL2
18
23
P2.2/A10
XTAL1
19
22
P2.1/A9
GND
20
21
P2.0/A8
Figure 1. IC80LV52/32 Pin Configuration:
40-pin DIP
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
MC006-0B
1
P1.3
P1.2
P1.1/T2EX
P1.0/T2
NC
VCC
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
INDEX
P1.4
IC80LV52
IC80LV32
6
5
4
3
2
1
44
43
42
41
40
P1.5
7
39
P0.4/AD4
P1.6
8
38
P0.5/AD5
P1.7
9
37
P0.6/AD6
RST
10
36
P0.7/AD7
RxD/P3.0
11
35
EA
NC
12
34
NC
TxD/P3.1
13
33
ALE
INT0/P3.2
14
32
PSEN
INT1/P3.3
15
31
P2.7/A15
T0/P3.4
16
30
P2.6/A14
T1/P3.5
17
29
P2.5/A13
18
19
20
21
22
23
24
25
26
27
28
WR/P3.6
RD/P3.7
XTAL2
XTAL1
GND
NC
A8/P2.0
A9/P2.1
A10/P2.2
A11/P2.3
A12/P2.4
TOP VIEW
Figure 2. IC80LV52/32 Pin Configuration: 44-pin PLCC
2
Integrated Circuit Solution Inc.
MC006-0B
P1.4
P1.3
P1.2
P1.1/T2EX
P1.0/T2
NC
VCC
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
IC80LV52
IC80LV32
44
43
42
41
40
39
38
37
36
35
34
P0.6/AD6
RST
4
30
P0.7/AD7
RxD/P3.0
5
29
EA
NC
6
28
NC
TxD/P3.1
7
27
ALE
INT0/P3.2
8
26
PSEN
INT1/P3.3
9
25
P2.7/A15
T0/P3.4
10
24
P2.6/A14
T1/P3.5
11
23
P2.5/A13
12
13
14
15
16
17
18
19
20
21
22
A12/P2.4
31
A11/P2.3
3
A10/P2.2
P1.7
A9/P2.1
P0.5/AD5
A8/P2.0
32
NC
2
GND
P1.6
XTAL1
P0.4/AD4
XTAL2
33
RD/P3.7
1
WR/P3.6
P1.5
Figure 3. IC80LV52/32 Pin Configuration: 44-pin PQFP
Integrated Circuit Solution Inc.
MC006-0B
3
IC80LV52
IC80LV32
VCC
P2.0-P2.7
P0.0-P0.7
P2
DRIVERS
P0
DRIVERS
P2
LATCH
P0
LATCH
GND
RAM ADDR
REGISTER
ADDRESS
DECODER
& 256
BYTES RAM
B
REGISTER
STACK
POINT
ADDRESS 2 LOCK BITS
DECODER
&
&
32 BYTES
8K ROM
ENCRYPTION
PROGRAM
ADDRESS
REGISTER
ACC
PCON SCON
T2CON
TH0
TL1
TH2
RCAP2L SBUF
TMOD TCON
TL0
TH1
TL2 RCAP2H
IE
IP
TMP2
INTERRUPT
SERIAL PORT
AND TIMER BLOCK
TMP1
PROGRAM
COUNTER
PC
INCREMENTER
ALU
PSW
PSEN
ALE
RST
TIMING
AND
CONTROL
EA
INSTRUCTION
REGISTER
BUFFER
DPTR
P3
LATCH
P1
LATCH
P3
DRIVERS
P1
DRIVERS
P3.0-P3.7
P1.0-P1.7
OSCILLATOR
XTAL1
XTAL2
Figure 4. IC80LV52/32 Block Diagram
4
Integrated Circuit Solution Inc.
MC006-0B
IC80LV52
IC80LV32
Table 1. Detailed Pin Description
Symbol
PDIP
PLCC
PQFP
I/O
Name and Function
ALE
30
33
27
I/O
Address Latch Enable: Output pulse for latching the low byte
of the address during an address to the external memory. In
normal operation, ALE is emitted at a constant rate of 1/6 the
oscillator frequency, and can be used for external timing or
clocking. Note that one ALE pulse is skipped during each
access to external data memory.
EA
31
35
29
I
External Access enable: EA must be externally held low to
enable the device to fetch code from external program memory
locations 0000H to FFFFH. If EA is held high, the device
executes from internal program memory unless the program
counter contains an address greater than 1FFFH.
P0.0-P0.7
39-32
43-36
37-30
I/O
Port 0: Port 0 is an 8-bit open-drain, bidirectional I/O port. Port
0 pins that have 1s written to them float and can be used as
high-impedance inputs. Port 0 is also the multiplexed low-order
address and data bus during accesses to external program and
data memory. In this application, it uses strong internal pullups
when emitting 1s.
P1.0-P1.7
1-8
2-9
40-44
1-3
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal
pullups. Port 1 pins that have 1s written to them are pulled high
by the internal pullups and can be used as inputs. As inputs,
Port 1 pins that are externally pulled low will source current
because of the internal pullups. (See DC Characteristics: IIL).
The Port 1 output buffers can sink/source four TTL inputs.
Port 1 also receives the low-order address byte during ROM
verification.
P2.0-P2.7
1
2
2
3
40
41
I
I
21-28
24-31
18-25
I/O
T2(P1.0): Timer/Counter 2 external count input.
T2EX(P1.1): Timer/Counter 2 trigger input.
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal
pullups. Port 2 pins that have 1s written to them are pulled high
by the internal pullups and can be used as inputs. As inputs,
Port 2 pins that are externally pulled low will source current
because of the internal pullups. (See DC Characteristics: IIL).
Port 2 emits the high order address byte during fetches from
external program memory and during accesses to external
data memory that used 16-bit addresses (MOVX @ DPTR). In
this application, Port 2 uses strong internal pullups when
emitting 1s. During accesses to external data memory that use
8-bit addresses (MOVX @ Ri [i = 0, 1]), Port 2 emits the contents
of the P2 Special Function Register.
Port 2 also receives the high-order bits and some control
signals during ROM verification.
Integrated Circuit Solution Inc.
MC006-0B
5
IC80LV52
IC80LV32
Table 1. Detailed Pin Description (continued)
Symbol
PDIP
PLCC
PQFP
I/O
Name and Function
P3.0-P3.7
10-17
11, 13-19
5, 7-13
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal
pullups. Port 3 pins that have 1s written to them are pulled high
by the internal pullups and can be used as inputs. As inputs,
Port 3 pins that are externally pulled low will source current
because of the internal pullups. (See DC Characteristics: IIL).
Port 3 also serves the special features of the IC80LV52/32, as
listed below:
10
11
12
13
14
15
16
17
11
13
14
15
16
17
18
19
5
7
8
9
10
11
12
13
I
O
I
I
I
I
O
O
RxD (P3.0): Serial input port.
TxD (P3.1): Serial output port.
INT0 (P3.2): External interrupt 0.
INT1 (P3.3): External interrupt 1.
T0 (P3.4): Timer 0 external input.
T1 (P3.5): Timer 1 external input.
WR (P3.6): External data memory write strobe.
RD (P3.7): External data memory read strobe.
PSEN
29
32
26
O
Program Store Enable: The read strobe to external program
memory. When the device is executing code from the external
program memory, PSEN is activated twice each machine cycle
except that two PSEN activations are skipped during each
access to external data memory. PSEN is not activated during
fetches from internal program memory.
RST
9
10
4
I
Reset: A high on this pin for two machine cycles while the
oscillator is running, resets the device. An internal MOS resistor
to GND permits a power-on reset using only an external
capacitor connected to Vcc.
XTAL 1
19
21
15
I
Crystal 1: Input to the inverting oscillator amplifier and input
to the internal clock generator circuits.
XTAL 2
18
20
14
O
Crystal 2: Output from the inverting oscillator amplifier.
GND
20
22
16
I
Ground: 0V reference.
Vcc
40
44
38
I
Power Supply: This is the power supply voltage for operation.
OPERATING DESCRIPTION
The detail description of the IC80LV52/32 included in this description are:
• Memory Map and Registers
• Timer/Counters
• Serial Interface
• Interrupt System
• Other Information
The detail information desription of the IC80LV52/32 refer to IC80C52/32 data sheet
6
Integrated Circuit Solution Inc.
MC006-0B
IC80LV52
IC80LV32
OTHER INFORMATION
Reset
The reset input is the RST pin, which is the input to a
Schmitt Trigger.
A reset is accomplished by holding the RST pin high for at
least two machine cycles (24 oscillator periods), while the
oscillator is running. The CPU responds by generating an
internal reset, with the timing shown in Figure 6.
The external reset signal is asynchronous to the internal
clock. The RST pin is sampled during State 5 Phase 2 of
every machine cycle. The port pins will maintain their
current activities for 19 oscillator periods after a logic 1 has
been sampled at the RST pin; that is, for 19 to 31 oscillator
periods after the external reset signal has been applied to
the RST pin.
The internal reset algorithm writes 0s to all the SFRs
except the port latches, the Stack Pointer, and SBUF. The
port latches are initialized to FFH, the Stack Pointer to
07H, and SBUF is indeterminate. Table 2 lists the SFRs
and their reset values.
Then internal RAM is not affected by reset. On power-up
the RAM content is indeterminate.
Integrated Circuit Solution Inc.
MC006-0B
Table 2. Reset Values of the SFR's
SFR Name
PC
ACC
Reset Value
0000H
00H
B
PSW
SP
DPTR
P0-P3
IP
IE
TMOD
TCON
T2CON
TH0
TL0
TH1
TL1
TH2
TL2
RCAP2H
RCAP2L
SCON
SBUF
PCON
00H
00H
07H
0000H
FFH
XX000000B
0X000000B
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
Indeterminate
0XXX0000B
7
IC80LV52
IC80LV32
Power-on Reset
An automatic reset can be obtained when VCC goes
through a 10µF capacitor and GND through an 8.2K
resistor, providing the VCC rise time does not exceed
1 msec and the oscillator start-up time does not exceed
10 msec. This power-on reset circuit is shown in Figure 5.
The CMOS devices do not require the 8.2K pulldown
resistor, although its presence does no harm.
Vcc
10 F
+
-
Vcc
IC80LV52/32
When power is turned on, the circuit holds the RST pin high
for an amount of time that depends on the value of the
capacitor and the rate at which it charges. To ensure a
good reset, the RST pin must be high long enough to allow
the oscillator time to start-up (normally a few msec) plus
two machine cycles.
RST
8.2K Ω
Note that the port pins will be in a random state until the
oscillator has start and the internal reset algorithm has
written 1s to them.
GND
With this circuit, reducing VCC quickly to 0 causes the RST
pin voltage to momentarily fall below 0V. However, this
voltage is internally limited, and will not harm the device.
Figure 5. Power-On Reset Circuit
12 OSC. PERIODS
S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4
RST
INTERNAL RESET SIGNAL
SAMPLE
SAMPLE
RST
RST
ALE
PSEN
P0
INST
ADDR
INST
11 OSC. PERIODS
ADDR
INST
ADDR
INST
ADDR
INST
ADDR
19 OSC. PERIODS
Figure 6. Reset Timing
8
Integrated Circuit Solution Inc.
MC006-0B
IC80LV52
IC80LV32
Power-Saving Modes of Operation
The IC80LV52/32 has two power-reducing modes. Idle
and Power-down. The input through which backup power
is supplied during these operations is Vcc. Figure 7 shows
the internal circuitry which implements these features. In
the Idle mode (IDL = 1), the oscillator continues to run and
the Interrupt, Serial Port, and Timer blocks continue to be
clocked, but the clock signal is gated off to the CPU. In
Power-down (PD = 1), the oscillator is frozen. The Idle and
Power-down modes are activated by setting bits in Special
Function Register PCON.
XTAL 1
XTAL 2
OSC
INTERRUPT,
SERIAL PORT,
TIMER BLOCKS
CLOCK
GEN
CPU
PD
IDL
Idle Mode
An instruction that sets PCON.0 is the last instruction
executed before the Idle mode begins. In the Idle mode,
the internal clock signal is gated off to the CPU, but not to
the Interrupt, Timer, and Serial Port functions. The CPU
status is preserved in its entirety: the Stack Pointer,
Program Counter, Program Status Word, Accumulator,
and all other registers maintain their data during Idle. The
port pins hold the logical states they had at the time Idle
was activated. ALE and PSEN hold at logic high levels.
There are two ways to terminate the Idle. Activation of any
enabled interrupt will cause PCON.0 to be cleared by
hardware, terminating the Idle mode. The interrupt will be
serviced, and following RETI the next instruction to be
executed will be the one following the instruction that put
the device into Idle.
The flag bits GF0 and GF1 can be used to indicate whether
an interrupt occurred during normal operation or during an
Idle. For example, an instruction that activates Idle can
also set one or both flag bits. When Idle is terminated by
an interrupt, the interrupt service routine can examine the
flag bits.
The other way of terminating the Idle mode is with a
hardware reset. Since the clock oscillator is still running,
the hardware reset must be held active for only two
machine cycles (24 oscillator periods) to complete the
reset.
Figure 7. Idle and Power-Down Hardware
Power-down Mode
An instruction that sets PCON.1 is the last instruction
executed before Power-down mode begins. In the Powerdown mode, the on-chip oscillator stops. With the clock
frozen, all functions are stopped, but the on-chip RAM and
Special function Registers are held. The port pins output
the values held by their respective SFRs. ALE and PSEN
output lows.
In the Power-down mode of operation, Vcc can be reduced
to as low as 2V. However, Vcc must not be reduced before
the Power-down mode is invoked, and Vcc must be restored
to its normal operating level before the Power-down mode is
terminated. The reset that terminates Power-down also
frees the oscillator. The reset should not be activated before
Vcc is restored to its normal operating level and must be held
active long enough to allow the oscillator to restart and
stabilize (normally less than 10 msec).
The only exit from power-down is a hardware reset. Reset
redefines all the SFRs but does not change the on-chip
RAM.
The signal at the RST pin clears the IDL bit directly and
asynchronously. At this time, the CPU resumes program
execution from where it left off; that is, at the instruction
following the one that invoked the Idle Mode. As shown in
Figure 22, two or three machine cycles of program execution
may take place before the internal reset algorithm takes
control. On-chip hardware inhibits access to the internal
RAM during his time, but access to the port pins is not
inhibited. To eliminate the possibility of unexpected outputs
at the port pins, the instruction following the one that
invokes Idle should not write to a port pin or to external data
RAM.
Integrated Circuit Solution Inc.
MC006-0B
9
IC80LV52
IC80LV32
Table 3. Status of the External Pins During Idle and Power-down Modes.
Mode
Memory
ALE
PSEN
PORT 0
PORT 1
PORT 2
PORT 3
Idle
Internal
1
1
Data
Data
Data
Data
Idle
External
1
1
Float
Data
Address
Data
Power-down
Internal
0
0
Data
Data
Data
Data
Power-down
External
0
0
Float
Data
Data
Data
On-Chip Oscillators
The on-chip oscillator circuitry of the IC80LV52/32 is a
single stage linear inverter, intended for use as a crystalcontrolled, positive reactance oscillator (Figure 8). In this
application the crystal is operated in its fundamental
response mode as an inductive reactance in parallel
resonance with capacitance external to the crystal (Figure
8). Examples of how to drive the clock with external
oscillator are shown in Figure 9.
The crystal specifications and capacitance values (C1 and
C2 in Figure 8) are not critical. 20 pF to 30 pF can be used
in these positions at a12 MHz to 24 MHz frequency with
good quality crystals. A ceramic resonator can be used in
place of the crystal in cost-sensitive applications. When a
ceramic resonator is used, C1 and C2 are normally selected
to be of somewhat higher values. The manufacturer of the
ceramic resonator should be consulted for recommendation
on the values of these capacitors.
C2
XTAL2
C1
XTAL1
XTAL2
NC
EXTERNAL
OSCILLATOR
SIGNAL
XTAL1
GND
GND
Figure 8. Oscillator Connections
Figure 9. External Clock Drive Configuration
Table 4. Recommended Value for C1, C2, R
C1
C2
R
10
Frequency Range
4 MHz-24 MHz
30 MHz-40 MHz
20 pF-30 pF
–
20 pF-30 pF
–
Not Apply
–
Integrated Circuit Solution Inc.
MC006-0B
IC80LV52
IC80LV32
ROM Verification
The address of the program memory location to be read is
applied to Port 1 and pins P2.4-P2.0. The other pins
should be held at the “Verify” level are indicated in Figure
10. The contents of the addressed locations exits on Port
0. External pullups are required on Port 0 for this operation.
Figure 10 shows the setup to verify the program memory.
+ 3..3V
A7-A0
P1
A12-A8
P2.4-P2.0
1
RST
1
EA
1
ALE
0
PSEN
0
P2.7
0
P2.6
Vcc
10K x 8
P0
PGM
DATA
XTAL1
4-6 MHz
XTAL2
GND
Figure 10. ROM Verification
Integrated Circuit Solution Inc.
MC006-0B
11
IC80LV52
IC80LV32
ROM Lock System
Encryption Array
The program lock system, when programmed, protects
the ROM code against software piracy. The IC80LV52/32
has a two-level program lock system (see Table 5) and a
32-byte encryption table. No matter what lock bit is, the
user submits the encryption table with his or her code in
verify ROM mode. Both the lock-bit and encryption array
programmed by the factory.
Within the ROM array are 32 bytes of Encryption Array that
are initially unprogrammed (all 1's). Every time that a byte
is addressed during verify, five address lines are used to
select a byte of the Encryption Array.This byte is then
exclusive-NOR'ed (XNOR) with the code byte, creating an
Encryption verify byte. The algorithm, with the array in the
unprogrammed state (all 1's), will return the code in its
original, unmodified form.
When using the encryption array, one important factor
needs to be considered. If a code byte has the value 0FFH,
verifying the byte will produce the encryption byte value. If
a large block (> 32 bytes) of code is left unprogrammed, a
verification routine will display the contents of the encryption
array. For this reason, all unused code bytes should be
programmed with some value other than 0FFH, and not all
of them the same value.
Table 5. Program Lock Bits
12
1
LB1
U
LB2
U
2
P
U
3
P
P
Protection Type
No Program Lock Features enabled. (Code verify will still be
encrypted by the Encryption Array if Programmed)
MOVC instructions executed from external program memory
are diabled form fetching code bytes from internal memory,
EA is sampled and latched on Reset.
Same as 2, also ROM verify is disabled.
Integrated Circuit Solution Inc.
MC006-0B
IC80LV52
IC80LV32
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TBIAS
TSTG
PT
Parameter
Terminal Voltage with Respect to GND(2)
Temperature Under Bias(3)
Storage Temperature
Power Dissipation
Value
–2.0 to +7.0
0 to +70
–65 to +125
1.5
Unit
V
°C
°C
W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V
for periods less than 20 ns. Maximum DC voltage on output pins is Vcc + 0.5V which may
overshoot to Vcc + 2.0V for periods less than 20 ns.
3. Operating temperature is for commercial products only defined by this specification.
OPERATING RANGE(1)
Range
Commercial
Ambient Temperature
0°C to +70°C
VCC
3.3V ± 10%
Oscillator Frequency
3.5 to 24 MHz
Note:
1. Operating ranges define those limits between which the functionality of the device is guaranteed.
Integrated Circuit Solution Inc.
MC006-0B
13
IC80LV52
IC80LV32
DC CHARACTERISTICS
(TA = 0°C to 70°C; Vcc = 3.3V ± 10%; GND = 0V)
Symbol
Parameter
Test conditions
Min
Max
Unit
VIL
Input low voltage (All except EA)
–0.5
0.2Vcc + 0.1
V
VIL1
Input low voltage (EA)
–0.5
0.2Vcc + 0.1
V
VIH
Input high voltage
(All except XTAL 1, RST)
0.2Vcc + 0.9
Vcc + 0.5
V
VIH1
Input high voltage (XTAL 1)
0.7Vcc
Vcc + 0.5
V
VSCH+
RST positive schmitt-trigger
threshold voltage
0.7Vcc
Vcc + 0.5
V
VSCH–
RST negative schmitt-trigger
threshold voltage
0
0.3Vcc
V
Vol(1)
Output low voltage
IOL = 1.6 mA
—
0.45
V
IOL = 3.2 mA
—
0.45
V
(Ports 1, 2, 3)
(1)
VOL1
Output low voltage
(Port 0, ALE, PSEN)
VOH
Output high voltage
(Ports 1, 2, 3, ALE, PSEN)
IOH = –20 µA
Vcc–0.9
—
V
VOH1
Output high voltage
(Port 0, ALE, PSEN)
IOH = –800 µA
Vcc–0.9
—
V
IIL
Logical 0 input current (Ports 1, 2, 3) VIN = 0.45V
—
–50
µA
ILI
Input leakage current (Port 0)
0.45V < VIN < Vcc
–5
5
µA
ITL
Logical 1-to-0 transition current
(Ports 1, 2, 3)
VIN = 2.0V
—
–450
µA
150
450
KΩ
RRST
RST pulldown resister
Note:
1. Under steady state (non-transient) conditions, Iol must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port
Port 0: 26 mA
Ports 1, 2, 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification.
Pins are not guaranteed to sink greater than the listed test conditions.
14
Integrated Circuit Solution Inc.
MC006-0B
IC80LV52
IC80LV32
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test conditions
(1)
Icc
Min
Max
Unit
Power supply current
Vcc = 3.3V
Active mode
12 MHz
—
15
mA
24 MHz
—
24
mA
Idle mode
12 MHz
—
4
mA
24 MHz
—
8
mA
Power-down mode
VCC = 3.3V
—
50
µA
Note:
1. See Figures 11, 12, 13, and 14 for Icc test conditiions.
Vcc
Vcc
Vcc
Icc
Icc
RST
RST
Vcc
Vcc
Vcc
Vcc
NC
XTAL2
CLOCK
SIGNAL
XTAL1
GND
P0
EA
NC
XTAL2
CLOCK
SIGNAL
XTAL1
GND
Figure 11. Active Mode
P0
EA
Figure 12. Idle Mode
Vcc
Icc
RST
Vcc
Vcc
NC
XTAL2
P0
XTAL1
GND
EA
Figure 13. Power-down Mode
Integrated Circuit Solution Inc.
MC006-0B
15
IC80LV52
IC80LV32
tCLCX
Vcc — 0.5V
0.45V
tCHCX
0.7Vcc
0.2Vcc — 0.1
tCHCL
tCLCH
tCLCL
Figure 14. Clock Signal Waveform for Icc Tests in Active and Idle Modes. (tCLCH=t CHCL=5 ns)
AC CHARACTERISTICS
(TA = 0°C to 70°C; Vcc = 3.3V ± 10%; GND = 0V; Cl for Port 0, ALE and PSEN Outputs = 100 pF; Cl for other outputs = 80 pF)
EXTERNAL MEMORY CHARACTERISTICS
Symbol
1/tCLCL
tLHLL
tAVLL
tLLAX
tLLIV
tLLPL
tPLPH
tPLIV
tPXIX
tPXIZ
tAVIV
tPLAZ
tRLRH
tWLWH
tRLDV
tRHDX
tRHDZ
tLLDV
tAVDV
tLLWL
tAVWL
tQVWX
tWHQX
tRLAZ
tWHLH
16
Parameter
Oscillator frequency
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instr in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instr in
Input instr hold after PSEN
Input instr float after PSEN
Address to valid instr in
PSEN low to address float
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address to RD or WR low
Data valid to WR transition
Data hold after WR
RD low to address float
RD or WR high to ALE high
12 MHz
Clock
Min Max
—
—
152
—
68
—
73
—
—
313
73
—
235
—
—
230
0
—
—
78
—
397
—
10
480
—
480
—
—
323
0
—
—
162
—
573
—
656
230 270
313
—
68
—
73
—
—
0
68
98
24 MHz
Clock
Min Max
— —
68 —
26 —
31 —
— 147
31 —
110 —
— 105
0
—
— 37
— 188
— 10
230 —
230 —
— 157
0
—
— 78
— 282
— 323
105 145
146 —
26 —
31 —
—
0
26 57
Variable Oscillator
(3.5-24 MHz)
Min
Max
3.5
24
2tCLCL–15
—
tCLCL–15
—
tCLCL–10
—
—
4tCLCL–20
tCLCL–10
—
3tCLCL–15
—
—
3tCLCL–20
0
—
—
tCLCL–5
—
5tCLCL–20
—
10
6tCLCL–20
—
6tCLCL–20
—
—
4tCLCL–10
0
—
—
2tCLCL–5
—
7tCLCL–10
—
8tCLCL–10
3tCLCL–20
3tCLCL+20
4tCLCL–20
—
tCLCL–15
—
tCLCL–10
—
—
0
tCLCL–15
tCLCL+15
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Integrated Circuit Solution Inc.
MC006-0B
IC80LV52
IC80LV32
EXTERNAL MEMORY CHARACTERISTICS
(CONTINUED)
Symbol
tXLXL
tQVXH
tXHQX
tXHDX
tXHDV
Parameter
Serial port clock cycle time
Output data setup to
clock rising edge
Output data hold after
clock rising edge
Input data hold after
clock rising edge
Clock rising edge to
input data valid
12 MHz
Clock
Min Max
990 1010
823
—
24 MHz
Clock
Min Max
290 310
240 —
Variable Oscillator
(3.5-24 MHz)
Min
Max
12tCLCL–10
12tCLCL+10
10tCLCL–10
—
157
—
40
—
2tCLCL–10
—
ns
0
—
0
—
0
—
ns
—
833
—
250
—
10tCLCL
ns
Min
3.5
10
10
—
—
Max
40
—
—
10
10
Unit
MHz
ns
ns
ns
ns
Min
4
—
—
0
Max
6
48tCLCL
48tCLCL
48tCLCL
Unit
MHz
Unit
ns
ns
EXTERNAL CLOCK DRIVE
Symbol
1/tCLCL
tCHCX
tCLCX
tCLCH
tCHCL
wParameter
Oscillator Frequency
High time
Low time
Rise time
Fall time
ROM VERIFICATION CHARACTERISTICS
Symbol
1/tCLCL
tAVQV
tELQV
tEHQZ
Parameter
Oscillator Frequency
Address to data valid
ENABLE low to data valid
Data float after ENABLE
Integrated Circuit Solution Inc.
MC006-0B
17
IC80LV52
IC80LV32
TIMING WAVEFORMS
tLHLL
ALE
tLLPL
tPLPH
tPLIV
tAVLL
PSEN
tPLAZ
tLLAX
PORT 0
A7-A0
tPXIX
tPXIZ
INSTR IN
A7-A0
tLLIV
tAVIV
PORT 2
A15-A8
A15-A8
Figure 15. External Program Memory Read Cycle
ALE
tWHLH
PSEN
tLLDV
tLLWL
RD
PORT 0
tAVLL
tRLAZ
tLLAX
tRLRH
tRLDV
A7-A0 FROM RI OR DPL
tRHDZ
tRHDX
DATA IN
A7-A0 FROM PCL
INSTR IN
tAVWL
tAVDV
PORT 2
A15-A8 FROM DPH
A15-A8 FROM PCH
Figure 16. External Data Memory Read Cycle
18
Integrated Circuit Solution Inc.
MC006-0B
IC80LV52
IC80LV32
ALE
tWHLH
PSEN
tLLWL
WR
tWLWH
tAVLL
PORT 0
tWHQX
tQVWX
tLLAX
A7-A0 FROM RI OR DPL
DATA OUT
A7-A0 FROM PCL
INSTR IN
tAVWL
PORT 2
A15-A8 FROM DPH
A15-A8 FROM PCH
Figure 17. External Data Memory Write Cycle
INSTRUCTION
0
1
2
3
4
5
6
7
8
ALE
tXLXL
CLOCK
tXHQX
tQVXH
0
DATAOUT
1
VALID
3
4
5
6
tXHDX
tXHDV
DATAIN
2
VALID
VALID
7
SET TI
VALID
VALID
VALID
VALID
VALID
SET RI
Figure 18. Shift Register Mode Timing Waveform
Integrated Circuit Solution Inc.
MC006-0B
19
IC80LV52
IC80LV32
tCLCX
Vcc — 0.5V
0.45V
tCHCX
0.7Vcc
0.2Vcc — 0.1
tCHCL
tCLCH
tCLCL
Figure 19. External Clock Drive Waveform
P1.0-P1.7
P2.0-P2.3
ADDRESS
PORT 0
DATA OUT
tAVQV
tELQV
tEHQZ
P2.7
Figure 20. ROM Verification Waveforms
Vcc - 0.5V
0.45V
0.2Vcc + 0.9V
0.2Vcc - 0.1V
Figure 21. AC Test Point
Note:
1. AC inputs during testing are driven at VCC – 0.5V for logic “1” and 0.45V for logic “0”.
Timing measurements are made at VIH min for logic “1” and max for logic “0”.
20
Integrated Circuit Solution Inc.
MC006-0B
IC80LV52
IC80LV32
ORDERING INFORMATION
COMMERCIAL TEMPERATURE: 0°C to +70°C
Speed
24 MHz
24 MHz
Order Part Number
IC80LV52-24PL
IC80LV52-24PQ
IC80LV52-24W
IC80LV32-24PL
IC80LV32-24PQ
IC80LV32-24W
Package
PLCC
PQFP
600mil DIP
PLCC
PQFP
600mil DIP
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
Integrated Circuit Solution Inc.
MC006-0B
21
IC80LV52
IC80LV32
22
Integrated Circuit Solution Inc.
MC006-0B