ICM7243 8-Character, MicroprocessorCompatible, LED Display Decoder Driver August 1997 Features Description • 14-Segment and 16-Segment Fonts with Decimal Point The ICM7243 is an 8-character, alphanumeric display driver and controller which provides all the circuitry required to interface a microprocessor or digital system to a 14-segment or 16-segment display. It is primarily intended for use in microprocessor systems, where it minimizes hardware and software overhead. Incorporated on-chip are a 64-character ASClI decoder, 8 x 6 memory, high power character and segment drivers, and the multiplex scan circuitry. • Mask Programmable for Other Font-Sets Up to 64 Characters • Microprocessor Compatible • Directly Drives LED Common Cathode Displays • Cascadable Without Additional Hardware • Standby Feature Turns Display Off; Puts Chip in Low Power Mode • Sequential Entry or Random Entry of Data Into Display • Single +5V Operation • Character and Segment Drivers, All MUX Scan Circuitry, 8 x 6 Static Memory and 64-Character ASCll Font Generator Included On-Chip Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. NO. ICM7243AIJL -25oC to 85 40 Ld CERPDIP F40.6 ICM7243AIPL -25oC to 85 40 Ld PDIP E40.6 ICM7243BIJL -25oC to 85 40 Ld CERPDIP F40.6 ICM7243BlPL -25 to 85 40 Ld PDIP E40.6 6-bit ASCll data to be displayed is written into the memory directly from the microprocessor data bus. Data location depends upon the selection of either Sequential (MODE = 1) or Random access mode (MODE = 0). In the Sequential Access mode the first entry is stored in the lowest location and displayed in the “left-most” character position. Each subsequent entry is automatically stored in the next higher location and displayed to the immediate “right” of the previous entry. A DISPlay FULL signal is provided after 8 entries; this signal can be used for cascading devices together. A CLeaR pin is provided to clear the memory and reset the location counter. The Random Access mode allows the processor to select the memory address and display digit for each input word. The character multiplex scan runs whenever data is not being entered. It scans the memory and CHARacter drivers, and ensures that the decoding from memory to display is done in the proper sequence. Intercharacter blanking is provided to avoid display ghosting. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 9-21 File Number 3162.1 ICM7243 Pinouts ICM7243A (16-SEGMENT CHARACTER) (PDIP, CERDIP) TOP VIEW VDD 1 40 SEG l SEG m 2 39 SEG g2 SEG e 3 38 SEG b SEG g1 4 37 SEG i SEG k 5 SEG c 6 SEG d1 SEG a1 ICM7243B (14-SEGMENT CHARACTER) (PDIP, CERDIP) TOP VIEW VDD 1 40 SEG m SEG e 2 39 SEG l SEG g1 3 38 SEG g2 SEG k 4 37 SEG b 36 SEG f SEG c 5 36 SEG i 35 SEG d2 SEG d 6 35 SEG f 7 34 DP SEG a 7 34 DP 8 33 SEG h D0 8 33 SEG h SEG a2 9 32 SEG j D1 9 32 SEG j D0 10 31 MODE D2 10 31 MODE D1 11 30 A0/SEN D3 11 30 A0/SEN D2 12 29 A1/CLR D4 12 29 A1/CLR D3 13 28 A2/DISP FULL D5 13 28 A2/DISP FULL D4 14 27 OSC/OFF CS 14 27 OSC/OFF D5 15 26 CHAR 1 CS 15 26 CHAR 1 CS 16 25 CHAR 2 CS 16 25 CHAR 2 WR 17 24 CHAR 3 WR 17 24 CHAR 3 CHAR 8 18 23 CHAR 4 CHAR 8 18 23 CHAR 4 CHAR 7 19 22 VSS CHAR 7 19 22 VSS CHAR 6 20 21 CHAR 5 CHAR 6 20 21 CHAR 5 9-22 ICM7243 Functional Block Diagram Q DATA INPUT D0 - D5 DATA D LATCHES CL 8x6 6 DATA D0 MEMORY CLR ADR CL D1 ONE SHOT WR (NOTE 1) CS CS CS 17 64 x 17 ROM (NOTE 1) (NOTE 1) 3 CL D ADDRESS LATCHES MUX CL D Q CONTROL LATCH A0/SEN A1/CLR 8 D SEL A2/DISP FULL 8 CHARACTER CHARACTER DRIVERS SEL CL EN SEQUENTIAL SEQUENTIAL ADDRESS 3 COUNTER CLR ADDRESS MULITPLEXER MULTIPLEXER AND DECODER OVERFLOW 3 OSC/OFF OSCILLATOR MULTIPLEX OSCILLATOR CHARACTER MULTIPLEX COUNTER NOTE: 1. ICM7243A has only one CS and no CS. ICM7243B has 15 Segments. 9-23 SEGMENT OUTPUTS SEG x 8 CL MODE SEGMENT DRIVERS INTER-CHARACTER BLANKING CHAR N CHARACTER OUTPUTS ICM7243 Absolute Maximum Ratings Thermal Information Supply Voltage VDD - VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V Input Voltage (Any Terminal) . . . . . . . . . . . VDD +0.3V to VSS -0.3V CHARacter Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . 300mA SEGment Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 55 N/A CERDIP Package . . . . . . . . . . . . . . . . 50 10 Maximum Junction Temperature CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VDD = 5V, VSS = 0V, TA = 25oC, Unless Otherwise Specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 4.75 5.0 5.25 V DC CHARACTERISTICS Supply Voltage (VDD - VSS), VSUPP Operating Supply Current, IDD VSUPP = 5.25V, 10 Segments ON, All 8 Characters - 180 - mA Quiescent Supply Current, ISTBY VSUPP = 5.25V, OSC/OFF Pin < 0.5V, CS = VSS - 30 250 µA 2 - - V Input High Voltage, VIH Input Low Voltage, VIL Input Current, IIN VSUPP = 5V, VOUT = 1V CHARacter Drive Current, ICHAR - - 0.8 V -10 - +10 µA 140 190 - mA - - 100 µA CHARacter Leakage Current, ICHLK VSUPP = 5V, VOUT = 2.5V SEGment Drive Current, ISEG SEGment Leakage Current, ISLK 14 19 - mA - 0.01 10 µA DISPlay FULL Output Low, VOL IOL = 1.6mA - - 0.4 V DISPlay FULL Output High, VOH lIH = 100µA 2.4 - - V - 400 - Hz Display Scan Rate, fDS Electrical Specifications Drive levels 0.4V and 2.4V, timing measured at 0.8V and 2.0V. VDD = 5V, TA = 25oC, Unless Otherwise Specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS AC CHARACTERISTICS WR, CLeaR Pulse Width Low, tWPI 300 250 - ns - 250 - ns Data Hold Time, tDH 0 -100 - ns Data Setup Time, tDS 250 150 - ns Address Hold Time, tAH 125 - - ns Address Setup Time, tAS 40 15 - ns ns WR, CLeaR Pulse Width High (Note 1), tWPH CS, CS Setup Time, tCS 0 - - Pulse Transition Time, tT - - 100 ns SEN Setup Time, tSEN 0 -25 - ns 700 480 - ns Display Full Delay, tWDF Capacitance PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Input Capacitance, ClN (Note 2) - 5 - pF Output Capacitance, CO (Note 2) - 5 - pF NOTES: 1. In Sequential mode WR high must be ≥ TSEN +TWDF . 2. For design reference only, not tested. 9-24 ICM7243 Timing Waveforms CS tCS CS tAH tAS VALID ADDRESS tWPI tWC tWHP WRITE tDS tT DATA tT tDH VALID FIGURE 1. RANDOM ACCESS TIMING CHAR 2 CHAR 1 WR CHAR 8 tWPH tSEN CLEAR SEN tWDF DISPLAY FULL FIGURE 2. SEQUENTIAL ACCESS MODE TIMING (MODE = 1) ~5µs ~300µs INTERNAL INTER-CHARACTER BLANKING SIGNAL CHAR 1 CHAR 2 CHAR 3 CHARACTERS DRIVE SIGNALS CHAR 4 CHAR 5 INTER-CHARACTER BLANKING CHAR 6 CHAR 7 CHAR 8 FIGURE 3. DISPLAY CHARACTERS MULTIPLEX TIMING DIAGRAM 9-25 ICM7243 Performance Curves 30 500 VDD = 5.5V VDD = 5.5V ICHAR (mA) ISEG (mA) 20 5.0V 10 400 300 5.0V 200 4.5V 4.5V 100 0 0 1 2 SEGMENT VOLTAGE (V) 3 0 FIGURE 4. SEGMENT CURRENT vs OUTPUT VOLTAGE 1 2 SEGMENT VOLTAGE (V) 3 FIGURE 5. CHARACTER CURRENT VS OUPUT VOLTAGE Pin Descriptions SIGNAL PIN FUNCTION ICM7243A(B) D0 - D5 10 - 15 (8 - 13) Six-Bit ASCll Data input pins (active high). CS, CS 16 (14 - 16) Chip Select from µP address decoder, etc. WR 17 WRite pulse input pin (active low). For an active high write pulse, CS can be used, and WR can be used as CS. MODE 31 Selects data entry MODE. High selects Sequential Access (SA) mode where first entry is displayed in “leftmost” character and subsequent entries appear to the “right”. Low selects the Random Access (RA) mode where data is displayed on the character addressed via A0 - A2 Address pins. A0/SEN 30 In RA mode it is the LSB of the character Address. In SA mode it is used for cascading devices for displays of more than 8 characters (active high enables device controller). A1/CLeaR 29 In RA mode this is the second bit of the address. In SA mode, a low input will CLeaR the Serial Address Counter, the Data Memory and the display. A2/DISPlay FULL 28 In RA mode this is the MSB of the Address. In SA mode, the output goes high after eight entries, indicating DISPlay FULL. OSC/OFF 27 OSCillator input pin. Adding capacitance to VDD will lower the internal oscillator frequency. An external oscillator can be applied to this pin. A low at this input sets the device into a (shutdown) mode, shutting OFF the display and oscillator but retaining data stored in memory. SEG a - SEG m, DP 2 - 9, 32 - 40 (2 - 7), (32 - 40) CHARacter 1 - 8 18 - 21, 23 - 26 SEGment driver outputs. CHARacter driver outputs. 9-26 ICM7243 Test Circuit 17 SEGMENTS CHAR 8 CHAR 7 CHAR 6 CHAR 5 CHAR 4 CHAR 3 CHAR 2 CHAR 1 VDD SEG m SEG e SEG g1 SEG k SEGMENTS SEG c SEG d1 SEG a1 SEG a2 D0 VDD D1 D2 D3 D4 D5 CS WR CHAR 8 CHAR 7 CHAR 6 40 1 2 39 3 38 4 37 5 36 6 35 7 34 8 33 9 32 10 ICM7243A 31 11 30 12 29 13 28 14 27 15 26 16 25 17 24 18 23 19 22 20 21 FIGURE 6. 9-27 SEG l SEG g2 SEG b 8 CHARACTERS SEG i SEG f SEGMENTS SEG d2 DP SEG h SEG j MODE (SA/RA) VDD A0/SEN A1/CLR A2/DISP FULL OSC/OFF CHAR 1 CHAR 2 CHAR 3 CHAR 4 CHAR 5 DISPLAY FULL OUTPUT VDD NC (FOR SA MODE) ICM7243 Typical Applications 8 CHARACTERS 8 CHARACTERS +5V CHAR CHAR SEG SEG RRI RBR8 CLR RBR7 CS CS ICM7243B DISP SEN IM6403 UART RBR1 - RBR6 DRR CLR FULL DISP FULL ETC. CS,WR CS,WR D0 - D5 CS D0 - D5 CS D0 - D5 CS D0 - D5 CS 6 BIT BUS DR +5V +5V +5V 20K OUT ICM7243B SEN WR WR CS CS V+ SEN SEN ICM7243B TR CS ICL7555 FULL CHAR TH ICM7243B CS SEG CHAR SEG 200pF 8 CHARACTERS 8 CHARACTERS FIGURE 7. DRIVING TWO ROWS OF CHARACTERS FROM A SERIAL INPUT 9-28 DISP FULL CLR CLR DELAY DISP ETC. ICM7243 Typical Applications (Continued) 8-CHARACTER LED DISPLAY 8-CHARACTER LED DISPLAY 8 CLR CLR 8 NOTE CLR CHAR SEN +5V MODE DATA BUS +5V +5V VDD VSS CS 6 CLR SEN MODE WR D0 - D5 SEG DISP FULL CS VDD VSS 6 SEN MODE WR D0 - D5 +5V +5V DISP FULL CS VDD VSS 6 WR, (CS) CS, (WR) FIRST 8 CHARACTERS SECOND 8 CHARACTERS NTH 8 CHARACTERS NOTE: 17 for ICM7243A, 15 for ICM7243B. FIGURE 8. MULTICHARACTER DISPLAY USING SEQUENTIAL ACCESS MODE +5V +5V +5V +5V +5V 1K 1.4APEAK 2N6034 100Ω 100Ω 1mA 2N2219 SEG SEG 300Ω ICM7243 1K ICM7243 14Ω (100mAPEAK) 25Ω R ON = 4Ω (100mAPEAK) CHAR CHAR 2N2219 14mA 2N6034 R ON = 4Ω 1K 1.4APEAK GND GND GND GND GND FIGURE 9A. COMMON CATHODE DISPLAY FIGURE 9B. COMMON ANODE DISPLAY FIGURE 9. DRIVING LARGE DISPLAYS 9-29 NOTE CHAR SEG DISP FULL WR D0 - D5 8 NOTE CHAR SEG +5V 8-CHARACTER LED DISPLAY +5V ICM7243 Typical Applications (Continued) 8 CHARACTERS 8 CHARACTERS 8 CHARACTERS 8 CHARACTERS ICM7243A/B ICM7243A/B ICM7243A/B ICM7243A/B CS A2 A1 A0 D0 - D5 WR CS A2 A1 A0 D0 - D5 WR CS A2 A1 A0 D0 - D5 WR CS A2 A1 A0 D0 - D5 WR P22 P21 P20 80C35 80C48 DB7 DB6 6 BIT BUS DB5 - DB0 WR FIGURE 10. RANDOM ACCESS 32-CHARACTER DISPLAY IN A 80C48 SYSTEM Display Font and Segment Assignments a1 f h a2 i g1 e m D5, D4 0 0 1 1 0 1 1 b g2 l d2 0 j k c d1 DP D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 FIGURE 11. ICM7232A 16-SEGMENT CHARACTER FONT WITH DECIMAL POINT 9-30 ICM7243 Display Font and Segment Assignments f (Continued) a1 a a2 h i j g1 e D5, D4 0 0 0 1 1 0 1 1 b g2 m l k d2 d d1 c DP D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 NOTE: Segments a and d appear as 2 segments each, but both halves are driven together. FIGURE 12. ICM7243B 14-SEGMENT CHARACTER FONT WITH DECIMAL POINT VDD SEGMENT DRIVER VLED = 1.6V RTYPICAL = 100µ R SEG x DISPLAY CHARACTER DRIVER CHAR N SEGMENT LEDs RDS(ON) ~ 4Ω VSS FIGURE 13. SEGMENT AND CHARACTER DRIVERS OUTPUT CIRCUIT 9-31 ICM7243 Detailed Description WR, CS, CS - These pins are immediately functionally ANDed, so all actions described as occurring on an edge of WR, with CS and CS enabled, will occur on the equivalent (last) enabling or (first) disabling edge of any of these inputs. The delays from CS pins are slightly (about 5ns) greater than from WR or CS due to the additional inverter required on the former. MODE - The MODE pin input is latched on the falling edge of WR (or its equivalent, see above). The location (in Data Memory) where incoming data will be placed is determined either from the Address pins or the Sequential Address Counter. This is controlled by MODE input. MODE also controls the function of A0/SEN, A1/CLR, and A2/DlSPlay FULL lines. Random Access Mode - When the internal mode latch is set for Random Access (RA) (MODE latched low), the Address input on A0, A1 and A2 will be latched by the falling edge of WR (or its equivalent). Subsequent changes on the Address lines will not affect device operation. This allows use of a multiplexed 6-bit bus controlling both address and data, with timing controlled by WR. Sequential Access Mode - If the internal latch is set for Sequential Access (SA), (MODE latched high), the Serial ENable input or SEN will be latched on the falling edge of WR (or its equivalent). The CLR input is asynchronous, and will force-clear the Sequential Address Counter to address 000 (CHARacter 1), and set all Data Memory contents to 100000 (blank) at any time. The DISPlay FULL output will be active in SA mode to indicate the overflow status of the Sequential Address Counter. If this output is low, and SEN is (latched) high, the contents of the Counter will be used to establish the Data Memory location for the Data input. The Counter is then incremented on the rising edge of WR. If SEN is low, or DISPlay FULL is high, no action will occur. This allows easy “daisy-chaining” of display drivers for multiple character displays in a Sequential Access mode. pin, this frequency can be reduced as far as desired. Alternatively, an external signal can be injected on this pin. The oscillator (or external) frequency is pre-divided by 64, and then further divided by 8 in the Multiplex Counter, to drive the CHARacter drive lines (see Figure 3). An inter-character blanking signal is derived from the pre-divider. An additional comparator on the OSC/OFF input detects a level lower than the relaxation oscillator's range, and blanks the display, disables the DISPlay FULL output (if active), and clears the pre-divider and Multiplex Counter. This puts the circuit in a low-power-dissipation mode in which all outputs are effectively open circuits, except for parasitic diodes to the supply lines. Thus a display connected to the output may be driven by another circuit (including another ICM7243) without driver conflicts. Display Output - The output of the Multiplex Counter is decoded and multiplexed into the address input of the Data Memory, except during WR operations (in Sequential Access mode, with SEN high and DISPlay FULL low), when it scans through the display data. The address decoder also drives the CHARacter outputs, except during the inter-character blanking interval (nominally about 5µs). Each CHARacter output lasts nominally about 300µs, and is repeated nominally every 2.5ms, i.e., at a 400Hz rate (times are based on internal oscillator without external capacitor). The 6 bits read from the Data Memory are decoded in the ROM to the 17 (15 for ICM7243B) segment signals, which drive the SEGment outputs. Both CHARacter and SEGment outputs are disabled during WR operations (with SEN high and DISPlay FULL Low for Sequential Access mode). The outputs may also be disabled by pulling OSC/OFF low. The decode pattern from 6 bits to 17 (15) segments is done by a ROM pattern according to the ASCll font shown. Custom decode patterns can be arranged, within these limitations, by consultation with the factory. Changing Modes - Care must be exercised in any application involving changing from one mode to another. The change will occur only on a falling edge of WR (or its equivalent). When changing mode from Sequential Access to Random Access, note that A2/DlSPlay FULL will be an output until WR has fallen low, and an Address drive here could cause a conflict. When changing from Random Access to Sequential Access, A1/CLR should be high to avoid inadvertent clearing of the Data Memory and Sequential Address Counter. DISPlay FULL will become active immediately after the rising edge of WR. Data Entry - The input Data is latched on the rising edge of WR (or its equivalent) and then stored in the Data Memory location determined as described above. The six Data bits can be multiplexed with the Address information on the same lines semiconductor in Random Access mode. is controlled All Intersil products are Timing manufactured, assembled and tested under ISO9000 quality systems certification. by theproducts WR input. Intersil are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate OSC/OFF - The device includes a relaxation with for its use; nor for any infringements of patents or other rights of third parties which and reliable. However, no responsibility is assumed by Intersiloscillator or its subsidiaries an internal and isa granted nominal frequency of 200kHz. may result from capacitor its use. No license by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. By adding external capacitance toregarding VDD at theCorporation OSC/OFF For information Intersil and its products, see web site 9-32 http://www.intersil.com