ICmic ICM7373/7353/7333 Dual 12/10/8-Bit Voltage Output DACs Serial Interface with Adjustable Output Gain IC MICROSYSTEMS FEATURES • 12/10/8-Bit Monotonic Dual DAC in 16 Lead QSOP Package • Adjustable Output Gain • Rail-to-Rail Voltage Output • 150 µA per DAC at 5V Supply • 100 µA per DAC at 3V Supply • On Board Reference • Serial Interface with three-wire SPI/QSPI and Microwire Interface Compatible • Serial Data Out for Daisy-Chaining • 8 µS Full scale Settling Time OVERVIEW The ICM7373, ICM7353 and ICM7333 are Dual 12-Bit, 10Bit and 8-Bit Rail-to-Rail voltage output DACs respectively, with guaranteed monotonic behavior. These DACs are available in 16 Lead QSOP package. They include adjustable output gain for ease of use and flexibility. The reference output is available on a separate pin and can be used to drive external loads. The operating supply range is 2.7V to 5.5V. The input interface is an easy to use three-wire SPI/QSPI and Microwire compatible interface. The DAC has a double buffered digital input. And there is a serial data output port to allow daisy-chaining applications. APPLICATION • Battery-Powered Applications • Industrial Process Control • Digital Gain and Offset Adjustment BLOCK DIAGRAM REFB REFA ICM7373/7353/7333 DAC A INPUT AND DAC LATCH + - VOA FBA DAC B INPUT AND DAC LATCH + - VOB FBB REFERENCE INPUT CONTROL LOGIC, REGISTERS AND LATCHES REFOUT SDO SDI Rev. A1 SCK CS CLR ICmic reserves the right to change the specifications without prior notice. 1 ICmic ICM7373/7353/7333 Dual 12/10/8-Bit Voltage Output DACs Serial Interface with Adjustable Output Gain IC MICROSYSTEMS PACKAGE 16 Lead QSOP AGND 1 16 VDD VOA 2 15 VOB FBA 3 14 FBB REFA 4 13 REFB CLR 5 12 N/C CS 6 11 REFOUT SDI 7 10 SDO SCK 8 9 DGND TOP VIEW PIN DESCRIPTION (16 Lead QSOP) Pin Name I/O Description 1 AGND I Analog Ground 2 VOA O DAC A Output Voltage 3 FBA I Inverting Input of The Output Amplifier DAC A. Output Amplifier Feedback Input. 4 REFA I Reference Voltage Input for DAC A 5 CLR I Active Low Clear Input (CMOS). Resets All Registers to Zero. DAC outputs go to 0 V 6 CS I Active Low Chip Select (CMOS) 7 SDI I Serial Data Input (CMOS) 8 SCK I Serial Clock Input (CMOS) 9 DGND I Digital Ground 10 SDO O Serial Data Output 11 REFOUT O Reference Output 12 N/C - No Connection 13 REFB I Reference Voltage Input for DAC B 14 FBB I Inverting Input of The Output Amplifier DAC B. Output Amplifier Feedback Input. 15 VOB O DAC B Output Voltage 16 VDD I Supply Voltage Rev. A1 ICmic reserves the right to change the specifications without prior notice. 2 ICmic ICM7373/7353/7333 Dual 12/10/8-Bit Voltage Output DACs Serial Interface with Adjustable Output Gain IC MICROSYSTEMS ABSOLUTE MAXIMUM RATING Symbol Parameter Value Unit VDD Supply Voltage -0.3 to 7.0 IIN Input Current +/- 25.0 VIN_ Digital Input Voltage (SCK, SDI, CS , CLR ) -0.3 to 7.0 VIN_REF Reference Input Voltage -0.3 to 7.0 TSTG Storage Temperature -65 to +150 o C 300 o C TSOL Soldering Temperature V mA V V Note: Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ORDERING INFORMATION Part Operating Temperature Range Package ICM7373 -40 oC to 85 oC 16-Pin QSOP ICM7353 -40 oC to 85 oC 16-Pin QSOP ICM7333 -40 C to 85 C o o 16-Pin QSOP DC ELECTRICAL CHARACTERISTICS (VDD = 2.7V to 5.5V; VOUT unloaded; all specifications TMIN to TMAX unless otherwise noted) Symbol Parameter Test Conditions Min Typ Max Unit DC PERFORMANCE ICM7373 N Resolution 12 Bits DNL Differential Nonlinearity (Notes 1 & 3) 0.4 +1.0 LSB INL Integral Nonlinearity (Notes 1 & 3) 4.0 +12.0 LSB ICM7353 N Resolution 10 Bits DNL Differential Nonlinearity (Notes 1 & 3) 0.1 +1.0 LSB INL Integral Nonlinearity (Notes 1 & 3) 1.0 +3.0 LSB ICM7333 N Resolution DNL Differential Nonlinearity (Notes 1 & 3) 8 0.05 +1.0 LSB Bits INL Integral Nonlinearity (Notes 1 & 3) 0.25 +0.75 LSB GE Gain Error +0.5 OE Offset Error +25 % of FS mV 3.6 V 1.5 mA POWER REQUIREMENTS VDD Supply Voltage IDD Supply Current Rev. A1 2.7 0.6 ICmic reserves the right to change the specifications without prior notice. 3 ICmic ICM7373/7353/7333 Dual 12/10/8-Bit Voltage Output DACs Serial Interface with Adjustable Output Gain IC MICROSYSTEMS Symbol Parameter Test Conditions Min Typ Max Unit VDD V 60 150 mA OUTPUT CHARACTERISTICS Output Voltage Range (Note 3) 0 VOSC Short Circuit Current ROUT Amp Output Impedance At Mid-scale (Note 2) At 0-scale (Note 2) 1.0 100 5.0 200 Ω Ω Output Line Regulation VDD=2.7 to 3.6 V 0.4 3.0 mV/V LOGIC INPUTS VIH Digital Input High (Note 2) VIL Digital Input Low (Note 2) 2.4 V 0.8 V 5 µΑ 1.25 1.3 V 0.8 4.0 mV/V Max Unit Digital Input Leakage REFERENCE VREFOUT Reference Output 1.2 Reference Output Line Regulation AC ELECTRICAL CHARACTERISTICS (VDD = 2.7V to 5.5V; VOUT unloaded; all specifications TMIN to TMAX unless otherwise noted) Symbol SR Parameter Test Conditions Min Slew Rate 2 Settling Time 8 Mid-scale Transition Glitch Energy Note 1: Note 2: Note 3: Typ V/µs µs nV-S 40 Linearity is defined from code 64 to 4095 (ICM7373) Linearity is defined from code 16 to 1023 (ICM7353) Linearity is defined from code 4 to 255 (ICM7333) Guaranteed by design; not tested in production See Applications Information TIMING CHARACTERISTICS (VDD = 2.7V to 5.5V; all specifications TMIN to TMAX unless otherwise noted) Symbol Parameter Test Conditions Min Typ Max Unit t1 SCK Cycle Time (Note 2) 30 ns t2 Data Setup Time (Note 2) 10 ns t3 Data Hold Time (Note 2) 10 ns t4 SCK Falling edge to CS Rising Edge (Note 2) 0 ns t5 CS Falling Edge to SCK Rising Edge (Note 2) 15 ns t6 CS Pulse Width (Note 2) 20 ns Rev. A1 ICmic reserves the right to change the specifications without prior notice. 4 ICmic ICM7373/7353/7333 Dual 12/10/8-Bit Voltage Output DACs Serial Interface with Adjustable Output Gain IC MICROSYSTEMS t6 CS t1 t4 t5 SCK t2 SDI C3 D0 t3 DAC INPUT WORD Figure 1. Serial Interface Timing Diagram Rev. A1 ICmic reserves the right to change the specifications without prior notice. 5 ICmic ICM7373/7353/7333 Dual 12/10/8-Bit Voltage Output DACs Serial Interface with Adjustable Output Gain IC MICROSYSTEMS CS (ENABLE SCK) (UPDATE OUTPUT) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SCK SDI CONTROL WORD DATA WORD INPUT WORD W 0 SDO C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 INPUT WORD W -1 D2 D1 D0 C3 INPUT WORD W 0 Figure 2. Serial Interface Operation Diagram Rev. A1 ICmic reserves the right to change the specifications without prior notice. 6 ICmic ICM7373/7353/7333 Dual 12/10/8-Bit Voltage Output DACs Serial Interface with Adjustable Output Gain IC MICROSYSTEMS CONTENTS OF INPUT SHIFT REGISTER ICM7373 (12-Bit DAC) MSB C3 LSB C2 C1 C0 D11 D10 D9 D8 D7 CONTROL WORD D6 D5 D4 D3 D2 D1 D0 D1 D0 X X X X DATA WORD Figure 3. Contents of ICM7373 Input Shift Register ICM7353 (10-Bit DAC) MSB C3 LSB C2 C1 C0 D9 D8 D7 D6 CONTROL WORD D5 D4 D3 D2 DATA WORD Figure 4. Contents of ICM7353 Input Shift Register ICM7333 (8-Bit DAC) MSB C3 LSB C2 C1 C0 D7 D6 CONTROL WORD D5 D4 D3 D2 D1 D0 DATA WORD X X X X X X X X Figure 5. Contents of ICM7333 Input Shift Register C3 C2 C1 C0 DATA (D0 - D11) FUNCTION 0 0 0 0 Data Load Input Latch DAC A 0 0 0 1 Data Update DAC A 0 0 1 0 Data Load Input Latch and Update DAC A 0 0 1 1 Data Load Input Latch DAC B 0 1 0 0 Data Update DAC B 0 1 0 1 Data Load Input Latch and Update DAC B 0 1 1 0 X No Operation 0 1 1 1 X No Operation 1 0 0 0 X No Operation 1 0 0 1 X No Operation 1 0 1 0 X No Operation 1 0 1 1 X No Operation 1 1 0 0 Data Load Input Latch All DACs 1 1 0 1 Data Update All DACs 1 1 1 0 Data Load Input Latch and Update All DACs 1 1 1 1 X No Operation Table 1. Serial Interface Input Word Rev. A1 ICmic reserves the right to change the specifications without prior notice. 7 ICmic IC MICROSYSTEMS DETAILED DESCRIPTION The ICM7373 is a 12-bit voltage output dual DAC. The ICM7353 is the 10-bit version of this family and the ICM7333 is the 8-bit version. This family of DACs employs a resistor string architecture guaranteeing monotonic behavior. There is a 1.25V onboard reference and an operating supply range of 2.7V to 5.5V. Reference Input Determine the output voltage using the following equation: VOUT = VREF x (D / (2n)) Where D is the numeric value of DAC’s decimal input code, VREF is the reference voltage and n is number of bits, i.e. 12 for ICM7373, 10 for ICM7353 and 8 for ICM7333. Reference Output The reference output is nominally 1.25V and is brought out to a separate pin and can be used to drive external loads. The outputs will nominally swing from 0 to 2.5V. Output Amplifier The dual DAC has 2 output amplifiers with a rail-to-rail output swing. The actual swing of the output amplifiers will be limited by offset error and gain error. See the Applications Information Section for a more detailed discussion. The 2 output amplifier’s inverting input of 2 DACs are available to the user, allowing force and sense capability for remote sensing and specific gain adjustment. The unity gain can be provided by connecting the inverting input to the output. The output amplifier can drive a load of 2.0 k to VDD or GND in parallel with a 500 pF load capacitance. The output amplifier has a full-scale typical settling time of 8 µs and it dissipates about 100 µA with a 3V supply voltage. Serial Interface and Input Logic This dual DAC family uses a standard 3-wire connection compatible with SPI/QSPI and Microwire interfaces. Data is loaded in 16-bit words which consist of 4 address and control bits (MSBs) followed by 12 bits of data (see table 1). The ICM7353 has the last 2 LSBs as don’t care and the ICM7333 has the last 4 LSBs as don’t care. The DAC is double buffered with an input latch and a DAC latch. ICM7373/7353/7333 Dual 12/10/8-Bit Voltage Output DACs Serial Interface with Adjustable Output Gain contents are transferred to a bank of 16 latches (see Figure 2.). The 4 bit control word (C3~C0) is then decoded and the DAC is updated or loaded depending on the control word (see Table 1). The DAC has a double-buffered input with an input latch and a DAC latch. The DAC output will swing to its new value when data is loaded into the DAC latch. The user has three options: loading only the input latch, updating the DAC with data previously loaded into the input latch or loading the input latch and updating the DAC at the same time with a new code. Serial Data Output SDO (Serial Data Output) is the internal shift register’s output. This pin can be used as the data output pin for Daisy-Chaining and data readback. And it is compatible with SPI/QSPI and Microwire interfaces. Power-On Reset There is a power-on reset on board that will clear the contents of all the latches to all 0s on power-up and the DAC voltage output will go to ground. APPLICATIONS INFORMATION Power Supply Bypassing and Layout Considerations As in any precision circuit, careful consideration has to be given to layout of the supply and ground. The return path from the GND to the supply ground should be short with low impedance. Using a ground plane would be ideal. The supply should have some bypassing on it. A 10 µF tantalum capacitor in parallel with a 0.1 µF ceramic with a low ESR can be used. Ideally these would be placed as close as possible to the device. Avoid crossing digital and analog signals, specially the reference, or running them close to each other. Output Swing Limitations The ideal rail-to-rail DAC would swing from GND to VDD. However, offset and gain error limit this ability. Figure 6 illustrates how a negative offset error will affect the output. The output will limit close to ground since this is single supply part, resulting in a dead-band area. As a larger input is loaded into the DAC the output will eventually rise above ground. This is why the linearity is specified for a starting code greater than zero. Figure 7 illustrates how a gain error or positive offset error will affect the output when it is close to VDD. A positive gain error or positive offset will cause the output to be limited to the positive supply voltage resulting in a deadband of codes close to full-scale. Serial Data Input SDI (Serial Data Input) pin is the data input pin for All DACs. Data is clocked in on the rising edge of SCK which has a Schmitt trigger internally to allow for noise immunity on the SCK pin. This specially eases the use for optocoupled interfaces. The Chip Select pin which is the 6th pin of 16 QSOP package is active low. This pin must be low when data is being clocked into the part. After the 16th clock pulse the Chip Select pin must be pulled high (level-triggered) for the data to be transferred to an input bank of latches. This pin also disables the SCK pin internally when pulled high and the SCK pin must be low before this pin is pulled back low. As the Chip Select pin is pulled high the shift register Rev. A1 ICmic reserves the right to change the specifications without prior notice. 8 ICmic ICM7373/7353/7333 Dual 12/10/8-Bit Voltage Output DACs Serial Interface with Adjustable Output Gain IC MICROSYSTEMS DEADBAND NEGATIVE OFFSET Figure 6. Effect of Negative Offset OFFSET AND GAIN ERROR VDD DEADBAND POSITIVE OFFSET Figure 7. Effect of Gain Error and Positive Offset Rev. A1 ICmic reserves the right to change the specifications without prior notice. 9 ICmic ICM7373/7353/7333 Dual 12/10/8-Bit Voltage Output DACs Serial Interface with Adjustable Output Gain IC MICROSYSTEMS PACKAGE INFORMATION 16 QSOP A 16 9 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (3,99) 0.150 (3,81) GAUGE PLANE 0.010 (0,25) 0° - 8° 0.035 (0,89) 0.016 (0,40) 1 8 0.012 (0,30) 0.008 (0,20) 0.025 (0,64) SEATING PLANE 0.010 (0,25) 0.004 (0,10) 0.069 (1,75) MAX 0.069 (1,75) MAX DIM A MAX A MIN PINS 16 20 0.197 (5,00) 0.344 (8,74) 0.189 (4,80) 0.337 (8,56) Note: 1. All Linear dimensions are in inches (millimeters) format 2. This drawing is subject to change without notice 3. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). 4. Falls within JEDEC MO-137. Rev. A1 ICmic reserves the right to change the specifications without prior notice. 10 ICmic ICM7373/7353/7333 IC MICROSYSTEMS DUAL 12/10/8-BIT VOLTAGE-OUTPUT DACS ORDERING INFORMATION ICM73X3 P G Device 7 - ICM7373 5 - ICM7353 3 - ICM7333 Rev. A1 G = RoHS Compliant Lead-Free package. Blank = Standard package. Non lead-free. Package Q = 16-Lead QSOP ICmic reserves the right to change the specifications without prior notice. 11