ICS1572 Integrated Circuit Systems, Inc. User Programmable Differential Output Graphics Clock Generator Description Features The ICS1572 is a high performance monolithic phase-locked loop (PLL) frequency synthesizer. Utilizing ICS’s advanced CMOS mixed-mode technology, the ICS1572 provides a low cost solution for high-end video clock generation in workstations and high-end PC applications. • The ICS1572 has differential video clock outputs (CLK+ and CLK-) that are compatible with industry standard video DACs. Another clock output, LOAD, is provided whose frequency is derived from the main clock by a programmable divider. An additional clock output is available, LD/N2, which is derived from the LOAD frequency and whose modulus may also be programmed. • • • • • Supports high-resolution graphics - CLK output to 180 MHz Eliminates need for multiple ECL output crystal oscillators Fully programmable synthesizer capability - not just a clock multiplier Available in 20-pin 300-mil wide body SOIC package Available in both parallel (101) and serial (301) programming versions Circuit included for reset of Brooktree RAMDAC pipeline delay Applications Operating frequencies are fully programmable with direct control provided for reference divider, pre-scaler, feedback divider and post-scaler. • • • Reset of the pipeline delay on Brooktree RAMDACs may be performed under register control. Outputs may also be set to desired states to facilitate circuit board testing. Workstations AutoCad Accelerators High-end PC graphics systems ICS1572-101 Pinout N.C. AD0 XTAL1 XTAL2 STROBE VSS VSS LOAD LD/N2 N.C. LOOP FILTER XTAL1 CRYSTAL OSCILLATOR XTAL2 EXTFBK BLANK /R PHASEFREQUENCY DETECTOR CHARGE PUMP VCO PRESCALER (-301 only) /M MUX /A FEEDBACK DIVIDER PROGRAMMING INTERFACE 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 N.C. AD1 AD2 VDD VDD VDDO IPRG CLK+ CLKN.C. ICS1572-301 Pinout MUX /2 DIFF. OUTPUT /4 CLK+ CLK− / N1 MUX DRIVER LOAD / N2 DRIVER LD/N2 N.C. AD0 XTAL1 XTAL2 STROBE VSS VSS LOAD LD/N2 N.C. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 N.C. AD1 AD2 VDD VDD VDDO IPRG CLK+ CLKN.C. Figure 1 ICS1572RevC093094 RAMDAC is a trademark of Brooktree Corporation. ICS1572 Overview PLL Post-Scaler The ICS1572 is ideally suited to provide the graphics system clock signals required by high-performance video DACs. Fully programmable feedback and reference divider capability allow virtually any frequency to be generated, not just simple multiples of the reference frequency. The ICS1572 uses the latest generation of frequency synthesis techniques developed by ICS and is completely suitable for the most demanding video applications. A programmable post-scaler may be inserted between the VCO and the CLK+ and CLK- outputs of the ICS1572. This is useful in generating of lower frequencies, as the VCO has been optimized for high-frequency operation. The post-scaler allows the selection of: • • • • PLL Synthesizer Description Ratiometric Mode The ICS1572 generates its output frequencies using phaselocked loop techniques. The phase-locked loop (or PLL) is a closed-loop feedback system that drives the output frequency to be ratiometrically related to the reference frequency provided to the PLL (see Figure 1). The reference frequency is generated by an on-chip crystal oscillator or the reference frequency may be applied to the ICS1572 from an external frequency source. VCO frequency divided by 2 VCO frequency divided by 4 Internal register bit (AUXCLK) value Load Clock Divider The ICS1572 has an additional programmable divider (referred to in Figure 1 as the N1 divider) that is used to generate the LOAD clock frequency for the video DAC. The modulus of this divider may be set to 3, 4, 5, 6, 8, or 10 under register control. The design of this divider permits the output duty factor to be 50/50, even when an odd modulus is selected. The input frequency to this divider is the output of the PLL post-scaler described above. The phase-frequency detector shown in the block diagram drives the voltage-controlled oscillator, or VCO, to a frequency that will cause the two inputs to the phase-frequency detector to be matched in frequency and phase. This occurs when: F(VCO): = VCO frequency F(XTAL1) . Feedback Divider Reference Divider Digital Inputs - ICS1572-101 Option The AD0-AD3 pins and the STROBE pin are used to load all control registers of the ICS1572 (-101 option). The AD0-AD3 and STROBE pins are each equipped with a pull-up and will be at a logic HIGH level when not connected. They may be driven with standard TTL or CMOS logic families. This expression is exact; that is, the accuracy of the output frequency depends solely on the reference frequency provided to the part (assuming correctly programmed dividers). The VCO gain is programmable, which permits the ICS1572 to be optimized for best performance at all operating frequencies. The address of the register to be loaded is latched from the AD0-AD3 pins by a negative edge on the STROBE pin. The data for that register is latched from the AD0-AD3 pins by a positive edge on the STROBE pin. See Figure 2 for a timing diagram. After power-up, the ICS1572-101 requires 32 register writes for new programming to become effective. Since only 13 registers are used at present, the programming system can perform 19 “dummy” writes to address 13 or 14 to complete the sequence. The reference divider may be programmed for any modulus from 1 to 128 in steps of one. The feedback divider may be programmed for any modulus from 37 through 391 in steps of one. Any even modulus from 392 through 782 can also be achieved by setting the “double” bit which doubles the feedback divider modulus. The feedback divider makes use of a dual-modulus prescaler technique that allows the programmable counters to operate at low speed without sacrificing resolution. This is an improvement over conventional fixed prescaler architectures that typically impose a factor-of-four penalty (or larger) in this respect. Table 1 permits the derivation of “A” & “M” counter programming directly from desired modulus. 2 ICS1572 An additional control pin on the ICS1572-301, BLANK can perform either of two functions. It may be used to disable the phase-frequency detector in line-locked applications. Alternatively, the BLANK pin may be used as a synchronous enable for VRAM shift clock generation. See sections on Line-Locked Operations and VRAM shift clock generation for details. This allows the synthesizer to be completely programmed for the desired frequency before it is made active. Once the part has been “unlocked” by the 32 writes, programming becomes effective immediately. ALL registers identified in the data sheet (0-9, 11, 12 & 15) MUST be written upon initial programming. The programming registers are not initialized upon power-up, but the latched outputs of those registers are. The latch is made transparent after 32 register writes. If any register has not been written, the state upon power-up (random) will become effective. Registers 13 & 14 physically do not exist. Register 10 does exist, but is reserved for future expansion. To insure compatibility with possible future modifications to the database, ICS recommends that all three unused locations be written with zero. Output Description The differential output drivers, CLK+ and CLK, are currentmode and are designed to drive resistive terminations in a complementary fashion. The outputs are current-sinking only, with the amount of sink current programmable via the IPRG pin. The sink current, which is steered to either CLK+ or CLK-, is approximately four times the current supplied to the IPRG pin. For most applications, a resistor from VDDO to IPRG will set the current to the necessary precision. See Figure 6 for output characteristics. ICS1572-101 Register Loading 5 STROBE 1 AD0-AD3 2 3 ADDRESS VALID The LOAD output is a high-current CMOS type drive whose frequency is controlled by a programmable divider that may be selected for a modulus of 3, 4, 5, 6, 8, or 10. It may also be suppressed under register control. 4 DATA VALID The LD/N2 output is high-current CMOS type drive whose frequency is derived from the LOAD output. The programmable modulus may range from 1 to 512 in steps of one. Figure 2 Digital Inputs - ICS1572-301 Option Pipeline Delay Reset Function The programming of the ICS1572-301 is performed serially by using the DATCLK, DATA, and HOLD~pins to load an internal shift register. The ICS1572 implements the clocking sequence required to reset the pipeline delay on Brooktree RAMDACs. This sequence can be generated by setting the appropriate register bit (DACRST) to a logic 1 and then resetting to logic 0. DATA is shifted into the register on the rising edge of DATCLK. The logic value on the HOLD~ pin is latched at the same time. When HOLD~ is low, the shift register may be loaded without disturbing the operation of the ICS1572. When high, the shift register outputs are transferred to the control registers, and the new programming information becomes active. Ordinarily, a high level should be placed on the HOLD~ pin when the last data bit is presented. See Figure 3 for the programming sequence. When changing frequencies, it is advisable to allow 500 microseconds after the new frequency is selected to activate the reset function. The output frequency of the synthesizer should be stable enough at that point for the video DAC to correctly execute its reset sequence. See Figure 4 for a diagram of the pipeline delay reset sequence. Pipeline Delay Reset Timing ICS1572-301 Register Loading 8 DATCLK 6 DATA STROBE or DATCLK 7 DATA_1 DATA_2 DATA_56 11 10 9 CLK+ 12 TCLK HOLD LOAD Figure 3 Figure 4 3 ICS1572 ICS1572-101 The ICS1572-101 supports phase detector disable via a special control mode. When the PDRSTEN (phase detector reset enable) bit is set, a high level on AD3 will disable PLL locking. Reference Oscillator and Crystal Selection The ICS1572 has circuitry on-board to implement a Pierce oscillator with the addition of only one external component, a quartz crystal. Pierce oscillators operate the crystal in anti(also called parallel-) resonant mode. See the AC Characteristics for the effective capacitive loading to specify when ordering crystals. ICS1572-301 The ICS1572-301 supports phase detector disable via the BLANK pin. When the PDRSTEN bit is set, a high level on the BLANK input will disable PLL locking. Series-resonant crystals may also be used with the ICS1572. Be aware that the oscillation frequency will be slightly higher than the frequency that is stamped on the can (typically 0.0250.05%). External Feedback Operation The ICS1572-301 option also supports the inclusion of an external counter as the feedback divider of the PLL. This mode is useful in graphic systems that must be “genlocked” to external video sources. As the entire operation of the phase-locked loop depends on having a stable reference frequency, we recommend that the crystal be mounted as closely as possible to the package. Avoid routing digital signals or the ICS1572 outputs underneath or near these traces. It is also desirable to ground the crystal can to the ground plane, if possible. When the EXTFBEN bit is set to logic 1, the phase-frequency detector will use the EXTFBK pin as its feedback input. The loop phase will be locked to the rising edges of the signal applied to the EXTFBK input. If an external reference frequency source is to be used with the ICS1572, it is important that it be jitter-free. The rising and falling edges of that signal should be fast and free of noise for best results. VRAM Shift Clock Generation The ICS1572-301 option supports VRAM shift clock generation and interruption. By programming the N2 counter to divide by 1, the LD/N2 output becomes a duplicate of the LOAD output. When the SCEN bit is set, the LD/N2 output may be synchronously started and stopped via the blank pin. When BLANK is high, the LD/N2 will be free-running and in phase with LOAD. When BLANK is taken low, the LD/N2 output is stopped at a low level. See Figure 5 for a diagram of the sequence. Note that this use of the BLANK pin precludes its use for phase comparator disable (see Line-Locked Operation). The loop phase is locked to the falling edges of the XTAL1 input signals. Line-Locked Operation The ICS1572 supports line-locked clock applications by allowing the LOAD (N1) and N2 divider chains to act as the feedback divider for the PLL. The N1 and N2 divider chains allow a much larger modulus to be achieved than the PLL’s own feedback divider. Additionally, the output of the N2 counter is accessible off-chip for performing horizontal reset of the graphics system, where necessary. This mode is set under register control (ALTLOOP bit). The reference divider (R counter) is set to divide by 1 in this mode, and the HSYNC signal of the external video will be supplied to the XTAL1 input. The output frequency of the synthesizer will then be: VRAM Shift Clock Control BLANK LOAD F(CLK) : = F (XTAL1) . N1 . N2. LD/N2 By using the phase-detector hardware disable mode, the PLL can be made to free-run at the beginning of the vertical interval of the external video, and can be reactivated at its completion. Figure 5 4 ICS1572 • Power-On Initialization The ICS1572 has an internal power-on reset circuit that performs the following functions: 1) Sets the multiplexer to pass the reference frequency to the CLK+ and CLK- outputs. 2) Selects the modulus of the N1 divider (for the LOAD clock) to be four. Phase Detector Gain: For most graphics applications and divider ranges, set P[1,0] = 10 and set P[2] = 1. Under some circumstances, setting the P[2] bit “on” can reduce jitter. During 1572 operation at exact multiples of the crystal frequency, P[2] bit = 0 may provide the best jitter performance. Board Test Support It is often desirable to statically control the levels of the output pins for circuit board test. The ICS1572 supports this through a register programmable mode, AUXEN. When this mode is set, two register bits directly control the logic levels of the CLK+/CLK- pins and the LOAD pin. This mode is activated when the S[0] and S[1] bits are both set to logic 1. See Register Mapping for details. These functions should allow initialization of most graphics systems that cannot immediately provide for register programming upon system power-up. Because the power-on reset circuit is on the VDD supply, and because that supply is filtered, care must be taken to allow the reset to de-assert before programming. A safe guideline is to allow 20 microseconds after the VDD supply reaches 4 volts. Power Supplies and Decoupling Programming Notes • • • The ICS1572 has two VSS pins to reduce the effects of package inductance. Both pins are connected to the same potential on the die (the ground bus). BOTH of these pins should connect to the ground plane of the video board as close to the package as is possible. VCO Frequency Range: Use the post-divider to keep the VCO frequency as high as possible within its operating range. Divider Range: For best results in normal situations (i.e., pixel clock generation for hi-res displays), keep the reference divider modulus as short as possible (for a frequency at the output of the reference divider in the few hundred kHz to several MHz range). If you need to go to a lower phase comparator reference frequency (usually required for increased frequency accuracy), that is acceptable, but jitter performance will suffer somewhat. VCO Gain Programming: Use the minimum gain which can reliably achieve the VCO frequency desired, as shown here: VCO GAIN 4 5 6 7 The ICS1572 has a VDDO pin which is the supply of +5 volt power to all output drivers. This pin should be connected to the power plane (or bus) using standard high-frequency decoupling practice. That is, capacitors should have low series inductance and be mounted close to the ICS1572. The VDD pin is the power supply pin for the PLL synthesizer circuitry and other lower current digital functions. We recommend that RC decoupling or zener regulation be provided for this pin (as shown in the recommended application circuitry). This will allow the PLL to “track” through power supply fluctuations without visible effects. See Figure 7 for typical external circuitry. MAX FREQUENCY 120 MHz 200 MHz 230 MHz * * SPECIAL APPLICATION. Contact factory for custom product above 230 MHz. Figure 6 5 ICS1572 ICS1572 Typical Interface DATA BUS SELECT 1 2 3 4 5 6 7 8 9 10 N.C. AD0 XTAL1 XTAL2 STROBE VSS VSS LOAD LD/N2 N.C. N.C AD1 AD2 AD3 VDD VDDO IPRG CLK+ CLKN.C. 20 19 18 17 16 15 14 13 12 11 +5V + 120 120 TO RAMDAC 390 Figure 3 6 390 ICS1572 Register Mapping - ICS1572-101 (Parallel Programming Option) NOTE: IT IS NOT NECESSARY TO UNDERSTAND THE FUNCTION OF THESE BITS TO USE THE ICS1572. PC SOFTWARE IS AVAILABLE FROM ICS TO AUTOMATICALLY GENERATE ALL REGISTER VALUES BASED ON REQUIREMENTS. CONTACT FACTORY FOR DETAILS. REG# BIT(S) BIT REF. DESCRIPTION 0 1 0-3 0-2 R[0]..R[3] R[4]..R[6] Reference divider modulus control bits Modulus = value + 1 2 0-3 A[0]..A[3] Controls A counter. When set to zero, modulus=7. Otherwise, modulus=7 for “value” underflows of the prescaler, and modulus=6 thereafter until M counter underflows. 3 4 0-3 0-1 M[0]..M[3] M[4]..M[5] M counter control bits Modulus = value + 1 4 3 DBLFREQ Doubles modulus of dual-modulus prescaler (from 6/7 to 12/14). 5 0-2 N1[0]..N1[2] Sets N1 modulus according to this table. These bits are set to implement a divide-by-four on power-up. N1[2] 0 0 0 0 1 1 1 1 6 7 0-3 0-3 N2[0]..N2[3] N2[4]..N2[7] 8 3 N2[8] 8 0-2 V[0]..V[1] N1[1] 0 0 1 1 0 0 1 1 N1[0] 0 1 0 1 0 1 0 1 RATIO 3 4 4 5 6 8 8 10 Sets the modulus of the N2 divider. Modulus = value + 1 The input of the N2 divider is the output of the N1 divider in all clock modes except AUXEN. Sets the gain of the VCO. V[2] V[1] V[0] 1 1 1 1 0 0 1 1 0 1 0 1 7 VCO GAIN (MHz/VOLT) 30 45 60 80 ICS1572 REG# BIT(S) 9 0-1 BIT REF. P[0]..P[1] DESCRIPTION Sets the gain of the phase detector according to this table. P[1] 0 0 1 1 P[0] 0 1 0 1 GAIN (uA/radian) 0.05 0.15 0.5 1.5 9 3 [P2] Phase detector tuning bit. Normally should be set to one. 11 0-1 S[0]..S[1] PLL post-scaler/test mode select bits S[1] S[0] DESCRIPTION 0 0 Post-scaler=1. F(CLK)=F(PLL). The output of the N1 divider drives the LOAD output which, in turn, drives the N2 divider. 0 1 Post-scaler=2. F(CLK)=F(PLL)/2. The output of the N1 divider drives the LOAD output which, in turn, drives the N2 divider. 1 0 Post-scaler=4. F(CLK)=F(PLL)/4. The output of the N1 divider drives the LOAD output which, in turn, drives the N2 divider. 1 1 AUXEN CLOCK MODE. The AUXCLK bit drives the differential outputs CLK+ and CLK- and the AUXN1 bit drives the LOAD output which, in turn, drives the N2 divider. 11 2 AUX_CLK When in the AUXEN clock mode, this bit controls the differential outputs. 11 3 AUX_N1 When in the AUXEN clock mode, this bit controls the LOAD output (and consequently the N2 output according to its programming). 12 0 RESERVED Must be set to zero. 12 1 JAMPLL Tristates phase detector outputs; resets phase detector logic, and resets R, A, M, and N2 counters. 12 2 DACRST Set to zero for normal operation. When set to one, the CLK+ output is kept high and the CLK- output is kept low. (All other device functions are unaffected.) When returned to zero, the CLK+ and CLK- outputs will resume toggling on a rising edge of the LD output (+/- 1 CLK period). To initiate a RAMDAC reset sequence, simply write a one to this register bit followed by a zero. 12 3 SELXTAL When set to logic 1, passes the reference frequency to the post-scaler. 15 0 ALTLOOP Controls substitution of N1 and N2 dividers into feedback loop of PLL. When this bit is a logic 1, the N1 and N2 dividers are used. 15 3 PDRSTEN Phase-detector reset enable control bit. When this bit is set, the AD3 pin becomes a transparent reset input to the phase detector. See LINE-LOCKED CLOCK GENERATION section for more details on the operation of this function. 8 ICS1572 Register Mapping - ICS1572-301 (Serial Programming Option) NOTE: IT IS NOT NECESSARY TO UNDERSTAND THE FUNCTION OF THESE BITS TO USE THE ICS1572. PC SOFTWARE IS AVAILABLE FROM ICS TO AUTOMATICALLY GENERATE ALL REGISTER VALUES BASED ON REQUIREMENTS. CONTACT FACTORY FOR DETAILS. BIT(S) BIT REF. 1-3 N1[0]..N1[2] DESCRIPTION Sets N1 modulus according to this table. These bits are set to implement a divide-by-four on power-up. N1[2] 0 0 0 0 1 1 1 1 N1[1] 0 0 1 1 0 0 1 1 N1[0] 0 1 0 1 0 1 0 1 RATIO 3 4 4 5 6 8 8 10 4 RESERVED Set to zero. 5 RESERVED MUST be set to zero.If this bit is ever programmed for a logic one, device operation will cease and further serial data load into the registers will be inhibited until a power-off/power-on sequence. 6 JAMPLL Tristates phase detector outputs, resets phase detector logic, and resets R, A, M, and N2 counters. 7 DACRST Set to zero for normal operations. When set to one, the CLK+ output is kept high and the CLK- output is kept low. (All other device functions are unaffected.) When returned to zero, the CLK+ and CLK- outputs will resume toggling on a rising edge of the LD output (+/−1 CLK period). To initiate a RAMDAC reset sequence, simply write a one to this register bit followed by a zero. 8 SELXTAL When set to logic 1, passes the reference frequency to the post-scaler. 9 ALTLOOP Controls substitution of N1 and N2 dividers into feedback loop of PLL. When this bit is a logic 1, the N1 and N2 dividers are used. 10 SCEN VRAM shift clock enable bit. When logic 1, the BLANK pin can be used to disable the LD/N2 output. 11 EXTFBKEN External PLL feedback select. When logic 1, the EXTFBK pin is used for the phase-frequency detector feedback input. 12 PDRSTEN Phase detector reset enable control bit. When this bit is set, a high level on the BLANK input will disable PLL locking. See LINE-LOCKED CLOCK GENERATION section for more details on the operation of this function. 9 ICS1572 BIT(S) BIT REF. 13-14 S[0]..S[1] DESCRIPTION PLL post-scaler/test mode select bits. S[1] S[0] DESCRIPTION 0 0 Post-scaler=1. F(CLK)=F(PLL). The output of the N1 divider drives the LOAD output which, in turn, drives the N2 divider. 0 1 Post-scaler=2. F(CLK)=F(PLL)/2. The output of the N1 divider drives the LOAD output which, in turn, drives the N2 divider. 1 0 Post-scaler=4. F(CLK)=F(PLL)/4. The output of the N1 divider drives the LOAD output which, in turn, drives the N2 divider. 1 1 AUXEN CLOCK MODE. The AUXCLK bit drives the differential outputs CLK+ and CLK- and the AUXN1 bit drives the LOAD output which, in turn, drives the N2 divider. 15 AUX_CLK When in the AUXEN clock mode, this bit controls the differential outputs. 16 AUX_N1 When in the AUXEN clock mode, this bit controls the N1 output (and consequently the N2 output according to its programming). 17-24 28 25-27 N2[0]..N2[7] N2[8] V[0]..V[2] 29-30 P[0]..P[1] Sets the modulus of the N2 divider. The input of the N2 divider is the output of the N1 divider in all clock modes except AUXEN. Sets the gain of VCO. V[2] V[1] V[0] 1 1 1 1 0 0 1 1 0 1 0 1 VCO GAIN (MHz/VOLT) 30 45 60 80 Sets the gain of the phase detector according to this table. P[1] 0 0 1 1 P[0] 0 1 0 1 GAIN (uA/radian) 0.05 0.15 0.5 1.5 31 RESERVED Set to zero. 32 P[2] Phase detector tuning bit. Should normally be set to one. 10 ICS1572 BIT(S) BIT REF. DESCRIPTION 33-38 M[0]..M[5] M counter control bits Modulus = value +1 39 RESERVED Set to zero. 40 DBLFREQ Doubles modulus of dual-modulus prescaler (from 6/7 to 12/14). 41-44 A[0]..A[3] Controls A counter. When set to zero, modulus=7. Otherwise, modulus=7 for “value” underflows of the prescaler, and modulus=6 thereafter until M counter underflows. 45-48 RESERVED Set to zero. 49-55 R[0]..R[6] Reference divider modulus control bits Modulus = value + 1 56 RESERVED Set to zero. 11 ICS1572 Table 1 - “A” & “M” Divider Programming Feedback Divider Modulus Table A[2]..A[0]M[5]..M[0] 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 001 13 19 25 31 37 43 49 55 61 67 73 79 85 91 97 103 109 115 121 127 133 139 145 151 157 163 169 175 181 187 193 010 20 26 32 38 44 50 56 62 68 74 80 86 92 98 104 110 116 122 128 134 140 146 152 158 164 170 176 182 188 194 011 27 33 39 45 51 57 63 69 75 81 87 93 99 105 111 117 123 129 135 141 147 153 159 165 171 177 183 189 195 100 34 40 46 52 58 64 70 76 82 88 94 100 106 112 118 124 130 136 142 148 154 160 166 172 178 184 190 196 101 41 47 53 59 65 71 77 83 89 95 101 107 113 119 125 131 137 143 149 155 161 167 173 179 185 191 197 110 48 54 60 66 72 78 84 90 96 102 108 114 120 126 132 138 144 150 156 162 168 174 180 186 192 198 111 000 55 61 67 73 79 85 91 97 103 109 115 121 127 133 139 145 151 157 163 169 175 181 187 193 199 7 14 21 28 35 42 49 56 63 70 77 84 91 98 105 112 119 126 133 140 147 154 161 168 175 182 189 196 203 210 217 224 A[2]..A[0]M[5]..M[0] 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 001 010 011 100 101 110 111 000 199 205 211 217 223 229 235 241 247 253 259 265 271 277 283 289 295 301 307 313 319 325 331 337 343 349 355 361 367 373 379 385 200 206 212 218 224 230 236 242 248 254 260 266 272 278 284 290 296 302 308 314 320 326 332 338 344 350 356 362 368 374 380 386 201 207 213 219 225 231 237 243 249 255 261 267 273 279 285 291 297 303 309 315 321 327 333 339 345 351 357 363 369 375 381 387 202 208 214 220 226 232 238 244 250 256 262 268 274 280 286 292 298 304 310 316 322 328 334 340 346 352 358 364 370 376 382 388 203 209 215 221 227 233 239 245 251 257 263 269 275 281 287 293 299 305 311 317 323 329 335 341 347 353 359 365 371 377 383 389 204 210 216 222 228 234 240 246 252 258 264 270 276 282 288 294 300 306 312 318 324 330 336 342 348 354 360 366 372 378 384 390 205 211 217 223 229 235 241 247 253 259 265 271 277 283 289 295 301 307 313 319 325 331 337 343 349 355 361 367 373 379 385 391 231 238 245 252 259 266 273 280 287 294 301 308 315 322 329 336 343 350 357 364 371 378 385 392 399 406 413 420 427 434 441 448 Notes: To use this table, find the desired modulus in the table. Follow the column up to find the A divider programming values. Follow the row to the left to find the M divider programming. Some feedback divisors can be achieved with two or three combinations of divider settings. Any are acceptable for use. The formula for the effective feedback modulus is: N =[(M +1) . 6] +A except when A=0, then: N=(M +1) . 7 Under all circumstances: A≤ M 12 ICS1572 Pin Descriptions - ICS1572-101 PIN# 13 12 8 3 4 2 19 18 17 9 5 16 15 14 6,7 1,10,11,20 NAME CLK+ CLK− LOAD XTAL1 XTAL2 AD0 AD1 AD2 AD3 LD/N2 STROBE VDD VDDO IPRG VSS NC DESCRIPTION Clock out (non-inverted) Clock out (inverted) Load output. This output is normally at the CLK frequency divided by N1. Quartz crystal connection 1/external reference frequency input Quartz crystal connection 2 Address/Data Bit 0 (LSB) Address/Data Bit 1 Address/Data Bit 2 Address/Data Bit 3 (MSB) Divided LOAD output. See text. Control for address/data latch PLL system power (+5V. See application diagram.) Output stage power (+5V) Output stage current set Device ground. Both pins must be connected to the same ground potential. Not connected Pin Descriptions - ICS1572-301 PIN# 13 12 8 3 4 5 19 18 17 9 2 16 15 14 6,7 1,10,11,20 NAME CLK+ CLK− LOAD XTAL1 XTAL2 DATCLK DATA HOLD~ BLANK LD/N2 EXTFBK VDD VDDO IPRG VSS NC DESCRIPTION Clock out (non-inverted) Clock out (inverted) Load output. This output is normally at the CLK frequency divided by N1. Quartz crystal connection 1/external reference frequency input Quartz crystal connection 2 Data Clock (Input) Serial Register Data (Input) HOLD (Input) Blanking (Input). See Text. Divided LOAD output/shift clock. See text. External feedback connection for PLL (input). See text. PLL system power (+5V. See application diagram.) Output stage power (+5V) Output stage current set Device ground. Both pins must be connected. Not connected 13 ICS1572 Absolute Maximum Ratings VDD, VDDO (measured to VSS) . . . . . . . . . . . . . . . . . . . . . . Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Soldering Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V VSS-0.5 to VDD + 0.5V VSS-0.5 to VDDO + 0.5V -55 to 125°C -65 to 150°C 175°C 260°C Recommended Operating Conditions VDD, VDDO (measured to VSS) . . . . . . . . . . . . . . . . . . . . . . 4.75 to 5.25V Operating Temperature (Ambient). . . . . . . . . . . . . . . . . . . . . . 0 to 70°C DC Characteristics TTL-Compatible Inputs 101 Option - (AD0-AD3, STROBE), 301 Option - (DATCLK, DATA, HOLD, BLANK, EXTFBK) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Capacitance SYMBOL Vih Vil Iih Iil Cin CONDITIONS Vih =VDD Vil =0.0 MIN 2.0 VSS-0.5 - MAX VDD+0.5 0.8 10 150 8 UNITS V V uA uA pF XTAL1 Input PARAMETER Input High Voltage Input Low Voltage SYMBOL Vxh Vxl CONDITIONS MIN 3.75 VSS-0.5 MAX VDD+0.5 1.25 UNITS V SYMBOL CONDITIONS MIN 0.6 MAX - UNITS V MAX 0.4 UNITS V V CLK+, CLK- Outputs PARAMETER Differential Output Voltage LOAD, LD/N2 Outputs PARAMETER Output High Voltage (Ioh=4.0mA) Output Low Voltage (Iol=8.0mA) SYMBOL CONDITIONS 14 MIN 2.4 - ICS1572 AC Characteristics SYMBOL Fvco Fxtal Cpar Fload Txhi Txlo Thigh Jclk Tlock Idd Iddo 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PARAMETER MIN TYP VCO Frequency (see Note 1) 20 Crystal Frequency 5 Crystal Oscillator Loading Capacitance 20 LOAD Frequency XTAL1 High Time (when driven externally) 8 XTAL1 Low TIme (when driven externally) 8 Differential Clock Output Duty Cycle 45 (see Note 2) Differential Clock Output Cumulative <0.06 Jitter (see Note 3) PLL Acquire Time (to within 1%) 500 VDD Supply Current 15 VDDO Supply Current (excluding CLK+/20 termination) DIGITAL INPUTS - ICS1572-101 Address Setup Time 10 Address Hold Time 10 Data Setup Time 10 Data Hold Time 10 20 STROBE Pulse Width (Thi or Tlo) DIGITAL OUTPUTS - ICS1572-301 DATA/HOLD~Setup Time 10 DATA/HOLD~Hold Time 10 20 DATCLK Pulse Width (Thi or Tlo) PIPELINE DELAY RESET Reset Activation Time Reset Duration 4*Tload Restart Delay Restart Matching -1*Tclk DIGITAL OUTPUTS CLK+/CLK- Clock Rate LOAD To LD/N2 Skew (Shift Clock Mode) -2 0 MAX 160 20 80 55 UNITS MHz MHz pF MHz ns ns % pixel t.b.d. t.b.d. µs mA mA ns ns ns ns ns ns ns ns 2*Tclk 2*Tload +1.5*Tclk ns ns ns ns 180 +2 MHz ns Note 1: Use of the post-divider is required for frequencies lower than 20 MHz on CLK+ & CLK- outputs. Use of the post-divider is recommended for output frequencies lower than 65 MHz. Note 2: Using load circuit of Figure 6. Duty cycle measured at zero crossings of difference voltage between CLK+ and CLK-. Note 3: Cumulative jitter is defined as the maximum error (in the time domain) of any CLK edge, at any point in time, compared with the equivalent edge generated by an ideal frequency source. ICS laboratory testing indicates that the typical value shown above can be treated as a maximum jitter specification in virtually all applications. Jitter performance can depend somewhat on circuit board layout, decoupling, and register programming. 15 ICS1572 NOTES 16 ICS1572 Application Information Output Circuit Considerations for the ICS1572 Stripline is the other form a PCB transmission line can take. A buried trace between ground planes (or between a power plane and a ground plane) is common in multi-layer boards. Attempting to create a workstation design without the use of multi-layer boards would be adventurous to say the least, the issue would more likely be whether to place the interconnect on the surface or between layers. The between layer approach would work better from an EMI standpoint, but would be more difficult to lay out. A stripline is shown below: Output Circuitry The dot clock signals CLK and CLK- are typically the highest frequency signals present in the workstation. To minimize problems with EMI, crosstalk, and capacitive loading extra care should be taken in laying out this area of the PC board. The ICS1572 is packaged in a 0.3”-wide 20-pin SOIC package. This permits the clock generator, crystal, and related components to be laid out in an area the size of a postage stamp. The ICS1572 should be placed as close as possible to the RAMDAC. The CLK and CLK- pins are running at VHF frequencies; one should minimize the length of PCB trace connecting them to the RAMDAC so that they don’t become radiators of RF energy. At the frequencies that the ICS1572 is capable of, PC board traces may be long enough to be a significant portion of a wavelength of that frequency. PC traces for CLK and CLKshould be treated as transmission lines, not just interconnecting wires. These lines can take two forms: microstrip and stripline. A microstrip line is shown below: Using 1oz. copper (0.0015” thick) and 0.040” thickness G10, a 0.010” trace will exhibit a characteristic impedance of 75Ω in a stripline configuration. Typically, RAMDACS require a Vih of VAA-1.0 Volts as a guaranteed logical “1” and a Vil of VAA-1.6 as a guaranteed logical “0.” Worst case input capacitance is 10 pF. Output circuitry for the ICS1572 is shown in the following diagram. It consists of a 4/1 current mirror, and two open drain output FETs along with inverting buffers to alternately enable each current-sinking driver. Both CLK and CLK- outputs are connected to the respective CLOCK and CLOCK* inputs of the RAMDAC with transmission lines and terminated in their equivalent impedances by the Thevenin equivalent impedances of R1 and R2 or R1’ and R2’. Essentially, the microstrip is a copper trace on a PCB over a ground plane. Typically, the dielectric is G10 glass epoxy. It differs from a standard PCB trace in that its width is calculated to have a characteristic impedance. To calculate the characteristic impedance of a microstrip line one must know the width and thickness of the trace, and the thickness and dielectric constant of the dielectric. For G10 glass epoxy, the dielectric constant (er) is about 5. Propagation delay is strictly a function of dielectric constant. For G10 propagation, delay is calculated to be 1.77 ns/ft. 17 ICS1572 Application Note Cb is shown as multiple capacitors. Typically, a 22 µF tantalum should be used with separate .1 µF and 220pf capacitors placed as close to the pins as possible. This provides low series inductance capacitors right at the source of high frequency energy. Rd is used to isolate the circuitry from external sources of noise. Five to ten ohms should be adequate. The ICS1572 is incapable of sourcing current, so Vih must be set by the ratios of these resistors for each of these lines. R1 and R2 are electrically in parallel from an AC standpoint because Vdd is bypassed to ground through bypass-capacitor network Cb. If we picked a target impedance of 75Ω for our transmission line impedance, a value of 91Ω for R1 and R1’ and a value of 430Ω for R2 and R2’ would yield a Thevinin equivalent characteristic impedance of 75.1W and a Vih value of VAA-.873 Volts, a margin of 0.127Volts. This may be adequate; however, at higher frequencies one must contend with the 10 pF input capacitance of the RAMDAC. Values of 82Ω for R1 and R1’ and 820Ω for R2 and R2’ would give us a characteristic impedance of 74.5Ω and a Vih value of VAA-.45. With a .55 Volt margin on Vih, this voltage level might be safer. To set a value for Vil, we must determine a value for Iprg that will cause the output FET’s to sink an appropriate current. We desire Vil to be VAA-1.6 or greater. VAA-2 would seem to be a safe value. Setting up a sink current of 25 milliamperes would guarantee this through our 82Ω pull-up resistors. As this is controlled by a 4/1 current mirror, 7 mA into Iprg should set this current properly. A 510Ω resistor from Vdd to Iprg should work fine. ICS1572 Output Circuitry Resistors Rt and Rt’ are shown as series terminating resistors at the ICS1572 end of the transmission lines. These are not required for operation, but may be useful for meeting EMI requirements. Their intent is to interact with the input capacitance of the RAMDAC and the distributed capacitance of the transmission line to soften up rise and fall times and consequently cut some of the high-order harmonic content that is more likely to radiate RF energy. In actual usage they would most likely be 10 to 20Ω resistors or possibly ferrite beads. Great care must be used when evaluating high frequency circuits to achieve meaningful results. The 10 pf input capacitance and long ground lead of an ordinary scope probe will make any measurements made with it meaningless. A low capacitance FET probe with a ground connection directly connected to the shield at the tip will be required. A 1GHz bandwidth scope will be barely adequate, try to find a faster unit. 18 ICS1572 SOIC Packages (wide body) LEAD COUNT DIMENSION L 14L 0.354 16L 0.404 18L 0.454 20L 0.504 24L 0.604 28L 0.704 32L 0.804 Ordering Information ICS1572M-101 or ICS1572M-301 Example: ICS XXXX M -XXX Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type M=SOIC Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV=Standard Device; GSP=Genlock Device 19