March 1997 ML6510* Series Programmable Adaptive Clock Manager (PACMan™) GENERAL DESCRIPTION FEATURES The ML6510 (Super PACMan™) is a Programmable Adaptive Clock Manager which offers an ideal solution for managing high speed synchronous clock distribution in next generation, high speed personal computer and workstation system designs. It provides eight channels of deskew buffers that adaptively compensate for clock skew using only a single trace. The input clock can be either TTL or PECL, selected by a bit in the control register. Frequency multiplication or division is possible using the M&N divider ratio, within the maximum frequency limit. 0.5X, 1X, 2X and 4X clocks can be easily realized. The ML6510 is implemented using a low jitter PLL with on-chip loop filter. The ML6510 deskew buffers adaptively compensate for clock skew on PC boards. An internal skew sense circuit is used to sense the skew caused by the PCB trace and load delays. The sensing is done by detecting a reflection from the load and the skew is corrected adaptively via a unique phase control delay circuit to provide low load-to-load skew, at the end of the PCB traces. Additionally, the ML6510 supports PECL reference clock outputs for use in the generation of clock trees with minimal part-to-part skew. The chip configuration can be programmed to generate the desired output frequency using the internal ROM or an external serial EEPROM or a standard two-wire serial microprocessor interface. ■ Input clocks can be either TTL or PECL with low input to output clock phase error ■ 8 independent, automatically deskewed clock outputs with up to 5ns of on-board deskew range (10ns round trip) Controlled edge rate TTL-compatible CMOS clock outputs capable of driving 40Ω PCB traces ■ ■ ■ ■ ■ ■ ■ ■ 10 to 80MHz (6510-80) or 10 to 130MHz (6510-130) input and output clock frequency range Less than 500ps skew between inputs at the device loads Small-swing reference clock outputs for minimizing part-to-part skew Frequency multiplication or division is possible using the M&N divider ratio Lock output indicates PLL and deskew buffer lock Test mode operation allows PLL and deskew buffer bypass for board debug Supports industry standard processors like Pentium,™ Mips, SPARC,™ PowerPC,™ Alpha,™ etc. *Some Packages Are Obsolete SYSTEM BLOCK DIAGRAM LOCAL BUS CPU CLK CACHE CONTROLLER CACHE RAM MEMORY BUS CONTROLLER CLOCK SUBSYSTEM CLOCK IN ML6510 • 8 • • CLOCK OUT TO COMPONENTS MEMORY BUS 1 ML6510 BLOCK DIAGRAM CLKINL CLKINH DESKEW BUFFER 0 M PLL PHASE DETECTOR SENSE CIRCUIT VOLTAGE CONTROLLED DELAY DRIVE CIRCUIT FB0 (from remote chip) CLK0 (to remote chip) R MAX DELAY ZERO DELAY N FB1 DESKEW BUFFER 1 R0MMSB MCLK MDOUT ZERO DELAY MDIN CLK1 MAXIMUM DELAY MAX DELAY LOCK PROGRAMMING AND CONTROL LOGIC RESET FB7 DESKEW BUFFER 7 CLK7 REF CLOCK RCLKH RCLKL FB3 AGND1 AVCC1 FB4 DGND4 CLK4 DVCC45 CLK5 DGND5 6 5 4 3 2 1 44 43 42 41 CLK3 7 40 39 DVCC23 8 38 DGND6 CLK2 9 37 CLK6 DGND2 10 36 DVCC67 FB2 11 35 CLK7 FB1 12 34 DGND7 DGND1 13 33 FB7 CLK1 14 32 ROMMSB DVCC01 15 31 AVCC2 CLK0 16 30 AGND2 23 24 25 RESET LOCK AGND3 AVCC3 26 27 29 28 CLKINH 22 RCLKL 21 RCLKH 19 20 MCLK FB0 17 18 MDOUT ML6510 44-LEAD PLCC (Q44) TOP VIEW MDIN DGND0 2 FB5 DGND3 PIN CONNECTION FB6 CLKINL ML6510 PIN DESCRIPTION PIN NUMBER NAME DESCRIPTION 32 ROMMSB 20 MDOUT Programming pin. See section on Programming the ML6510. 19 MDIN Programming pin. See section on Programming the ML6510. 21 MCLK Programming pin. See section on Programming the ML6510. 22 RESET Reset all internal circuits. Asserted polarity is low. 23 LOCK Indicates when the PLL and deskew buffers have locked. Asserted polarity is high. 28 29 CLKINH CLKINL Input clock pins. For TTL clock reference use CLKINH pin shorted to the CLKINL pin. For PECL clock reference drive pins differentially. Input clock type is selected by the CS bit in the shift register. 16,14,9,7, 44, 42, 37, 35 CLK[0–7] 18,12,11,5, 2, 40, 39, 33 FB[0–7] 3,31 25 AVCC[1–3] Analog circuitry supply pins, separated from noisy digital supply pins to provide isolation. All supplies are nominally +5V. 4, 30, 24 AGND[1–3] Analog circuitry ground pins 15 DVCC01 Digital supply pin for CLK0 and CLK1 output buffers. Nominally +5V. 8 DVCC23 Digital supply pin for CLK2 and CLK3 output buffers. Nominally +5V. 43 DVCC45 Digital supply pin for CLK4 and CLK5 output buffers. Nominally +5V. 36 DVCC67 Digital supply pin for CLK6 and CLK7 output buffers. Nominally +5V. 17, 13, 10, 6, 1, 41, 38, 34 DGND[0–7] 26 27 RCLKL RCLKH MSB of the internal ROM address. Tie to GND if not used. See section on Programming the ML6510. Clock outputs Clock feedback inputs for the deskew buffers Digital ground pins for CLK [0–7] output buffers. Each clock output buffer has its own ground pin to avoid crosstalk and ground bounce problems. Differential reference clock output used to minimize part-to-part skew when building clock trees with other PACMan integrated circuits. 3 ML6510 ABSOLUTE MAXIMUM RATINGS VCC Supply Voltage Range ............................ –0.3V to 6V Input Voltage Range .................................... –0.3V to VCC Output Current CLK[0–7] ........................................................ 70mA All other outputs ............................................. 10mA Junction Temperature .............................................. 150°C Storage Temperature ................................ –65°C to 150°C Thermal Resistance (θJA) ....................................... 54°C/W ELECTRICAL CHARACTERISTICS The following specifications apply over the recommended operating conditions of DVCC = AVCC = 5V ± 5% and ambient temperature between 0°C and 70°C. Loading conditions are specified individually (Note 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT SUPPLY DVCCXX Supply Current for each pair of clock outputs µA fCLKX = 0 50 CL= 20pF, ZO = 50Ω fOUT = 80MHz 40 60 mA IAVCC1 Static supply current, AVCC1 pin 100 120 mA IAVCC2 Static supply current, AVCC2 pin 35 40 mA IAVCC3 Static supply current, AVCC3 pin 1 2 mA LOW FREQUENCY INPUTS AND OUTPUTS (ROMMSB, MDOUT, MDIN, MCLK, RESET, LOCK) VIH High level input voltage DVCC – 0.5 VIL Low level input voltage VOH High level output voltage, MCLK and MDIN IOH = –100 µA VOL Low level output voltage, MCLK and MDIN IOL = +200 µA VOH High level output voltage, LOCK output IOH = –100 µA IOH = –10 µA VOL Low level output voltage, LOCK output IOL = +1 mA IIN Static input current CIN Input capacitance V DGND + 0.5 DVCC – 0.5 V V DGND + 0.5 2.4 DVCC – 0.5 V V V 0.4 V 10 µA 5 pF HIGH FREQUENCY INPUTS AND OUTPUTS (CLKINH, CLKINL, FB[0-7], CLK[0-7]) VIH High level input voltage CS = 0 (TTL Input Clock) CS = 1 (PECL Input Clock) VIL Low level input voltage AVCC – 1.165 CS = 0 (TTL Input Clock) V AVCC – 0.88 V 0.8 V CS = 1 (PECL Input Clock) AVCC – 1.810 AVCC – 1.475 V 2.0 AVCC – 0.4 V 100 µA VICM Common mode input voltage range for PECL reference clocks CS = 1 (PECL Input Clock) IIH High level input current VIH = 2.4V IIL Low level input current VIL = 0.4V VOH High level output voltage IOH = –60mA VOL Low level output voltage IOL = +60mA 4 2.0 –400 µA 2.4 V 0.4 V ML6510 ELECTRICAL CHARACTERISTICS (Continued) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT AC CHARACTERISTICS rise time, fall time and duty cycle are measured for a generic load; (see Load Conditions section). tR Rise time, LOAD [0-7] output 0.8 → 2.0V, 80MHz 150 1500 ps tF Fall time, LOAD [0-7] output 2.0 → 0.8V, 80MHz 150 1500 ps fIN Input frequency, CLKIN pin 10 80 MHz fOUT Output frequency , CLK [0-7] output ML6510-80 10 80 MHz ML6510-130 (Note 2) 10 130 MHz 80 160 MHz 40 60 % fVCO PLL VCO operating frequency DC Output duty cycle Measured at device load, at 1.5V tJITTER Output jitter Cycle-to-cycle 75 ps Peak-to-peak 150 ps After programming is complete 11 ms tLOCK PLL and deskew lock time SKEW CHARACTERISTICS All skew measurements are made at the load, at 1.5V threshold each output load can vary independently within the specified range for a generic load (see Load Conditions section). tSKEWR Output to output rising edge skew, all clocks tSKEWF Output to output falling edge skew Output clock frequency ≥ 50MHz tSKEWIO CLKIN input to any LOAD [0-7] output rising edge skew N=M=0 600 ps N ≥ 2, M ≥ 2 1.25 ns tRANGE Round trip delay CLKX to FBX pin; output CLK period = tCLK Output frequency < 50MHz Output frequency ≥ 50MHz tSKEWB Output-to-output rising edge skew, between matched loads Providing first (see LOAD conditions) order matching order matching between outputs 0 0 500 ps 1.5 ns 10 tCLK/2 250 ns ps PART-TO-PART SKEW CHARACTERISTICS Skew measured at the loads, at 1.5V threshold. Reference clock output pins drive clock input pins of another ML6510. tPP1 Total load-to-load skew between multiple chips interfaced with reference clock pins. Slave chip CS = 1, CM = 1 and N = 0, M = 0; RCLK outputs to CLKIN inputs distance less than 2" 1 ns tPP2 Total load-to-load skew between multiple chips interfaced with reference clock pins. Slave chip CS = 1, CM = 1 and N ≥ 2, M ≥ 2; RCLK outputs to CLKIN inputs distance less than 2" 1 ns PROGRAMMING TIMING CHARACTERISTICS tRESET RESET assertion pulse width tA1 50 ns AUX mode MCLK high time 2000 ns tA2 AUX mode MCLK low time 2000 ns tA3 AUX mode MDOUT data hold time 10 ns tA4 AUX mode MDOUT data setup time 10 ns tA5 AUX mode MCLK period 5000 ns 5 ML6510 ELECTRICAL CHARACTERISTICS (Continued) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT PROGRAMMING TIMING CHARACTERISTICS (continued) tM1 MAIN mode MCLK high time 900 ns tM2 MAIN mode MCLK low time 900 ns tM3 MAIN mode MCLK period 1800 ns tM4 MAIN mode MCLK to MDOUT valid (EEPROM read time) Note 1: Note 2: 900 ns Limits are guaranteed by 100% testing, sampling or correlation with worst case test conditions. If ML6510-130 is used in a master-slave mode, the maximum operating frequency is 120MHz. ML6510 configured with bit CM = 0: PECL INPUT CLOCKS OR AVCC – 0.4V TTL INPUT CLOCK tSKEWIO CLKINH CLKINL LOAD [0-7] 1st Order Match tSKEWB OR tSKEWF tSKEWR VICM 2.0 V LOAD [0-7] with no 1st order match Note: 6 All skew is measured at the device load input pin, NOT at the ML6510 clock output pin. Skew is always a positive number, regardless of which edge is leading and which is trailing. ML6510 AC/SKEW CHARACTERISTICS LOAD CONDITIONS ML6510-80 GENERIC LOAD FBX R1 ML6510-130 GENERIC LOAD FBX PCB trace impedance Z0 = 50Ω LOAD R2 Lumped CL ≤ 20pF CLKX PCB trace impedance Z0 = 50Ω LOAD CLKX Lumped CL ≤ 20pF R3 One way trip delay < tRANGE/2 One way trip delay < tRANGE/2 FBX R1 PCB trace impedance Z0 = 50Ω CLKX FBX LOAD Lumped CLX ≤ 20pF R2 Length LX ML6510-80 FIRST-ORDER MATCHED LOADS R1 PCB trace impedance Z0 = 50Ω CLKY R3 ML6510-130 FIRST-ORDER MATCHED LOADS |CLX – CLY| < 5pF |LX – LY| < 4" ZOX = ZOY FBY PCB trace impedance Z0 = 50Ω CLKX Length LX |CLX – CLY| < 5pF |LX – LY| < 4" ZOX = ZOY FBY LOAD Lumped CLY ≤ 20pF R2 PCB trace impedance Z0 = 50Ω CLKY Length LY LOAD Lumped CLX ≤ 20pF R3 LOAD Lumped CLY ≤ 20pF Length LY One way trip delay < tRANGE/2 One way trip delay < tRANGE/2 ML6510 RCLKH RCLKL LOAD[0-7] tSKEWR (or tSKEWB) LOAD[0-7] DISTANCE <2" CLKINH CLKINL ML6510 SLAVE CHIP (CM=1, CS=1) tSKEWR (or tSKEWB) LOAD[8-15] LOAD[8-15] tpp1 or tpp2 7 ML6510 FUNCTIONAL DESCRIPTION Micro Linear’s ML6510 is the first clock chip to use a feedback mechanism to adaptively (on a real time basis), eliminate clock skew in high speed personal computer and workstation system designs. Figure 1 shows a basic configuration of the ML6510 in a system. The skew problem results due to the delaying of clock signals in the system, as shown in Figure 2. Clock skew results from variation in factors like trace length, PCB trace characteristics, load capacitance, parasitic capacitance, temperature and supply variations, etc. Figure 2 shows a representation of the clock skew problem from a timing perspective. It shows a worst case example where the clock signal is delayed so much that its rising edge completely misses the data it is intended to strobe. Using a clock deskew mechanism, this problem can be eliminated and the strobe with the appropriate setup and hold times with respect to the data bus can be generated. The ML6510 has eight deskew buffers, each with its own independent the reflection and error correction circuit. The deskew buffer eliminates skew by using the reflection from a remote chip to measure the clock error and then corrects it by generating the appropriate skew to the clock output to compensate. Eight individually deskewed copies of the clock are provided by the ML6510. CLOCK GENERATOR CPU DATA REMOTE CHIP The deskew buffers compensate internally for board-level skew caused by the PCB trace length variations and device load variations. This is accomplished by sensing the round trip delay via a reflected signal, and then delaying or advancing the clock edge so that all 8 output clocks arrive at their loads in phase. Each of the eight clock lines can have any length PCB trace (up to 5ns each way or 1/4th of the output clock period, whichever is smaller) and the device loads can vary from line to line. The ML6510 will automatically compensate for these variations, keeping the device load clocks in phase. Although ML6510 will compensate for skew caused by loading, excessive capacitive loading can cause rise/fall time degradation at the load. Cascading one ML6510 to another ML6510 should be done using the PECL reference clock outputs, to minimize part-to-part skew. CLOCK REGENERATION The programmable adaptive clock deskew can function in a clock regeneration mode to assist in building clock trees or to expand the number of deskewed clock lines. In this mode, it has the ability to do clock multiplication or division as well, while maintaining low skew between WRITE SIGNAL CLOCK AT REMOTE CHIP DATA AT REMOTE CHIP CLOCK #0 FEEDBACK #0 DATA WRITE SIGNAL CLOCK IN CLOCK #1 MICRO LINEAR FEEDBACK #1 ML6510 CLOCK CHIP CLOCK #7 CLOCK AT REMOTE CHIP tS DATA AT REMOTE CHIP tH DATA FEEDBACK #7 Figure 2. The Skew Problem. Figure 1. Basic System Configuration Using the ML6510. 8 ML6510 ECL INPUT BUFFER CLKINH 1 CLKINL ÷(M + 1) [÷1 TO 64] PHASE DETECTOR LOOP FILTER VCO 80-160 MHz 0 ÷2R TTL TO ECL CS BIT RCLKH RCLKL MAXIMUM DELAY 1 ÷(N + 1) [÷1 TO ÷128] 0 CM BIT 0 1 TEST SYS_CLK TO DESKEW BUFFERS Figure 3. ML6510 Clock Generation Block Diagram. input clock and output clocks. It can thus generate a 2x or 4x or 0.5x frequency multiplication or division from input to output (e.g. 33 MHz input, 66 MHz output or 66 MHz input, 33 MHz output, etc.). It also can generate a 1x frequency output. The VCO frequency is defined by: ( ) N + 1 × 2R fVCO = fREF × M + 1 ( ) and the output frequency is still given by: fOUT = fVCO/2R Example: Generating a 2x clock input frequency = 33 MHz Set R = 01 (output range 40 – 80 MHz), N = 5 (0000101), M = 2 (000010), M/S = 0 ( ) N + 1 × 2R 1 = 33MHz × 6 × 2 = 132MHz fVCO = fREF × M + 1 3 ( ) fOUT = fVCO/2R = 132 MHz/21 = 66 MHz Example: Generating a 1x clock Input frequency = 66 MHz R1 R0 INPUT/OUTPUT RANGE 0 0 80-130 MHz 0 1 40–80 MHz 1 0 20–40 MHz 1 1 10–20 MHz Note: R implies R1, R0; for -80 version, Not valid: Defaults to R = 01 The VCO still must remain in the range 80–160 MHz, and the minimum phase detector input frequency is 625kHz = (80 MHz/128). Thus the product of (N + 1) and 2R should be limited to 128: (N + 1) x 2R ≤ 128 to make sure that the phase detector inputs remain above the minimum frequency. Set R = 01 (output range 40–80 MHz), set M = 0 (000000), N = 0 (0000000), M/S = 0 1 fVCO = 66MHz × 1× 2 = 132MHz 1 fOUT = fVCO/2R = 132 MHz/21 = 66 MHz For doing frequency multiplication and division, keep M ≥ 2 and N ≥ 2 for the lowest skew between input clock and output clock. Several configurations for doing frequency multiplication and division are included in the 8 configurations stored in the on-chip ROM (see PROGRAMMING the ML6510). 9 ML6510 ADAPTIVE DESKEW BUFFERS LOAD CONDITIONS Each copy of the clock is driven by an adaptive deskew buffer. The deskew buffer compensates for skew time automatically in accordance to the flight time delay it senses from the reflection on the transmission line. The ML6510 has been designed to drive the wide range of load conditions that are encountered in a high frequency system. The eight output clock loads can each vary within a range of trace length and lumped capacitive load, and the ML6510 will maintain the low skew characteristics specified in Electrical Characteristics. The clock skew can be further minimized by providing some first-order matching between any two loads that require particularly wellmatched clocks. Figure 4 shows the simplified functional block diagram of the deskew circuit. The phase of the sense signal and the driver signal is presented to a three-input phase comparator and compared with the reference signal. The phase comparator then controls the voltage controlled delay in the output drive line to match the delay of the fixed reference delay line. Therefore, the sum of the delay of the driver circuit, PCB trace delay, rise time delay at the load and the adjustable delay will always equal the fixed maximum delay. The sense circuit has an internal level detect such that any skew caused by loading is also accounted for. Since the delay of the circuit is matched for the entire loop, the phase of all the drivers are in close alignment at the inputs of the load. CLOCK IN FIXED MAX DELAY PHASE DETECTOR SENSE VOLTAGE CONTROLLED DELAY DRIVE LOAD Figure 4. Deskew Circuit Block Diagram. 10 The ML6510-80 produces a 5V swing at the load and requires a single external termination resistor for each output. The ML6510-130 produces a 3V swing at the load and requires two external termination resistors for each output. The FB input pin is connected to the other side of the termination resistor R1 or R2, with a short connection. Termination resistor valves should be chosen as follows: R1 = Z0 R2 = 1.5 × Z0 TRACE IMPEDANCE Z0 40Ω 50Ω 63Ω R3 = 3 × Z0 R1 RESISTOR VALUES R2 R3 40 50 63 60 75 95 120 150 189 ML6510 ML6510-80 GENERIC LOAD FBX R1 PCB trace impedance Z0 = 40Ω to 65Ω LOAD CLKX ML6510-130 GENERIC LOAD FBX R2 Lumped CL ≤ 20pF PCB trace impedance Z0 = 40Ω to 65Ω LOAD CLKX Lumped CL ≤ 20pF R3 One way trip delay < tRANGE/2 One way trip delay < tRANGE/2 FBX R1 PCB trace impedance Z0 = 40Ω to 65Ω CLKX FBX LOAD Lumped CLX ≤ 20pF R2 CLKX Length LX ML6510-80 FIRST-ORDER MATCHED LOADS |CLX – CLY| < 5pF |LX – LY| < 4" ZOX = ZOY FBY R1 PCB trace impedance Z0 = 40Ω to 65Ω CLKY PCB trace impedance Z0 = 40Ω to 65Ω R3 ML6510-130 FIRST-ORDER MATCHED LOADS Length LX |CLX – CLY| < 5pF |LX – LY| < 4" ZOX = ZOY FBY LOAD Lumped CLY ≤ 20pF R2 PCB trace impedance Z0 = 40Ω to 65Ω CLKY Length LY LOAD Lumped CLX ≤ 20pF R3 LOAD Lumped CLY ≤ 20pF Length LY One way trip delay < tRANGE/2 One way trip delay < tRANGE/2 EXTERNAL INPUT CLOCKS The external input clock to the ML6510 can be either a differential Pseudo-ECL clock or a single-ended TTL clock. This is selected using the CS bit in the serial shift register. For the single-ended TTL clock tie the CLKINH and CLKINL pins together. The ML6510 ensures that there is a welldefined phase difference between the input and output clocks. RESET AND LOCK tRESET RESET LOCK tLOCK PROGRAM IN THE CONFIGURATION When RESET is de-asserted, the internal programming logic will become active, loading in the configuration bits (see Programming the ML6510). Once the configuration is loaded, the PLL will lock onto the reference signal, and then the deskew blocks will adapt to the load conditions. When all eight output clocks are stable and deskewed, LOCK will be asserted. The asserted polarity of lock is high. Thus, LOCK can be used to indicate that the system is ready, or it can be used to drive the RESET input of another PACMan in a clock tree. 5V CHIP VCC 0 tLOCK PROGRAM IN THE CONFIGURATION RESET may be reasserted at any time to reset the chip operations. Following a RESET assertion of valid pulse width (see Programming Electrical Characteristics), the ML6510 must again be loaded with a configuration, then it will re-lock and reassert lock when all eight clock outputs are stable and deskewed. 11 ML6510 PROGRAMMING THE ML6510 2. AUX Mode When MDIN is tied to VCC, programming the ML6510 will occur via the AUX Mode. This mode shifts the configuration bits into the shift register directly from the MDOUT pin. The first 18 (ML6510-80) or 19 (ML6510130) clock rising edges provided externally on the MCLK pin after RESET is deasserted will be used to load the shift register data, which should be provided on the MDOUT pin. See figure 6. The configuration of the ML6510 is programmed by loading 18 (ML6510-80) or 19 (ML6510-130) bits into the configuration shift register. To load these bits, the user has 3 options: MAIN, AUX or ROM modes. Which mode is used is determined by the logic level on the MDIN pin when RESET is deasserted. If MDIN is tied high, the ML6510 will assume AUX mode; if its tied low, ROM mode. If MDIN is high-impedance (i.e. tied to the input of an EEPROM), it will assume MAIN mode. µ PROCESSOR ML6510 1. MAIN Mode ROMMSB In this mode, the ML6510 will read the configuration bits from an external serial EEPROM, such as the 93C46, using the industry standard 3-wire serial I/O protocol. The serial EEPROM should be a 1K organized in 64 x 16 bits and the PACMan will read the configuration bits out of the two least significant 16-bit words. To use this mode, simply connect the EEPROM serial data input pin to MDIN (ML6510 pin 19), the EEPROM serial data output pin to MDOUT (ML6510 pin 20), and the EEPROM serial data clock pin to MCLK (ML6510 pin 21) and CS pin for the EEPROM should be tied to the RESET signal. After power up, when RESET is deasserted, the ML6510 will automatically generate the address and clock to read out the configuration bits. Refer MAIN Mode waveform in Figure 5. MDIN DATA CLOCK CS 3. ROM Mode When MDIN is tied to GND, programming the ML6510 will occur via the ROM Mode. This mode reads the configuration bits directly from an on chip ROM. The selection of one of the eight preset configuration codes is accomplished by means of the pins ROMMSB, MCLK and MDOUT as shown in Tables 1 and 2. The TEST mode configuration (code 7) is enabled when the TEST bit is set. In this mode the PLL is bypassed for low frequency testing. Codes 0-2 are used when the ML6510 clock inputs are driven from another PACMan’s reference clock outputs. Code 3 is used when zero phase error is desired between input and load clocks. DATA IN MCLK OPCODES ADDRESS MDIN DATA DATA OUT MDOUT AUX Mode Configuration. ROMMSB CLK MCLK VCC ML6510 1K SERIAL EEPROM (64 X 16 BIT) RESET CLOCK MDOUT RESET ML6510 ROM ADDRESS BITS ROMMSB MAIN Mode Configuration. ROM 8 X 19 BIT MCLK MDOUT TO SHIFT REGISTER SERIAL DATA IN MDIN tM1 MCLK (Driven by ML6510) MDIN (Driven by ML6510) MDOUT (Driven by EEPROM) 01 SB 1 tM3 tM2 02 OP1 1 03 OP0 0 04 A5 0 05 A4 0 06 A3 0 ROM Mode Configuration. 07 A2 0 08 A1 0 09 10 11 12 13 ••• 25 26 27 (28) A0 0 D15 D14 D13 ••• D0 D15 D14 (D13) tM4 16 bits data at adddress 0 Figure 5. MAIN Mode Waveforms. 12 2 bits at address 1 (3 bits for ML6510-130) ML6510 TABLE 1: ML6510-80 ROM CODES SELECTION BITS CODE 0 1 2 3 4 5 6 7 DESCRIPTION ROMMSB PECL Input Clock, 1x mode 0 PECL Input Clock, 0.5x mode 0 PECL Input Clock, 2x mode 0 PECL Input Clock, 1x mode 0 TTL Input Clock, 1x mode 1 TTL Input Clock, 0.5x mode 1 TTL Input Clock, 2x mode 1 TEST mode, TTL Input clock 1 MCLK MDOUT 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 INPUT FREQ (MHz) 40-80 40-80 20-40 40-80 40-80 40-80 20-40 0-50 OUTPUT FREQ (MHz) 40-80 20-40 40-80 40-80 40-80 20-40 40-80 0-50 CONFIGURATION CODE CS 1 1 1 1 0 0 0 0 CM R1, R0 1 01 1 10 1 01 0 01 0 01 0 10 0 01 — — M 0 5 2 0 0 5 2 — N 0 2 5 0 0 2 5 — TEST 0 0 0 0 0 0 0 1 TABLE 2: ML6510-130 ROM CODES SELECTION BITS CODE 0 1 2 3 4 5 6 7 DESCRIPTION ROMMSB PECL Input Clock, 1x mode 0 PECL Input Clock, 0.5x mode 0 PECL Input Clock, 2x mode 0 PECL Input Clock, 1x mode 0 TTL Input Clock, 1x mode 1 TTL Input Clock, 0.5x mode 1 TTL Input Clock, 2x mode 1 TEST mode, TTL Input clock 1 INPUT FREQ MCLK MDOUT (MHz) 0 0 80-130 0 1 80-160 1 0 40-65 1 1 80-130 0 0 80-130 0 1 80-130 1 0 40-65 1 1 0-50 tA2 MCLK (Input to ML6510) MDOUT (Input to ML6510) tA1 tA3 CONFIGURATION CODE CM R1, R0 1 00 1 01 1 00 0 00 0 00 0 01 0 00 — — M 0 5 2 0 0 5 2 — N 0 2 5 0 0 2 5 — DDSK 0 0 0 0 0 0 0 — TEST 0 0 0 0 0 0 0 1 tA5 01 M5 OUTPUT FREQ (MHz) CS 80-130 1 40-80 1 80-130 1 80-130 1 80-130 0 40-65 0 80-130 0 0-50 0 02 M4 18 N0 tA4 Figure 6. AUX Mode Waveform. 13 ML6510 REGISTER DEFINITIONS REGISTER SIZE FUNCTION N 7 bit This register is used to define the ratio for the desired frequency of the primary clock. R 2 bit This register defines the frequency of the primary clocks, CLK [0-7]. CM 1 bit Set CM = 1 when the PECL input reference clock is from another 6510 reference clock output. Set CM = 0 if the clock reference is TTL or PECL from an external source and minimum phase error between input and output is desired. CS 1 bit CS = 0 selects TTL input clock, CS = 1 selects PECL input clock. TEST 1 bit When set to 1, the PLL is bypassed for low frequency testing. M 6 bit This register is used to define the ratio for the desired frequency of the primary clock. DDSK 1 bit When DDSK is set to 1, deskew is disabled. The chip will provide low skew clocks at the chip output pins, but trace length variations will not be compensated. When DDSK is set to 0, normal deskew will provide low skew clocks at the loads. This bit is only for ML6510-130. ML6510-80 SHIFT REGISTER CHAIN N0 SERIAL DATA IN (from EEPROM, or µProcessor, or internal ROM) N1 N2 N3 N4 N5 LSB N6 R0 R1 MSB LSB MSB N6 R0 R1 MSB LSB MSB CM CS TEST M0 M1 M2 M3 M4 LSB M5 MSB ML6510-130 SHIFT REGISTER CHAIN N0 SERIAL DATA IN (from EEPROM, or µProcessor, or internal ROM) 14 LSB N1 N2 N3 N4 N5 DDSK CM CS TEST M0 LSB M1 M2 M3 M4 M5 MSB ML6510 APPLICATIONS ZERO SKEW CLOCK GENERATION BOARD TO BOARD SYNCHRONIZATION The most advantageous feature of using PACMan is its ability to deliver multiple copies of the clock to the load with very low skew. Because of its unique ability in deskewing, trace length and load consideration are no longer critical in board design. Distribution of the synchronous clock could present significant difficulty at high frequency. With the system clock generated by the ML6510, a zero skew clock delivery to a backplane is now possible. By using the ML6510 slave chip or the ML6510 in slave mode at the receiver end, a near zero delay clock link can be accomplished between the mother board and the satellite boards. Because of the unique deskewing scheme, neither the trace length nor the device loads need to be equal. This is true for loads, <20pF. Higher loads can be driven if they are placed close to the clock chip, to guarantee signal integrity. Because the PACMan has frequency doubling capability, a lower frequency signal can be used to route across a back plane. CLOCK DRIVER tO–tS1 tS1 tO–tS2 tS 2 tO–tS3 ML6510 (SLAVE MODE) ML6510 tS3 tS0 ONE DEVICE LOAD tS0 TWO DEVICE LOAD tS0 THREE DEVICE LOAD EXAMPLE CONFIGURATION LOW SKEW CLOCK DISTRIBUTION Clock distribution design is usually not a trivial task, especially when multiple clock chips are needed. By using closely grouped PACMans, 16 or more clock lines can be created with low part-to-part skew. Additional groups of clocks can be clustered and driven from deskewed clock lines, to minimize the number of longdistance clock lines. ML6510 CLK0 CLK1 CLK2 ••• CLK0 CLK1 CLK2 tpp2 tSKEWR (or tSKEWB) ••• ••• ML6510 ML6510 CLK0 CLK1 CLK2 CLK3 Shown in Figure 7 is an example configuration using two ML6510-80 chips in tandem to generate eight 66 MHz clocks and eight 33MHz low-skew clocks from a 66MHz input reference. This requires only the termination resistors. Configurations are loaded from the internal ROM. PCB traces 0 to 15 are each 50Ω impedance and the load capacitances CL0-CL15 are 0 to 20pF each. No trace length matching is required among separate clock outputs. All traces are shown with a series termination at the output. If ML6510-130’s are used in a master slave mode the maximum operating frequency will be 120MHz. TO REMOTE GROUP OF CLUSTERED LOADS LOAD[0-7] LOAD[8-15] 33 MHz tSKEWR (or tSKEWB) 15 ML6510 CLK0 SYSTEM RESET LOW 50 PCB TRACE 0 LOAD0 RESET CL0 FB0 VCC 66 MHz ROMMSB MCLK MDIN MDOUT CLK1 ML6510-80 TTL 1X MODE 50 LOAD1 PCB TRACE 1 66 MHz CL1 FB1 CLKINH 66MHz TTL REFERENCE CLKINL CLK7 50 PCB TRACE 7 LOAD7 66 MHz CL7 FB7 LOCK RCLKH RCLKL 66MHz CLKINH CLKINL CLK0 50 PCB TRACE 8 LOAD8 33 MHz CL8 FB0 RESET ROMMSB ML6510-80 PECL 0.5X MODE CLK1 50 LOAD9 PCB TRACE 9 CL9 FB1 MCLK MDIN VCC MDOUT 50 CLK7 FB7 PCB TRACE 15 LOAD15 33 MHz CL15 LOCK ALL_CLOCK_READY Figure 7. Example use of two ML6510-80 to generate multiple frequency clocks. First ML6510-80 generates eight 66MHz clocks while second ML6510-80 takes 66MHz small-swing reference from the first chip and generates eight 33MHz clocks. 16 33 MHz ML6510 PHYSICAL DIMENSIONS inches (millimeters) Package: Q44 44-Pin PLCC 0.685 - 0.695 (17.40 - 17.65) 0.042 - 0.056 (1.07 - 1.42) 0.650 - 0.656 (16.51 - 16.66) 0.025 - 0.045 (0.63 - 1.14) (RADIUS) 1 PIN 1 ID 0.042 - 0.048 (1.07 - 1.22) 12 34 0.650 - 0.656 0.685 - 0.695 (16.51 - 16.66) (17.40 - 17.65) 0.500 BSC (12.70 BSC) 23 0.009 - 0.011 (0.23 - 0.28) 0.050 BSC (1.27 BSC) 0.026 - 0.032 (0.66 - 0.81) 0.013 - 0.021 (0.33 - 0.53) 18 0.165 - 0.180 (4.06 - 4.57) SEATING PLANE 0.148 - 0.156 (3.76 - 3.96) 0.100 - 0.112 (2.54 - 2.84) 0.590 - 0.630 (14.99 - 16.00) ML6510 ORDERING INFORMATION PART NUMBER TEMPERATURE RANGE PACKAGE ML6510CQ-80 0°C to 70°C 44-pin PLCC (Q44) ML6510CQ-130 0°C to 70°C 44-pin PLCC (Q44) (Obsolete) © Micro Linear 1997 is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application. 18 2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295 DS6510-01