PRELIMINARY Integrated Circuit Systems, Inc. ICS843251-04 FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS843251-04 is a 10Gb/12Gb Ethernet Clock Generator and a member of the HiPerClockS™ HiPerClocks TM family of high perfor mance devices from ICS. The ICS843251-04 can synthesize 10 Gigabit Ethernet and 12 Gigabit Ethernet with a 25MHz crystal. It can also generate SATA and 10Gb Fibre Channel reference clock frequencies with the appropriate choice of crystals. The ICS843251-04 has excellent phase jitter performance and is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. • 1 differential 3.3V LVPECL output ICS • Crystal oscillator interface designed for 18pF parallel resonant crystals • Crystal input frequency range: 19.33MHz - 30MHz • Output frequency range: 145MHz - 187.5MHz • VCO frequency range: 580MHz - 750MHz • RMS phase jitter at 156.25MHz (1.875MHz - 20MHz): 0.39ps (typical) • 3.3V operating supply • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request • Available in both standard and lead-free compliant packages CONFIGURATION TABLE Crystal Frequency (MHz) 25 25MHZ CRYSTAL WITH Inputs Feedback VCO Frequency Divide (MHz) 30 750 25 25 CONFIGURATION TABLE WITH N Output Divide 625 Output Frequency (MHz) 4 187.5 12 Gigabit Ethernet 4 156.25 10 Gigabit Ethernet SELECTABLE CRYSTALS Crystal Frequency (MHz) 20 Feedback Divide 30 21.25 30 Inputs VCO Frequency (MHz) 600 N Output Divide 637.5 Output Frequency (MHz) 4 150 4 159.375 24 25 600 4 150 25.5 25 637.5 4 159.375 30 25 750 4 187.5 BLOCK DIAGRAM XTAL_IN OSC XTAL_OUT Application Application SATA 10 Gigabit Fibre Channel SATA 10 Gigabit Fibre Channel 12 Gigabit Ethernet PIN ASSIGNMENT Phase Detector DIV. N ÷4 VCO 580MHz-750MHz nQ Q VCCA VEE XTAL_OUT XTAL_IN 1 2 3 4 8 7 6 5 VCC Q nQ FREQ_SEL ICS843251-04 0 = ÷25 (default) 1 = ÷30 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View FREQ_SEL Pulldown The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 843251AG-04 www.icst.com/products/hiperclocks.html REV. A SEPTEMBER 12, 2005 1 PRELIMINARY Integrated Circuit Systems, Inc. ICS843251-04 FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name Type 1 VCCA Power 2 3, 4 5 VEE XTAL_OUT, XTAL_IN FREQ_SEL Power 6, 7 nQ, Q Output Differential clock outputs. LVPECL interface levels. 8 VCC Power Core supply pin. Input Input Description Analog supply pin. Negative supply pin. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characterristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLDOWN Input Pulldown Resistor 51 kΩ 843251AG-04 Test Conditions Minimum www.icst.com/products/hiperclocks.html 2 Typical Maximum Units REV. A SEPTEMBER 12, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843251-04 FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 101.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA=0°C TO 70°C Symbol Parameter Minimum Typical Maximum Units VCC Core Supply Voltage Test Conditions 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 ICC Power Supply Current TBD mA ICCA Analog Supply Current TBD mA IEE Power Supply Current TBD mA V TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 3.3V±5%, TA=0°C TO 70°C Symbol Parameter Test Conditions VIH Input High Voltage FREQ_SEL Minimum Typical 2 VIL Input Low Voltage FREQ_SEL IIH Input High Current FREQ_SEL VCC = VIN = 3.465V -0.3 IIL Input Low Current FREQ_SEL VCC = 3.465V, VIN = 0V Maximum Units VCC + 0.3 V 0.8 V 150 µA -5 µA TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA=0°C TO 70°C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions Minimum VCC - 1.4 Typical VCC - 0.9 V VOL Output Low Voltage; NOTE 1 VCC - 2.0 VCC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50Ω to VCC - 2V. 843251AG-04 www.icst.com/products/hiperclocks.html 3 REV. A SEPTEMBER 12, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843251-04 FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Maximum Units 30 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW Mode of Oscillation Typical Fundamental Frequency 19.33 TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±5%, TA=0°C TO 70°C Symbol Parameter fOUT Output Frequency tjit(Ø) tR / tF RMS Phase Jitter (Random); NOTE 1 Output Rise/Fall Time Test Conditions Minimum 156.25MHz @ Integration Range: 1.875MHz - 20MHz 159.375MHz @ Integration Range: 1.875MHz - 20MHz 187.5MHz @ Integration Range: 1.875MHz - 20MHz 20% to 80% odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plots following this section. 843251AG-04 Typical 145 www.icst.com/products/hiperclocks.html 4 Maximum Units 187.5 MHz 0.39 ps TBD ps 0.48 ps 340 ps 50 % REV. A SEPTEMBER 12, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843251-04 FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 2V Phase Noise Plot Qx SCOPE Noise Power V CC LVPECL Phase Noise Mask nQx VEE f1 Offset Frequency f2 -1.3V ± 0.165V RMS Jitter = Area Under the Masked Phase Noise Plot 3.3V OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTER nQ0 80% Q0 80% VSW I N G t PW t odc = Clock Outputs PERIOD t PW 20% 20% tR tF x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 843251AG-04 OUTPUT RISE/FALL TIME www.icst.com/products/hiperclocks.html 5 REV. A SEPTEMBER 12, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843251-04 FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843251-04 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, and VCCA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VCCA pin. The 10Ω resistor can also be replaced by a ferrite bead. 3.3V VCC .01μF 10Ω V CCA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. The ICS843251-04 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 27p Figure 2. CRYSTAL INPUt INTERFACE 843251AG-04 www.icst.com/products/hiperclocks.html 6 REV. A SEPTEMBER 12, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843251-04 FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR TERMINATION FOR 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to 3.3V Zo = 50Ω 125Ω FOUT FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω 1 RTT = Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 3A. LVPECL OUTPUT TERMINATION 843251AG-04 125Ω 84Ω FIGURE 3B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 7 REV. A SEPTEMBER 12, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843251-04 FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 101.7°C/W 90.5°C/W 89.8°C/W TRANSISTOR COUNT The transistor count for ICS843251-04 is: 1891 843251AG-04 www.icst.com/products/hiperclocks.html 8 REV. A SEPTEMBER 12, 2005 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR ICS843251-04 FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR 8 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N A Maximum 8 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 3.10 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 843251AG-04 www.icst.com/products/hiperclocks.html 9 REV. A SEPTEMBER 12, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843251-04 FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS843251AG-04 51A04 8 Lead TSSOP tube 0°C to 70°C ICS843251AG-04T 51A04 8 Lead TSSOP 2500 tape & reel 0°C to 70°C ICS843251AG-04LF 1A04L 8 Lead "Lead-Free" TSSOP tube 0°C to 70°C ICS843251AG-04LFT 1A04L 8 Lead "Lead-Free" TSSOP 2500 tape & reel 0°C to 70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843251AG-04 www.icst.com/products/hiperclocks.html 10 REV. A SEPTEMBER 12, 2005