PRELIMINARY ICS844001-21 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS844001-21 is a a highly versatile, low ICS phase noise LVDS Synthesizer which can generate HiPerClockS™ low jitter reference clocks for a var iety of communications applications and is a member of the HiPerClocksTM family of high performance clock solutions from IDT. The dual crystal interface allows the synthesizer to support up to two communications standards in a given application (i.e. 1GB Ethernet with a 25MHz crystal and 1Gb Fibre Channel using a 25.5625MHz crystal). The rms phase jitter performance is typically less than 1ps, thus making the device acceptable for use in demanding applications such as OC48 SONET and 10Gb Ethernet. The ICS844001-21 is packaged in a small 24-pin TSSOP package. • One differential LVDS output pair and one LVCMOS reference output • Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input • VCO range: 560MHz - 700MHz • Supports the following applications: SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV • RMS phase jitter @ 622.08MHz (12kHz - 20MHz): 0.92ps (typical) • Full 3.3V supply mode • 0°C to 70°C ambient operating temperature • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages BLOCK DIAGRAM 3 N2:N0 PIN ASSIGNMENT SEL0 Pulldown SEL1 Pulldown N XTAL_IN0 OSC 00 11 XTAL_OUT0 XTAL_IN1 OSC 01 Phase Detector VCO XTAL_OUT1 REF_CLK Pulldown 10 11 000 001 010 011 100 101 110 111 10 01 00 M ÷18 ÷22 ÷24 ÷25 ÷32 (default) ÷40 ÷40 ÷40 ÷1 ÷2 ÷3 ÷4 (default) ÷5 ÷6 ÷8 111 ÷10 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 REF_OUT GND REF_OE M2 M1 M0 MR SEL1 SEL0 REF_CLK XTAL_IN0 XTAL_OUT0 ICS844001-21 24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm package body G Package Top View MR Pulldown M2:M0 000 001 010 011 100 101 110 VDDO_CMOS N0 N1 N2 VDDO_LVDS Q0 Q nQ0 GND nQ VDDA VDD XTAL_OUT1 XTAL_IN1 3 REF_OUT REF_OE Pulldown The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. IDT ™ / ICS™ INSERT PRODUCT NAME 1 ICS844001AG-21 REV. A SEPTEMBER 14, 2007 ICS844001-21 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER PRELIMINARY TABLE 1. PIN DESCRIPTIONS Number Name 1 VDDO_CMOS Power Type 2, 3 N0, N1 Input 4 N2 Input 5 VDDO_LVDS Power Description Output supply pin for LVCMOS output. Pullup Output divider select pins. Default ÷4. L Pulldown VCMOS/LVTTL interface levels. Output supply pin for LVDS outputs. 6, 7 Q, nQ Ouput Differential output pair. LVDS interface levels. 8, 23 GND Power Power supply ground. 9 VDDA Power Analog supply pin. 10 11 12 13 14 15 VDD XTAL_OUT1, XTAL_IN1 XTAL_OUT0, XTAL_IN0 REF_CLK Power 16, 17 SEL0, SEL1 Input 18 MR Input 19, 20 M0, M1 Input 21 M2 Input Pulldown MUX select pins. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true output Q to go low and the inver ted output nQ to Pulldown go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Pulldown Feedback divider select pins. Default ÷32. LVCMOS/LVTTL interface levels. Pullup 22 REF_OE Input Pulldown 24 REF_OUT Output Input Input Input Core supply pin. Parallel resonant cr ystal interface. XTAL_OUT1 is the output, XTAL_IN1 is the input. Parallel resonant cr ystal interface. XTAL_OUT0 is the output, XTAL_IN0 is the input. Pulldown Reference clock input. LVCMOS/LVTTL interface levels. Reference clock output enable. Default Low. LVCMOS/LVTTL interface levels. Reference clock output. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions CIN Input Capacitance 4 pF RPULLDOWN Input Pulldown Resistor 51 kΩ RPULLUP Input Pullup Resistor 51 kΩ Rout Output Impedance 7 Ω REF_OUT IDT ™ / ICS™ INSERT PRODUCT NAME 2 Minimum Typical Maximum Units ICS844001AG-21 REV. A SEPTEMBER 14, 2007 ICS844001-21 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER PRELIMINARY TABLE 3A. COMMON CONFIGURATIONS TABLE Input Reference Clock (MHz) M Divider Value N Divider Value VCO (MHz) Output Frequency (MHz) Application 27 22 8 594 74.25 HDTV 24.75 24 8 594 74.25 HDTV 14.8351649 40 8 593.4066 74.1758245 HDTV 19.44 32 4 622.08 155.52 SONET 19.44 32 8 622.08 77.76 SONET 19.44 32 1 622.08 622.08 SONET 19.44 32 2 622.08 311.04 SONET 19.53125 32 4 625 156.25 10 GigE 25 25 5 625 125 1 GigE 25 25 10 625 62.5 1 GigE 25 24 6 600 100 PCI Express 25 24 4 600 150 SATA 25 24 8 600 75 SATA 26.5625 24 6 637.5 106.25 Fibre Channel 1 26.5625 24 3 637.5 212.5 4 Gig Fibre Channel 26.5625 24 4 637.5 159.375 10 Gig Fibre Channel 31.25 18 3 562.5 187.5 12 Gig Ethernet TABLE 3C. PROGRAMMABLE N DIVIDER FUNCTION TABLE TABLE 3B. PROGRAMMABLE M DIVIDER FUNCTION TABLE Inputs Inputs Input Frequency (MHz) M2 M1 M0 M Divider Value 0 0 0 18 31.1 38.9 0 0 0 1 0 0 1 22 25.5 31.8 0 0 1 2 Minimum Maximum N2 N1 N0 N Divide Value 0 1 0 24 23.3 29.2 0 1 0 3 0 1 1 25 22.4 28.0 (default) 0 1 1 4 (default) 1 0 0 32 17.5 21.9 1 0 0 5 17.5 1 0 1 6 1 1 0 8 1 1 1 10 1 0 1 40 14.0 TABLE 3D. BYPASS MODE FUNCTION TABLE Inputs Reference PLL Mode 0 XTAL0 Active (default) 1 XTAL1 Active 1 0 REF_CLK Active 1 1 REF_CLK Bypass SEL1 SEL0 0 0 IDT ™ / ICS™ INSERT PRODUCT NAME 3 ICS844001AG-21 REV. A SEPTEMBER 14, 2007 ICS844001-21 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER PRELIMINARY ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA Outputs, VO (LVCMOS) -0.5V to VDDO + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause per manent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 82.3°C/W (0 mps) -65°C to 150°C Storage Temperature, TSTG TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO_LVDS = VDDO_CMOS = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage VDD – 0.15 3.3 VDD V VDDO_LVDS, _CMOS Output Supply Voltage 3.135 3. 3 3.465 V IDD Power Supply Current 110 mA IDDA Analog Supply Current 15 mA IDDO_LVDS, _CMOS Output Supply Current 40 mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO_CMOS = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Maximum Units VIH Input High Voltage 2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current VDD = VIN = 3.465V 150 µA VDD = VIN = 3.465V 5 µA IIL Input Low Current Test Conditions REF_CLK, SEL0, SEL1, OE_REF, MR, M0, M1, N2 M2, N0, N1 REF_CLK, SEL0, SEL1, OE_REF, MR, M0, M1, N2 M2, N0, N1 VDD = 3.465V, VIN = 0V Minimum Typical -5 µA -150 VDD = 3.465V, VIN = 0V Output High Voltage; REF_OUT 2.6 VOH NOTE 1 Output Low Voltage: REF_OUT VOL Note 1 NOTE 1: Output terminated with 50Ω to VDDO _CMOS/2. See Parameter Measurement Information Section, "3.3V Output Load Test Circuit Diagram". IDT ™ / ICS™ INSERT PRODUCT NAME 4 µA V 0.5 V ICS844001AG-21 REV. A SEPTEMBER 14, 2007 ICS844001-21 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER PRELIMINARY TABLE 4C. LVDS DC CHARACTERISTICS, VDD = VDDO_LVDS = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VOD Differential Output Voltage Test Conditions Minimum Typical Maximum Units 400 mV Δ VOD VOD Magnitude Change 50 mV VOS Offset Voltage 1.5 V Δ VOS VOS Magnitude Change 50 mV TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Fundamental Frequency 12 Units MHz 40 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW Maximum Units 700 MHz NOTE: Characterized using an 18pF parallel resonant crystal. TABLE 6. AC CHARACTERISTICS, VDD = VDDO_LVDS = VDDO_CMOS = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fOUT Output Frequency Propagation Delay, REF_CLK to NOTE 1 REF_OUT RMS Phase Jitter, (Random); NOTE 2, 3 Q, nQ Output Rise/Fall Time REF_OUT tPD tjit(Ø) tR / tF Test Conditions 2.95 ns 622.08MHz (12kHz - 20MHz) 0.92 ps 20% to 80% 300 ps 20% to 80% 300 ps 50 50 % % Output Duty Cycle IDT ™ / ICS™ INSERT PRODUCT NAME Typical 56 Q, nQ REF_OUT NOTE 1: Measured from the VDD/2 of the input to VDDO_CMOS/2 of the output. NOTE 2: Phase jitter measured using a 25MHz quar tz crystal. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. odc Minimum 5 ICS844001AG-21 REV. A SEPTEMBER 14, 2007 ICS844001-21 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER PRELIMINARY ➤ TYPICAL PHASE NOISE AT 622.08MHZ 622.08MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.92ps (typical) Raw Phase Noise Data ➤ ➤ NOISE POWER dBc Hz OC-12 Filter Phase Noise Result by adding Sonet OC-12 Filter to raw data OFFSET FREQUENCY (HZ) IDT ™ / ICS™ INSERT PRODUCT NAME 6 ICS844001AG-21 REV. A SEPTEMBER 14, 2007 ICS844001-21 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER PRELIMINARY PARAMETER MEASUREMENT INFORMATION 1.65±5% 1.65±5% VDD, VDDO_LVDS 3.3V±5% POWER SUPPLY + Float GND – VDDA SCOPE VDD, VDDO_CMOS SCOPE Qx VDDA Qx LVCMOS LVDS nQx GND -1.65V±5% 3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT 3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT Noise Power Phase Noise Plot VDD 2 Phase Noise Mask REF_CLK f1 Offset Frequency VDDO_LVCMOS f2 REF_OUT RMS Jitter = Area Under the Masked Phase Noise Plot 2 t PD RMS PHASE JITTER PROPAGATION DELAY 80% 80% 80% 80% VOD Clock Outputs 20% 20% tR Clock Outputs tF LVDS OUTPUT RISE/FALL TIME IDT ™ / ICS™ INSERT PRODUCT NAME 20% 20% tR tF LVCMOS OUTPUT RISE/FALL TIME 7 ICS844001AG-21 REV. A SEPTEMBER 14, 2007 ICS844001-21 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER VDD PRELIMINARY VDD out out LVDS ➤ ➤ ➤ DC Input LVDS 100 VOD/Δ VOD ➤ out VOS/Δ VOS out ➤ DC Input ➤ OFFSET VOLTAGE SETUP DIFFERENTIAL OUTPUT VOLTAGE SETUP nQ V DDO_CMOS 2 REF_OUT Q t PW t PW t odc = t PERIOD t PW x 100% odc = t PERIOD t PW x 100% t PERIOD LVDS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD IDT ™ / ICS™ INSERT PRODUCT NAME PERIOD LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 8 ICS844001AG-21 REV. A SEPTEMBER 14, 2007 ICS844001-21 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER PRELIMINARY APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS844001-21 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO_x should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a 0.01μF bypass capacitor should be connected to each VDDA. 3.3V VDD .01μF 10Ω VDDA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CRYSTAL INPUTS For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. LVDS OUTPUT All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, there should be no trace attached. LVCMOS OUTPUT All unused LVCMOS output can be left floating. There should be no trace attached. REF_CLK INPUT For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the REF_CLK to ground. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. CRYSTAL INPUT INTERFACE were determined using a 25MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error. The ICS844001-21 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below XTAL_IN C1 22p X1 18pF Parallel Crystal XTAL_OUT C2 22p FIGURE 2. CRYSTAL INPUt INTERFACE IDT ™ / ICS™ INSERT PRODUCT NAME 9 ICS844001AG-21 REV. A SEPTEMBER 14, 2007 ICS844001-21 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER PRELIMINARY LVCMOS TO XTAL INTERFACE impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output VDD VDD R1 Ro .1uf Rs Zo = 50 Zo = Ro + Rs XTAL_IN R2 XTAL_OUT FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE 3.3V LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 4. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 3.3V 3.3V LVDS + R1 100 - 100 Ohm Differential Transmission Line FIGURE 4. TYPICAL LVDS DRIVER TERMINATION IDT ™ / ICS™ INSERT PRODUCT NAME 10 ICS844001AG-21 REV. A SEPTEMBER 14, 2007 ICS844001-21 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER PRELIMINARY SCHEMATIC EXAMPLE optimizing frequency accuracy. One example of LVDS and one example of LVCMOS terminations are shown in this schematic. The decoupling capacitors should be located as close as possible to the power pin. Figure 5 shows an example of ICS844001-21 application schematic. In this example, the device is operated at VDD = 3.3V. The 18pF parallel resonant 25MHz crystal is used. The C1 = 22pF and C2 = 22pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for FIGURE 5. ICS844001-21 SCHEMATIC LAYOUT IDT ™ / ICS™ INSERT PRODUCT NAME 11 ICS844001AG-21 REV. A SEPTEMBER 14, 2007 ICS844001-21 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER PRELIMINARY POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS844001-21. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS844001-21 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. Core and LVDS Output Power Dissipation • Power (core, LVDS) = VDD_MAX * (IDD + IDDO_LVDS + IDDA ) = 3.465V * (110mA + 40mA + 15mA) = 572mW LVCMOS Output Power Dissipation • Output Impedance ROUT Power Dissipation due to Loading 50Ω to VDDO_CMOS/2 Output Current IOUT = VDDO_CMOS_MAX / [2 * (50Ω + ROUT)] = 3.465V / [2 * (50Ω + 7Ω)] = 30.4mA • Power Dissipation on the ROUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 72Ω * (30.4mA)2 = 6.47mW per output • Dynamic Power Dissipation at 25MHz Power (25MHz) = CPD * frequency * (VDDO_CMOS)2 = 8pF * 25MHz * (3.465V)2 = 2.4 mW Total Power Dissipation • Total Power = Power (core, LVDS) + Total Power (ROUT) + Total Power (125MHz) + Total Power (25MHz) = 572mW + 6.47mW + 2.4mW = 581mW IDT ™ / ICS™ INSERT PRODUCT NAME 12 ICS844001AG-21 REV. A SEPTEMBER 14, 2007 ICS844001-21 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER PRELIMINARY 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 82.3°C/W per Table 7 is: 70°C + 0.581W * 82.3°C/W = 118°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 7. THERMAL RESISTANCE θJA FOR 24-TSSOP, FORCED CONVECTION θJA by Velocity (Meters per Second) 0 Multi-Layer PCB, JEDEC Standard Test Boards IDT ™ / ICS™ INSERT PRODUCT NAME 82.3°C/W 13 1 2.5 78°C/W 75.9°C/W ICS844001AG-21 REV. A SEPTEMBER 14, 2007 ICS844001-21 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER PRELIMINARY RELIABILITY INFORMATION TABLE 8. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP θJA by Velocity (Meters per Second) 0 Multi-Layer PCB, JEDEC Standard Test Boards 82.3°C/W 1 2.5 78°C/W 75.9°C/W TRANSISTOR COUNT The transistor count for ICS844001-21 is: 4045 IDT ™ / ICS™ INSERT PRODUCT NAME 14 ICS844001AG-21 REV. A SEPTEMBER 14, 2007 ICS844001-21 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER PRELIMINARY PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP TABLE 9. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N A Maximum 24 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 7.90 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT ™ / ICS™ INSERT PRODUCT NAME 15 ICS844001AG-21 REV. A SEPTEMBER 14, 2007 ICS844001-21 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER PRELIMINARY TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS844001AG-21 ICS844001AG21 24 Lead TSSOP tube 0°C to 70°C ICS844001AG-21T ICS844001AG21 24 Lead TSSOP 2500 tape & reel 0°C to 70°C ICS844001AG-21LF TBD 24 Lead "Lead Free" TSSOP tube 0°C to 70°C ICS844001AG-21LFT TBD 24 Lead "Lead Free" TSSOP 2500 tape & reel 0°C to 70°C NOTE: Pats that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended termperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ INSERT PRODUCT NAME 16 ICS844001AG-21 REV. A SEPTEMBER 14, 2007 ICS844001-21 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER PRELIMINARY Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. 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