ICS844004-104 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER General Description Features The ICS844004-104 is a 4 output LVDS Synthesizer optimized to generate Fibre Channel reference clock HiPerClockS™ frequencies and is a member of the HiPerClocksTM family of high performance clock solutions from IDT. Using a 26.5625MHz 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL[1:0]): 212.5MHz, 187.5MHz, 159.375MHz, 106.25MHz and 53.125MHz. The ICS844004-104 uses IDT’s 3rd generation low phase noise VCO technology and can achieve <1ps typical rms phase jitter, easily meeting Fibre Channel jitter requirements. The ICS844004-104 is packaged in a 32-pin VFQFN package. • • Four differential LVDS outputs • Supports the following output frequencies: 212.5MHz, 187.5MHz, 159.375MHz, 106.25MHz and 53.125MHz • • VCO range: 560MHz - 680MHz • • • Full 3.3V or 2.5V output supply modes ICS Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input RMS phase jitter at 212.5MHz (637kHz – 10MHz), using a 26.5625MHz crystal: <1ps (typical) 0°C to 70°C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages MR 3 nPLL_SEL 4 212.5 (default) 8 26.5625 0 1 24 4 6 159.375 nc 5 26.5625 1 0 24 6 4 106.25 nc 6 26.5625 1 1 24 12 2 53.125 nc 7 187.5 (default) nc 8 23.4375 0 0 24 3 8 Pulldown nPLL_SEL Pulldown REF_CLK Q2 VDDO nQ2 ICS844004-104 32 Lead VFQFN 23 nQ3 22 GND 5mm x 5mm x 0.925mm package body K Package Top View 21 nc 20 nc 19 nXTAL_SEL 9 10 11 12 13 14 15 16 18 REF_CLK 17 GND 2 Q0 Pulldown 1 F_SEL[1:0] 0 0 ÷3 0 1 ÷4 1 0 ÷6 1 1 ÷12 1 26.5625MHz XTAL_IN OSC 0 VCO 637.5MHz Phase Detector (w/26.5625MHz Reference) XTAL_OUT nXTAL_SEL nc Q3 Block Diagram F_SEL[1:0] nc 24 nc 2 nc 3 nQ0 XTAL_IN 24 1 XTAL_OUT 0 32 31 30 29 28 27 26 25 Q0 VDD 0 M N M/N Output Divider Divider Divider Frequency Value Value Value (MHz) F_SEL1 26.5625 F_SEL0 VDDA F_SEL1 F_SEL0 Input Frequency (MHz) nQ1 VDDO Inputs Q1 Pin Assignment Table 1. Frequency Table nQ0 Q1 nQ1 0 Q2 Pulldown nQ2 Q3 M = 24 (fixed) nQ3 MR Pulldown IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 1 ICS844004AK-104 REV. A SEPTEMBER 15, 2008 ICS844004-104 FEMTOCLOCK™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER Table 1. Pin Descriptions Number Name 1, 2 Q0, nQ0 Type Description Output Differential output pair. LVDS interface levels. 3 MR Input Pulldown Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs nQx to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. 4 nPLL_SEL Input Pulldown Selects between the PLL and REF_CLK as input to the dividers. When LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels. 5, 6, 7, 8, 15, 16, 20, 21, 28, 29 nc Unused 9 VDDA Power 10, 12 F_SEL0, F_SEL1 Input 11 VDD Power Core supply pin. 13, 14 XTAL_OUT XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 17, 22 GND Power 18 REF_CLK Input Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels. 19 nXTAL_SEL Input Pulldown Selects between crystal or REF_CLK inputs as the PLL Reference source. Selects XTAL inputs when LOW. Selects REF_CLK when HIGH. LVCMOS/LVTTL interface levels. 23, 24 nQ3, Q3 Output Differential output pair. LVDS interface levels. 25, 32 VDDO Power Output supply pins. 26, 27 Q2, nQ2 Output Differential output pair. LVDS interface levels. 30, 31 nQ1, Q1 Output Differential output pair. LVDS interface levels. No connect. Analog supply pin. Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. Power supply ground. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLDOWN Input Pulldown Resistor 51 kΩ IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER Test Conditions 2 Minimum Typical Maximum Units ICS844004AK-104 REV. A SEPTEMBER 15, 2008 ICS844004-104 FEMTOCLOCK™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuos Current Surge Current 10mA 15mA Package Thermal Impedance, θJA 42.4°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 3A. Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter VDD Core Supply Voltage VDDA Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V Analog Supply Voltage VDD – 0.12 3.3 VDD V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 105 mA IDDA Analog Supply Current 12 mA IDDO Output Supply Current 120 mA Table 3B. Power Supply DC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = 0°C to 70°C Symbol Parameter VDD Core Supply Voltage VDDA Minimum Typical Maximum Units 2.375 2.5 2.625 V Analog Supply Voltage VDD – 0.10 2.5 VDD V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 100 mA IDDA Analog Supply Current 10 mA IDDO Output Supply Current 100 mA IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER Test Conditions 3 ICS844004AK-104 REV. A SEPTEMBER 15, 2008 ICS844004-104 FEMTOCLOCK™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER Table 3C. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V ± 5% or 2.5V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum VIH Input High Voltage VDD = 3.3V VIL Input Low Voltage IIH Input High Current REF_CLK, MR, F_SEL[0:1], nPLL_SEL, nXTAL_SEL VDD = VIN = 3.465V or 2.625V IIL Input Low Current REF_CLK, MR, F_SEL[0:1], nPLL_SEL, nXTAL_SEL VDD = 3.465V or 2.625V, VIN = 0V Typical Maximum Units 2 VDD + 0.3 V VDD = 2.5V 1.7 VDD + 0.3 V VDD = 3.3V -0.3 0.8 V VDD = 2.5V -0.3 0.7 150 -5 µA µA Table 3D. LVDS DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter VOD Differential Output Voltage ∆VOD VOD Magnitude Change VOS Offset Voltage ∆VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 300 450 600 mV 50 mV 1.65 V 50 mV 1.2 1.425 Table 3E. LVDS DC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = 0°C to 70°C Symbol Parameter VOD Differential Output Voltage ∆VOD VOD Magnitude Change VOS Offset Voltage ∆VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 250 400 550 mV 50 mV 1.4 V 50 mV 1.0 1.2 Table 4. Crystal Characteristics Parameter Test Conditions Minimum Maximum Units 28.33 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Mode of Oscillation Typical Fundamental Frequency 23.33 26.5625 NOTE: Characterized using an 18pF parallel resonant crystal. IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 4 ICS844004AK-104 REV. A SEPTEMBER 15, 2008 ICS844004-104 FEMTOCLOCK™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER AC Electrical Characteristics Table 5A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Parameter Symbol fOUT tsk(o) tjit(Ø) tR / tF odc Output Frequency Test Conditions Minimum Typical Maximum F_SEL[1:0] = 00 186.67 226.66 MHz F_SEL[1:0] = 01 140 170 MHz F_SEL[1:0] = 10 93.33 113.33 MHz F_SEL[1:0] = 11 46.67 56.66 MHz 35 ps Output Skew; NOTE 1, 2 RMS Phase Jitter, Random; NOTE 3 Output Rise/Fall Time Output Duty Cycle Units 212.5MHz, (637kHz - 10MHz) 0.73 ps 159.375MHz, (637kHz - 10MHz) 0.78 ps 106.25MHz, (637kHz -10MHz) 0.92 ps 53.125MHz, (637kHz - 10MHz) 0.95 ps 187.5MHz, (637kHz - 10MHz) 0.75 ps 20% to 80% 250 500 ps F_SEL[1:0] ≠ ÷3 48 52 % F_SEL[1:0] = ÷3 40 60 % NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the differential cross points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plots. Table 5B. AC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = 0°C to 70°C Parameter Symbol fOUT tsk(o) tjit(Ø) Output Frequency Test Conditions Minimum Typical Maximum F_SEL[1:0] = 00 186.67 226.66 MHz F_SEL[1:0] = 01 140 170 MHz F_SEL[1:0] = 10 93.33 113.33 MHz F_SEL[1:0] = 11 46.67 56.66 MHz Output Skew; NOTE 1, 2 RMS Phase Jitter, Random; NOTE 3 tR / tF Output Rise/Fall Time odc Output Duty Cycle 35 Units ps 212.5MHz, (637kHz - 10MHz) 0.72 ps 159.375MHz, (637kHz - 10MHz) 0.88 ps 106.25MHz, (637kHz -10MHz) 0.89 ps 53.125MHz, (637kHz - 10MHz) 0.96 ps 187.5MHz, (637kHz - 10MHz) 0.74 ps 20% to 80% 250 550 ps F_SEL[1:0] ≠ ÷3 48 52 % F_SEL[1:0] = ÷3 40 60 % NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the differential cross points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plots. IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 5 ICS844004AK-104 REV. A SEPTEMBER 15, 2008 ICS844004-104 FEMTOCLOCK™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER ➝ Typical Phase Noise at 106.25MHz (3.3V) Fibre Channel Filter Raw Phase Noise Data ➝ ➝ Noise Power dBc Hz 106.25MHz RMS Phase Jitter (Random) 637kHz to 10MHz = 0.89ps (typical) Phase Noise Result by adding a Fibre Channel filter to raw data Offset Frequency (Hz) ➝ Typical Phase Noise at 212.5MHz (3.3V) Fibre Channel Filter ➝ Noise Power dBc Hz 212.5MHz RMS Phase Jitter (Random) 637kHz to 10MHz = 0.72ps (typical) ➝ Raw Phase Noise Data Phase Noise Result by adding a Fibre Channel filter to raw data Offset Frequency (Hz) IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 6 ICS844004AK-104 REV. A SEPTEMBER 15, 2008 ICS844004-104 FEMTOCLOCK™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER Parameter Measurement Information SCOPE 3.3V±5% POWER SUPPLY + Float GND – VDD, VDDO VDDA SCOPE Qx VDD, VDDO VDDA 2.5V±5% POWER SUPPLY + Float GND – LVDS Qx LVDS nQx nQx 3.3V LVDS Output Load AC Test Circuit 2.5V LVDS Output Load AC Test Circuit Phase Noise Plot Noise Power nQx Qx Phase Noise Mask nQy Qy tsk(o) f1 Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot Output Skew RMS Phase Jitter nQ[0:3] nQ[0:3] 80% 80% QA[0:3} VOD QA[0:3} t PW t 20% 20% tR tF VOS odc = GND t PW x 100% t PERIOD Output Rise/Fall Time IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER PERIOD Output Duty Cycle/Pulse Width/Period 7 ICS844004AK-104 REV. A SEPTEMBER 15, 2008 ICS844004-104 FEMTOCLOCK™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER Parameter Measurement Information, continued VDD VDD out 100 ➤ DC Input LVDS VOD/∆ VOD out out ➤ LVDS ➤ DC Input ➤ out ➤ VOS/∆ VOS ➤ Differential Output Voltage Setup Offset Voltage Setup Application Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS844004-104 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 3.3V or 2.5V VDD .01µF 10Ω .01µF 10µF VDDA Figure 1. Power Supply Filtering 8 ICS844004AK-104 REV. A SEPTEMBER 15, 2008 ICS844004-104 FEMTOCLOCK™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER Crystal Input Interface The ICS844004-104 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 26.5625MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. XTAL_IN C1 18pF X1 18pF Parallel Crystal XTAL_OUT C2 18pF Figure 2. Crystal Input Interface LVCMOS to XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output VDD impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. VDD R1 Ro Rs 0.1µf 50Ω XTAL_IN Zo = Ro + Rs R2 XTAL_OUT Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 9 ICS844004AK-104 REV. A SEPTEMBER 15, 2008 ICS844004-104 FEMTOCLOCK™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER Recommendations for Unused Input and Output Pins Inputs: Outputs: LVCMOS Control Pins LVDS Outputs All control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, we recommend that there is no trace attached. REF_CLK INPUT For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the REF_CLK to ground. 3.3V, 2.5V LVDS Driver Termination A general LVDS interface is shown in Figure 4. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 3.3V or 2.5V VDD 50Ω LVDS Driver + R1 100Ω – 50Ω 100Ω Differential Transmission Line Figure 4. Typical LVDS Driver Termination IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 10 ICS844004AK-104 REV. A SEPTEMBER 15, 2008 ICS844004-104 FEMTOCLOCK™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 5. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/Electrically Enhance Leadframe Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER LAND PATTERN (GROUND PAD) PIN PIN PAD Figure 5. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 11 ICS844004AK-104 REV. A SEPTEMBER 15, 2008 ICS844004-104 FEMTOCLOCK™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER Schematic Example Figure 6 shows an example of ICS844004-104 application schematic. In this example, the device is operated at VDD = VDDO = 3.3V. The 18pF parallel resonant 25MHz crystal is used. The C1 = 33pF and C2 = 22pF are recommended for frequency accuracy. VDDO Logic Control Input Examples Set Logic Input to '0' RU2 Not Install To Logic Input pins 1 2 MR 3 nPLL_SEL 4 5 6 7 8 To Logic Input pins RD1 Not Install 32 31 30 29 28 27 26 25 U1 RD2 1K VD D O Q1 nQ 1 nc nc nQ 2 Q2 VD D O RU1 1K Zo = 50 Ohm 0.1uF C3 Q3 nQ3 GND nc nc nXTAL_SEL REF_CLK GND Q0 nQ0 MR nPLL_SEL nc nc nc nc VD D A F _SEL0 VD D F _SEL1 XT AL_O U T XT AL_I N nc nc VDD Zo = 50 Ohm + C4 0.1uF nQ 0 VDD Q0 VDDO Q0 Set Logic Input to '1' For different board layouts, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. Two examples of LVDS for receiver without built-in termination are show in this schematic. 24 23 22 21 20 19 18 17 R2 100 nQ0 - Q3 nQ3 VDD=3.3V nXTAL_SEL REF_CLK VDDO=3.3V R1 10 VDDA ICS844004-104 F_SEL0 C5 10uF C6 9 10 11 12 13 14 15 16 VDD VDD Q3 0.01u C8 .1uf Zo = 50 Ohm F_SEL1 R3 50 + X1 25MHz F p 8 1 C2 27pF C1 33pF Q1 nQ3 R1 Zo = 50 Ohm C7 0.1uF R4 50 - Zo = 50 33 Alternate LVDS Termination Driv er_LVCMOS Figure 6. ICS844004-104 Schematic Example IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 12 ICS844004AK-104 REV. A SEPTEMBER 15, 2008 ICS844004-104 FEMTOCLOCK™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER Power Considerations This section provides information on power dissipation and junction temperature for the ICS844004-104. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS844004-104 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (105mA + 12mA) = 405.4mW • Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 120mA = 415.8mW Total Power_MAX = 405.4mW + 415.8mW = 821.2mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 42.4°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.821W * 42.4°C/W = 104.8°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 7. Thermal Resistance θJA for 32 Lead VFQFN, Forced Convection θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 0 1 2.5 42.4°C/W 37.0°C/W 33.2°C/W 13 ICS844004AK-104 REV. A SEPTEMBER 15, 2008 ICS844004-104 FEMTOCLOCK™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER Reliability Information Table 8. θJA vs. Air Flow Table for a 32 Lead VFQFN θJA vs. Air Flow Meter per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 42.4°C/W 37.0°C/W 33.2°C/W Transistor Count The transistor count for ICS844004-104 is: 2914 Package Outline and Package Dimensions Package Outline - K Suffix for VFQFN Packages (Ref.) S eating Plan e N &N Even (N -1)x e (R ef.) A1 Ind ex Area A3 N L N e (Ty p.) 2 If N & N 1 Anvil Singula tion are Even 2 OR E2 (N -1)x e (Re f.) E2 2 To p View b A (Ref.) D Chamfer 4x 0.6 x 0.6 max OPTIONAL e D2 2 N &N Odd 0. 08 C Th er mal Ba se D2 C Table 9. Package Dimensions NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 8 below. JEDEC Variation: VHHD-2/-4 All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.25 0.30 8 ND & NE D&E 5.00 Basic D2 & E2 3.0 3.3 e 0.50 Basic L 0.30 0.40 0.50 Reference Document: JEDEC Publication 95, MO-220 IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 14 ICS844004AK-104 REV. A SEPTEMBER 15, 2008 ICS844004-104 FEMTOCLOCK™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER Ordering Information Table 10. Ordering Information Part/Order Number 844004AK-104 844004AK-104T 844004AK-104LF 844004AK-104LFT Marking ICS4044A104 ICS4044A104 ICS004A104L ICS004A104L Package 32 Lead VFQFN 32 Lead VFQFN “Lead-Free” 32 Lead VFQFN “Lead-Free” 32 Lead VFQFN Shipping Packaging Tray 2500 Tape & Reel Tray 2500 Tape & Reel Temperature 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 15 ICS844004AK-104 REV. A SEPTEMBER 15, 2008 ICS844004-104 FEMTOCLOCK™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER Contact Information: www.IDT.com www.IDT.com Sales Technical Support 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT [email protected] +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA