FemtoClock™
Crystal-to-LVDS/LVCMOS Frequency
ICS8402015I
DATASHEET
General Description
Features
ICS8402015I is a low phase noise Clock Synthesizer
and is a member of the HiPerClockS™family of high
HiPerClockS™
performance clock solutions from IDT. The device
provides three banks of outputs and a reference clock.
Each bank can be enabled by using output enable
pins. A 25MHz or 50MHz, 18pF parallel resonant crystal is used to
generate 25MHz LVCMOS, 125MHz LVCMOS and 125MHz LVDS
outputs. ICS8402015I is packaged in a small, 32-pin VFQFN
package that is optimum for applications with space limitations.
•
ICS
Three banks of outputs:
Bank A: three single-ended LVCMOS/LVTTL outputs at 25MHz
or 50MHz
Bank B: three single-ended LVCMOS/LVTTL outputs at 125MHz
Bank C: three differential LVDS outputs at 125MHz
Reference LVCMOS/LVTTL output at 25MHz
•
•
•
Crystal input frequency: 25MHz
•
RMS phase jitter @ 25MHz, using a 25MHz crystal
(12kHz - 1MHz): 0.64ps (typical) LVCMOS output
•
•
•
Full 3.3V supply mode
Maximum output frequency: 125MHz
RMS phase jitter @ 125MHz, using a 25MHz crystal
(637kHz - 62.5MHz): 0.373ps (typical) LVDS output
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
VDDA
GND
OE0
OE1
OE2
XTAL_IN
GND
XTAL_OUT
Pin Assignment
32 31 30 29 28 27 26 25
VDDO_REF
1
24
VDDO_C
REF_OUT
2
23
nQC2
GND
3
22
QC2
GND
4
21
nC1
20
QA1
6
19
nQC0
QA2
7
18
QC0
VDDO_A
8
17
VDDO_C
GND
MR
VDD
QB2
GND
10 11 12 13 14 15 16
QB1
9
QB0
5
QC1
VDDO_B
QA0
ICS8402015I
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
ICS8402015AKI REVISION A JUNE 25, 2009
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©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Block Diagram
OE1 = Pullup
3
OE[2:0] OE0, OE2 = Pulldown
OE
LOGIC
LVCMOS - 25MHz or
50MHz
QA0
÷10
÷20
QA1
QA2
25MHz
XTAL_IN
LVCMOS - 125MHz
OSC
XTAL_OUT
QB0
VCO
Phase
Detector
500MHz
÷4
QB1
QB2
÷20
LVDS - 125MHz
QC0
nQC0
÷4
QC1
nQC1
QC2
nQC2
MR Pulldown
LVCMOS - 25MHz
REF_OUT
ICS8402015AKI REVISION A JUNE 25, 2009
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©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Number
Name
Type
Description
1
VDDO_REF
Power
Output supply pin for REF_OUT output.
2
REF_OUT
Output
Reference clock output. LVCMOS/LVTTL interface levels.
3, 4, 13, 16,
25, 32
GND
Power
Power supply ground.
5, 6, 7
QA0, QA1, QA2
Output
Single-ended Bank A clock outputs.LVCMOS/LVTTL interface levels.
8
VDDO_A
Power
Power output supply pin for Bank A LVCMOS outputs.
9
VDDO_B
Power
Power output supply pin for Bank B LVCMOS outputs.
10, 11, 12
QB0, QB1, QB2
Output
Single-ended Bank B clock outputs.LVCMOS/LVTTL interface levels.
14
MR
Input
15
VDD
Power
Core supply pin.
17, 24
VDDO_C
Power
Power output supply pin for Bank C LVDS outputs.
18, 19
QC0, nQC0
Output
Differential Bank C clock outputs. LVDS interface levels.
20, 21
QC1, nQC1
Output
Differential Bank C clock outputs. LVDS interface levels.
22, 23
QC2, nQC2
Output
Differential Bank C clock outputs. LVDS interface levels.
26
VDDA
Power
Analog supply pin.
27, 29
OE0, OE2
Input
Pulldown
Output enable and configuration pins. See Table 3.
LVCMOS/LVTTL interface levels.
28
OE1
Input
Pullup
Output enable and configuration pin. See Table 3.
LVCMOS/LVTTL interface levels.
30, 31
XTAL_IN,
XTAL_OUT
Input
Pulldown
Master reset, resets the internal dividers. During reset, LVCMOS outputs are pulled
LOW, and LVDS outputs are pulled LOW and HIGH (QCx pulled LOW, nQCx
pulled HIGH). LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_OUT is the output, XTAL_IN is the input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
CIN
Input Capacitance
CPD
Power Dissipation
Capacitance (per output)
RPULLUP
Minimum
Typical
Maximum
Units
4
pF
15
pF
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
ROUT
Output
Impedance
20
Ω
VDD, VDDO_A, VDDO_B, VDDO_C = 3.465V
QA[0:2],
QB[0:2],
REF_OUT
ICS8402015AKI REVISION A JUNE 25, 2009
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©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Function Table
Table 3. OE Function and ConfigurationTable
Inputs
Output Frequency (MHz)
Bank A
Bank B
Bank C
OE2
OE1
OE0
A0
A1
A2
B0
B1
B2
C0
C1
C2
0
0
0
25
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
125
Hi-Z
Hi-Z
0
0
1
25
Hi-Z
Hi-Z
125
Hi-Z
Hi-Z
125
Hi-Z
Hi-Z
0*
1*
0*
25
25
Hi-Z
Hi-Z
Hi-Z
Hi-Z
125
125
Hi-Z
0
1
1
25
25
25
125
125
125
125
125
125
1
0
0
50
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
125
Hi-Z
Hi-Z
1
0
1
25
25
Hi-Z
125
125
Hi-Z
125
125
Hi-Z
1
1
0
50
50
Hi-Z
Hi-Z
Hi-Z
Hi-Z
125
125
Hi-Z
1
1
1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
*Default
ICS8402015AKI REVISION A JUNE 25, 2009
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©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, IO (LVCMOS)
-0.5V to VDDO_LVCMOS + 0.5V
Outputs, IO (LVDS)
Continuos Current
Surge Current
10mA
15mA
Operating Temperature Range, TA
-40°C to +85°C
Package Thermal Impedance, θJA
37°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDO_A = VDDO_B = VDDO_C = VDDO_REF = 3.3V±5%, TA = -40°C to 85°C
Symbol
Parameter
VDD
Core Supply Voltage
VDDA
Analog Supply Voltage
Test Conditions
VDDO_A,
VDDO_B,
Output Supply Voltage
VDDO_C,
VDDO_REF
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
VDD – 0.36
3.3
VDD
V
3.135
3.3
3.465
V
IDD
Power Supply Current
30
mA
IDDA
Analog Supply Current
36
mA
IDDO_A,
IDDO_B,
IDDO_C,
IDDO_REF
Total Output Supply Current
26
mA
ICS8402015AKI REVISION A JUNE 25, 2009
Outputs Unused
5
©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Table 4C. LVCMOS/LVTTL DC Characteristics, VDD = VDDO_A = VDDO_B = VDDO_REF = 3.3V±5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VIH
Input High Voltage
2
VDD + 0.3
V
VIL
Input Low Voltage
-0.3
0.8
V
Input
High Current
OE1
IIH
VDD = VIN = 3.465V
5
µA
OE0, OE2, MR
VDD = VIN = 3.465V
150
µA
Input
Low Current
OE1
VDD = 3.465V
-150
µA
IIL
OE0, OE2, MR
VDD = 3.465V
-5
µA
VOH
Output
High Voltage
QA0:QA2,
QB0:QB2,
REF_OUT
VDDO_REF = 3.3V±5%, IOH = -12mA
2.6
V
VOL
Output
Low Voltage
QA0:QA2,
QB0:QB2,
REF_OUT
VDDO_REF = 3.3V±5%, IOL = 12mA
0.5
V
Table 4D. LVDS DC Characteristics, VDD = VDDO_C = 3.3V±5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
VOD
Differential Output Voltage
∆VOD
VOD Magnitude Change
VOS
Offset Voltage
∆VOS
VOS Magnitude Change
IOz
High Impedance Leakage
IOFF
Power Off Leakage
IOSD
Differential Output Short Circuit Current
IOS
Output Short Circuit Current
Minimum
Typical
Maximum
Units
300
450
575
mV
50
mV
1.575
V
50
mV
-10
+10
µA
-20
+20
µA
-3.5
-5
mA
-3.5
-5
mA
Maximum
Units
1.325
1.4
Table 5. Crystal Characteristics
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Fundamental
Frequency
25
MHz
Equivalent Series Resistance
50
Ω
Shunt Capacitance
7
pF
ICS8402015AKI REVISION A JUNE 25, 2009
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©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Table 6. AC Characteristics, VDD = VDDO_A = VDDO_B = VDDO_C = VDDO_REF = 3.3V±5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
QA[0:2]
fout
Output Frequency
tsk(b)
tR / t F
odc
RMS Phase Noise
Jitter; NOTE 1
Bank Skew;
NOTE 2, 3
Output
Rise/Fall Time
Output
Duty Cycle
Maximum
25
Units
MHz
QA[0:1]
50
MHz
QB[0:2]
125
MHz
QC[0:2]/
nQC[0:2]
125
MHz
REF_OUT
tjit(Ø)
Typical
25
MHz
QA0:QA2,
REF_OUT
25MHz, Integration Range:
12kHz - 1MHz
0.642
ps
QB0:QB2
125MHz, Integration Range:
637kHz - 62.5MHz
0.389
ps
QC0:QC2
125MHz, Integration Range:
637kHz - 62.5MHz
0.373
ps
QA[0:2], QB[0:2]
45
ps
QC[0:2]/nQC[0:2]
35
ps
QA[0:2], QB[0:2],
REF_OUT
20% to 80%
0.425
1.15
ns
QC[0:2]/
nQC[0:2]
20% to 80%
145
415
ps
QA[0:2], QB[0:2],
REF_OUT
48
52
%
QC[0:2]/
nQC[0:2]
48
52
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: Please refer to Phase Noise Plots.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
ICS8402015AKI REVISION A JUNE 25, 2009
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©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Parameter Measurement Information
1.65V±5%
1.65V±5%
SCOPE
Qx
VDD,
VDDO_C
3.3V±5%
POWER SUPPLY
+ Float GND –
SCOPE
VDD,
VDDO_A,
VDDA
LVDS
VDDO_B
VDDA
Qx
LVCMOS
nQx
GND
-1.65V±5%
3.3V LVDS Output Load AC Test Circuit
3.3V LVCMOS Output Load AC Test Circuit
Phase Noise Plot
Noise Power
nQC[0:2]
Qx[0:2]
Phase Noise Mask
nQC[0:2]
Qx[0:2]
f1
Offset Frequency
tsk(b)
f2
Where X = Bank A, Bank B or Bank C outputs
RMS Jitter = Area Under the Masked Phase Noise Plot
Bank Skew
RMS Phase Jitter
V
nQC{0:2]
DDO_CMOS
QA[0:2],
QB[0:2]
2
QC{0:2]
t PW
t
t PW
t PW
odc =
t
PERIOD
odc =
x 100%
t PW
x 100%
t PERIOD
t PERIOD
Single-Ended Output Duty Cycle/Pulse Width/Period
ICS8402015AKI REVISION A JUNE 25, 2009
PERIOD
Differential Output Duty Cycle/Pulse Width/Period
8
©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Parameter Measurement Information, continued
nQC{0:2]
80%
80%
80%
80%
VOD
QA[0:2], QB[0:2]
20%
20%
tR
LVDS Output Rise/Fall Time
out
+
Float GND
_
IOZ
DC Input
tF
tR
LVCMOS Output Rise/Fall Time
3.3V±5% POWER SUPPLY
20%
20%
QC{0:2]
tF
VDD
➤
out
LVDS
IOZ
➤
DC Input
out
➤
LVDS
IOSD
out
High Impedance Leakage Current Setup
Differential Output Short Circuit Setup
VDD
VDD
out
100
➤
DC Input
LVDS
VOD/∆ VOD
out
out
➤
LVDS
➤
DC Input
➤
out
➤
VOS/∆ VOS
➤
Differential Output Voltage Setup
ICS8402015AKI REVISION A JUNE 25, 2009
Offset Voltage Setup
9
©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Parameter Measurement Information, continued
VDD
out
DC Input
➤
IOS
LVDS
LVDS
➤
➤
IOSB
VDD
IOFF
out
Power Off Leakage Setup
Output Short Circuit Current Setup
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS8402015I provides
separate power supplies to isolate any high switching noise from the
outputs to the internal PLL. VDD, VDDA, VDDO_A, VDDO_B, VDDO_C, and
VDDO_REF should be individually connected to the power supply
plane through vias, and 0.01µF bypass capacitors should be used for
each pin. Figure 1 illustrates this for a generic VDD pin and also
shows that VDDA requires that an additional 10Ω resistor along with
a 10µF bypass capacitor be connected to the VDDA pin.
3.3V
VDD
.01µF
10Ω
.01µF
10µF
VDDA
Figure 1. Power Supply Filtering
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
LVDS Outputs
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
All unused LVDS outputs should be terminated with 100Ω resistor
between the differential pair.
LVCMOS Outputs
All unused LVCMOS output can be left floating. There should be no
trace attached.
ICS8402015AKI REVISION A JUNE 25, 2009
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©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Crystal Input Interface
The ICS8402015I has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in Figure 2 below
were determined using a 25MHz, 18pF parallel resonant crystal and
were chosen to minimize the ppm error.
XTAL_IN
C1
27p
X1
18pF Parallel Crystal
XTAL_OUT
C2
27p
Figure 2. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The input
edge rate can be as slow as 10ns. For LVCMOS signals, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
VDD
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the crystal input will attenuate the signal in half. This can be done in
one of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50Ω applications, R1 and R2
can be 100Ω. This can also be accomplished by removing R1 and
making R2 50Ω.
VDD
R1
Ro
Rs
0.1µf
50Ω
XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
ICS8402015AKI REVISION A JUNE 25, 2009
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©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
3.3V LVDS Driver Termination
A general LVDS interface is shown in Figure 4. In a 100Ω differential
transmission line environment, LVDS drivers require a matched load
termination of 100Ω across near the receiver input. For a multiple
LVDS outputs buffer, if only partial outputs are used, it is
recommended to terminate the unused outputs.
3.3V
50Ω
3.3V
LVDS Driver
+
R1
100Ω
–
50Ω
100Ω Differential Transmission Line
Figure 4. Typical LVDS Driver Termination
ICS8402015AKI REVISION A JUNE 25, 2009
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©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 5. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s
Thermally/Electrically Enhance Leadframe Base Package, Amkor
Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
PIN
PIN PAD
SOLDER
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
LAND PATTERN
(GROUND PAD)
PIN
PIN PAD
Figure 5. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
ICS8402015AKI REVISION A JUNE 25, 2009
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©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Schematic Example
frequency accuracy. For different board layouts, the C1 and C2 may
be slightly adjusted for optimizing frequency accuracy. Two example
of LVDS for receiver without built-in termination and one example of
LVCMOS are shown in this schematic.
Figure 6 shows an example of ICS8402015I application schematic. In
this example, the device is operated at VDD = VDDO_REF = VDDO_A =
VDDO_B = VDDO_C = 3.3V. The 18pF parallel resonant 25MHz crystal
is used. The C1 = 27pF and C2 = 27pF are recommended for
Logic Input Pin Examples
QC2
Set Logic
Input to
'1'
VDD
Set Logic
Input to
'0'
VDD
RU1
1K
RU2
Not Install
To Logic
Input
pins
nQC2
+
To Logic
Input
pins
RD1
Not Install
QC0
C3
0.01uF
C6
10uF
25
26
27
28
29
30
31
32
OE0
OE1
OE2
XTAL_IN
F
p
8
1
C1
27pF
24
23
22
21
20
19
18
17
VDDA
X1
25MHz
XTAL_OUT
GND
VDDA
OE0
OE1
OE2
XTAL_IN
XTAL_OUT
GND
-
VDD=3.3V
VDD
GND
VDD
MR
GND
QB2
QB1
QB0
VDDO_B
16
15
14
13
12
11
10
9
VDD
MR
nQC0
Zo = 50 Ohm
QC0
QB2
QB2
R3
50
+
C4
0.1uF
Zo = 50 Ohm
nQC0
C5
0.1uF
R4
50
-
1
2
3
4
5
6
7
8
C2
27pF
R1
100
VDDO=3.3V
VD D O _C
nQ C 2
QC 2
nQ C 1
QC 1
nQ C 0
QC 0
VD D O _C
10
VD D O _R EF
R EF _O U T
GN D
GN D
Q A0
Q A1
Q A2
VD D O _A
R2
Zo = 50 Ohm
nQC2
VDDO
RD2
1K
U1
VDD
Zo = 50 Ohm
QC2
Alternate
LVDS
Termination
VDDO
(U1:1) VDDO (U1:8) (U1:9)
C7
0.1uF
C8
0.1uF
(U1:17)
C9
0.1uF
R5
30
(U1:24)
C10
0.1uF
Zo = 50 Ohm
C11
0.1uF
LVCMOS
REF_OUT
R6
30
Zo = 50 Ohm
LVCMOS
Figure 6.ICS8402015I Schematic Example
ICS8402015AKI REVISION A JUNE 25, 2009
14
©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8402015I.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS8402015I is the sum of the core power plus the analog power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
Core and LVDS Output Power Dissipation
•
Power (core, LVDS) = VDD_MAX * (IDD + IDDO_X + IDDA) = 3.465V * (30mA + 26mA + 36mA) = 318.78mW
LVCMOS Output Power Dissipation
•
Output Impedance ROUT Power Dissipation due to Loading 50Ω to VDDO/2
Output Current IOUT = VDDO_MAX / [2 * (50Ω + ROUT)] = 3.465V / [2 * (50Ω + 20Ω)] = 24.7mA
•
Power Dissipation on the ROUT per LVCMOS output
Power (ROUT) = ROUT * (IOUT)2 = 20Ω * (24.7mA)2 = 12.25mW per output
•
Total Power Dissipation on the ROUT
Total Power (ROUT) = 12.25mW * 6 = 73.5mW
Total Power Dissipation
•
Total Power
= Power (core, LVDS) + Total Power (ROUT)
= 318.78mW + 73.5mW
= 392.28mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The
maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 37°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.392W * 37°C/W = 99.5°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance θJA for 32 Lead VFQFN, Forced Convection
θJA Vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
ICS8402015AKI REVISION A JUNE 25, 2009
0
1
2.5
37.0°C/W
32.4°C/W
29.0°C/W
15
©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Reliability Information
Table 8. θJA vs. Air Flow Table for a 32 Lead VFQFN
θJA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
37.0°C/W
32.4°C/W
29.0°C/W
Transistor Count
The transistor count for ICS8402015I is: 2311
Package Outline and Package Dimensions
Package Outline - K Suffix for 32 Lead VFQFN
(Ref.)
S eating Plan e
N &N
Even
(N -1)x e
(R ef.)
A1
Ind ex Area
A3
N
L
N
e (Ty p.)
2 If N & N
1
Anvil
Singula tion
are Even
2
OR
E2
(N -1)x e
(Re f.)
E2
2
To p View
b
A
(Ref.)
D
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
e
D2
2
N &N
Odd
0. 08
C
Th er mal
Ba se
D2
C
Table 9. Package Dimensions
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This drawing
is not intended to convey the actual pin count or pin layout of this
device. The pin count and pinout are shown on the front page. The
package dimensions are in Table 9.
JEDEC Variation: VHHD-2/-4
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
32
A
0.80
1.00
A1
0
0.05
A3
0.25 Ref.
b
0.18
0.25
0.30
8
ND & NE
D&E
5.00 Basic
D2 & E2
3.0
3.3
e
0.50 Basic
L
0.30
0.40
0.50
Reference Document: JEDEC Publication 95, MO-220
ICS8402015AKI REVISION A JUNE 25, 2009
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©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Ordering Information
Table 10. Ordering Information
Part/Order Number
8402015AKILF
8402015AKILFT
Marking
ICS02015AIL
ICS02015AIL
Package
“Lead-Free” 32 Lead VFQFN
“Lead-Free” 32 Lead VFQFN
Shipping Packaging
Tray
2500 Tape & Reel
Temperature
-40°C to 85°C
-40°C to 85°C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support
devices or critical medical instruments.
ICS8402015AKI REVISION A JUNE 25, 2009
17
©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Revision History Sheet
Rev
Table
Page
A
T10
17
ICS8402015AKI REVISION A JUNE 25, 2009
Description of Change
Date
Ordering Information Table - added “I” in part/order number.
18
6/25/09
©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
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FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
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