IDT ICS844021BGI

PRELIMINARY
ICS844021I-01
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS844021I-01 is an Ethernet Clock Generator
ICS
and a member of the HiPerClocksTM family of high
HiPerClockS™
performance devices from IDT. The ICS844021I01 uses an 18pF parallel resonant crystal over the
range of 24.5MHz – 34MHz. For Ethernet applications, a 25MHz crystal is used. The ICS844021I-01 has
excellent <1ps phase jitter performance, over the 1.875MHz –
20MHz integration range. The ICS844021I-01 is packaged in a
small 8-pin TSSOP, making it ideal for use in systems with
limited board space.
• One Differential LVDS output
• Crystal oscillator interface, 18pF parallel resonant crystal
(24.5MHz – 34MHz)
• Output frequency range: 122.5MHz – 170MHz
• VCO range: 490MHz – 680MHz
• RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz – 20MHz): 0.32ps (typical) @ 3.3V
• 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
COMMON CONFIGURATION TABLE - Gb ETHERNET
Inputs
Crystal Frequency (MHz)
M
N
25
20
4
Multiplication
Value M/N
5
Output Frequency
(MHz)
125
26.666
20
4
5
133.33
33.33
20
4
5
166.66
BLOCK DIAGRAM
OE
PIN ASSIGNMENT
Pullup
XTAL_IN
OSC
Phase
Detector
VCO
490MHz - 680MHz
N = ÷4 (fixed)
XTAL_OUT
Q
nQ
VDDA
GND
XTAL_OUT
XTAL_IN
1
2
3
4
8
7
6
5
VDD
Q
nQ
OE
ICS844021I-01
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
M = ÷20 (fixed)
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT ™ / ICS™ LVDS CLOCK GENERATOR
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ICS844021I-01
FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number
Name
1
VDDA
Power
Type
Description
Analog supply pin.
2
3,
4
GND
XTAL_OUT,
XTAL_IN
Power
5
OE
Input
6, 7
nQ, Q
Output
Power supply ground.
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
Output enable pin. When HIGH, Q/nQ output is active.
When LOW, the Q/nQ output is in a high impedance state.
LVCMOS/LVTTL interface levels.
Differential clock outputs. LVDS interface levels.
8
VDD
Power
Core supply pin.
Input
Pullup
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
IDT ™ / ICS™ LVDS CLOCK GENERATOR
Test Conditions
2
Minimum
Typical
Maximum
Units
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
Inputs, VI
Outputs, IO (LVDS)
Continuous Current
Surge Current
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
-0.5V to VDD + 0.5 V
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
10mA
15mA
beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
Package Thermal Impedance, θJA 129.5°C/W (0 mps)
Storage Temperature, TSTG
conditions for extended periods may affect product reliability.
-65°C to 150°C
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VDD
Core Supply Voltage
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
VDDA
Analog Supply Voltage
VDD – 0.08
3.3
VDD
V
IDD
Power Supply Current
55
mA
IDDA
Analog Supply Current
8
mA
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VDD
Core Supply Voltage
Test Conditions
Minimum
Typical
Maximum
Units
2.375
2.5
2.625
V
VDDA
Analog Supply Voltage
VDD – 0.08
2.5
VDD
V
IDD
Power Supply Current
52
mA
IDDA
Analog Supply Current
8
mA
TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Maximum
Units
VDD = 3.3V
2
VDD + 0.3
V
VDD = 2.5V
1.7
VDD + 0.3
V
VDD = 3.3V
-0.3
0.8
V
VDD = 2.5V
-0.3
0.7
V
5
µA
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
VDD = VIN = 3.465V or 2.625V
IIL
Input Low Current
VDD = 3.465V or 2.625V, VIN = 0V
IDT ™ / ICS™ LVDS CLOCK GENERATOR
3
-150
Typical
µA
ICS844021BGI-01 REV. C SEPTEMBER 27, 2007
ICS844021I-01
FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR
PRELIMINARY
TABLE 3D. LVDS DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VOD
Differential Output Voltage
400
mV
Δ VOD
VOD Magnitude Change
10
mV
VOS
Offset Voltage
1.3
V
Δ VOS
VOS Magnitude Change
10
mV
NOTE: Please refer to Parameter Measurement Information for output information.
TABLE 3E. LVDS DC CHARACTERISTICS, VDD = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VOD
Differential Output Voltage
Test Conditions
Minimum
Typical
Maximum
Units
400
mV
Δ VOD
VOD Magnitude Change
10
mV
VOS
Offset Voltage
1.2
V
Δ VOS
VOS Magnitude Change
10
mV
NOTE: Please refer to Parameter Measurement Information for output information.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Maximum
Units
34
MHz
Fundamental
Frequency
24.5
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
100
µW
Maximum
Units
170
MHz
Drive Level
TABLE 5A. AC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
Output Frequency
t jit(Ø)
tR / tF
RMS Phase Jitter ( Random);
NOTE 1
Output Rise/Fall Time
Test Conditions
Minimum
Typical
122.5
125MHz @ Integration Range:
1.875MHz - 20MHz
133.33MHz @ Integration Range:
1.875MHz - 20MHz
166.66MHz @ Integration Range:
1.875MHz - 20MHz
20% to 80%
o dc
Output Duty Cycle
NOTE 1: Please refer to the Phase Noise Plots following this section.
0.32
ps
TBD
ps
TBD
ps
300
ps
50
%
TABLE 5B. AC CHARACTERISTICS, VDD = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
Output Frequency
t jit(Ø)
tR / tF
RMS Phase Jitter ( Random);
NOTE 1
Output Rise/Fall Time
Test Conditions
Typical
122.5
125MHz @ Integration Range:
1.875MHz - 20MHz
133.33MHz @ Integration Range:
1.875MHz - 20MHz
166.66MHz @ Integration Range:
1.875MHz - 20MHz
20% to 80%
o dc
Output Duty Cycle
NOTE 1: Please refer to the Phase Noise Plots following this section.
IDT ™ / ICS™ LVDS CLOCK GENERATOR
Minimum
4
Maximum
Units
170
MHz
0.31
ps
TBD
ps
TBD
ps
320
ps
50
%
ICS844021BGI-01 REV. C SEPTEMBER 27, 2007
ICS844021I-01
FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR
PRELIMINARY
➤
TYPICAL PHASE NOISE AT 125MHZ @ 3.3V
125MHz
NOISE POWER dBc
Hz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.32ps (typical)
Ethernet Filter
Raw Phase Noise Data
➤
➤
Phase Noise Result by adding
Ethernet Filter to raw data
OFFSET FREQUENCY (HZ)
➤
TYPICAL PHASE NOISE AT 125MHZ @ 2.5V
125MHz
Ethernet Filter
Raw Phase Noise Data
➤
➤
NOISE POWER dBc
Hz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.32ps (typical)
Phase Noise Result by adding
Ethernet Filter to raw data
OFFSET FREQUENCY (HZ)
IDT ™ / ICS™ LVDS CLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR
PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
SCOPE
SCOPE
Qx
VDD
3.3V±5%
POWER SUPPLY
+ Float GND –
VDDA
VDD
2.5V±5%
POWER SUPPLY
+ Float GND –
LVDS
Qx
VDDA
LVDS
nQx
nQx
LVDS 3.3V OUTPUT LOAD AC TEST CIRCUIT
LVDS 2.5V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
Noise Power
nQ
Q
t PW
t
Phase Noise Mask
odc =
f1
Offset Frequency
PERIOD
t PW
x 100%
t PERIOD
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VVDD
DD
out
80%
DC Input
VOD
Clock
Outputs
LVDS
➤
80%
➤
20%
20%
out
tF
tR
VOS/Δ VOS
➤
OFFSET VOLTAGE SETUP
OUTPUT RISE/FALL TIME
VDD
V
DD
➤
out
➤
LVDS
100
VOD/Δ VOD
out
➤
DC Input
DIFFERENTIAL OUTPUT VOLTAGE SETUP
IDT ™ / ICS™ LVDS CLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR
PRELIMINARY
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS844021I-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD and VDDA should
be individually connected to the power supply plane through
vias, and bypass capacitors should be used for each pin.
To achieve optimum jitter performance, power supply isolation
is required. Figure 1 illustrates how a 10Ω resistor along with
a 10μF and a .01μF bypass capacitor should be connected to
each VDDA pin.
3.3V or 2.5V
VDD
.01μF
10Ω
VDDA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
resonant crystal and were chosen to minimize the ppm error.
The optimum C1 and C2 values can be slightly adjusted for
different board layouts.
The ICS844021I-01 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 25MHz, 18pF parallel
XTAL_OUT
C1
33p
X1
18pF Parallel Crystal
XTAL_IN
C2
27p
FIGURE 2. CRYSTAL INPUt INTERFACE
IDT ™ / ICS™ LVDS CLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR
PRELIMINARY
LVCMOS TO XTAL INTERFACE
series resistance (Rs) equals the transmission line impedance.
In addition, matched termination at the crystal input will
attenuate the signal in half. This can be done in one of two
ways. First, R1 and R2 in parallel should equal the transmission
line impedance. For most 50Ω applications, R1 and R2 can be
100Ω. This can also be accomplished by removing R1 and
making R2 50Ω.
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram
is shown in Figure 3. The XTAL_OUT pin can be left floating.
The input edge rate can be as slow as 10ns. For LVCMOS
inputs, it is recommended that the amplitude be reduced from
full swing to half swing in order to prevent signal interference
with the power rail and to reduce noise. This configuration
requires that the output impedance of the driver (Ro) plus the
VDD
VDD
R1
Ro
.1uf
Rs
Zo = 50
Zo = Ro + Rs
XTAL_IN
R2
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER
TO
XTAL INPUT INTERFACE
3.3V, 2.5V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4 In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near
the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the
unused outputs.
3.3V or 2.5V
VDD
LVDS
+
R1
100
-
100 Ω Differential Transmission
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
IDT ™ / ICS™ LVDS CLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR
PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS844021I-01
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS844021I-01 is the sum of the core power plus the analog plus the power dissipated in the
load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (55mA + 8mA) = 218.3mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air
flow and a multi-layer board, the appropriate value is 129.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.218W * 129.5°C/W = 113.2°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and
the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA
FOR
8-LEAD TSSOP, FORCED CONVECTION
θJA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards
IDT ™ / ICS™ LVDS CLOCK GENERATOR
129.5°C/W
9
1
2.5
125.5°C/W
123.5°C/W
ICS844021BGI-01 REV. C SEPTEMBER 27, 2007
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR
PRELIMINARY
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
FOR
8 LEAD TSSOP
θJA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards
129.5°C/W
1
2.5
125.5°C/W
123.5°C/W
TRANSISTOR COUNT
The transistor count for ICS844021I-01 is: 2533
IDT ™ / ICS™ LVDS CLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR
PACKAGE OUTLINE - G SUFFIX
FOR
PRELIMINARY
8 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
SYMBOL
Millimeters
Minimum
N
A
Maximum
8
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
2.90
3.10
E
E1
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT ™ / ICS™ LVDS CLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR
PRELIMINARY
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS844021BGI-01
2BI01
8 lead TSSOP
tube
-40°C to 85°C
ICS844021BGI-01T
2BI01
8 lead TSSOP
2500 tape & reel
-40°C to 85°C
ICS844021BGI-01LF
BI01L
8 lead "Lead-Free" TSSOP
tube
-40°C to 85°C
ICS844021BGI-01LFT
BI01L
8 lead "Lead-Free" TSSOP
2500 tape & reel
-40°C to 85°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional
processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
IDT ™ / ICS™ LVDS CLOCK GENERATOR
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ICS844021I-01
FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR
PRELIMINARY
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
For Tech Support
800-345-7015
408-284-8200
Fax: 408-284-2775
[email protected]
480-763-2056
Corporate Headquarters
Asia Pacific and Japan
Europe
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
+408 284 8200 (outside U.S.)
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
+65 6 887 5505
IDT Europe, Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU
England
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
© 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA