PRELIMINARY Integrated Circuit Systems, Inc. ICS844252-04 FEMTOCLOCKS™ CRYSTAL-TOLVDS CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS844252-04 is a 10Gb/12Gb Ethernet Clock Generator and a member of the HiPerClockS™ HiPerClocks TM family of high perfor mance devices from ICS. The ICS844252-04 can synthesize 10 Gigabit Ethernet and 12 Gigabit Ethernet with a 25MHz crystal. It can also generate SATA and 10Gb Fibre Channel reference clock frequencies with the appropriate choice of crystals. The ICS844252-04 has excellent phase jitter performance and is packaged in a small 16-pin TSSOP, making it ideal for use in systems with limited board space. • Two differential LVDS outputs ICS • Crystal oscillator interface designed for 18pF parallel resonant crystals • Crystal input frequency range: 19.33MHz - 30MHz • Output frequency range: 145MHz - 187.5MHz • VCO frequency range: 580MHz - 750MHz • RMS phase jitter at 156.25MHz (1.875MHz - 20MHz): 0.36ps (typical) • 3.3V operating supply • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request • Available in both standard and lead-free compliant packages CONFIGURATION TABLE 25MHZ CRYSTAL WITH Crystal Frequency (MHz) 25 Feedback Divide 30 25 25 CONFIGURATION TABLE Crystal Frequency (MHz) 20 WITH Inputs VCO Frequency (MHz) 750 Application 4 187.5 12 Gigabit Ethernet 4 156.25 10 Gigabit Ethernet 625 SELECTABLE CRYSTALS Inputs Feedback VCO Frequency Divide (MHz) 30 600 21.25 N Output Divide Output Frequency (MHz) 30 N Output Divide 637.5 Output Frequency (MHz) 4 150 4 159.375 SATA 24 25 600 4 150 25.5 25 637.5 4 159.375 30 25 750 4 187.5 nPLL_SEL REF_CLK Pulldown 12 Gigabit Ethernet D Q LE 1 XTAL_IN OSC 0 1 Phase Detector DIV. N ÷4 VCO 580MHz-750MHz Q1 nQ1 Pulldown 0 = ÷25 (default) 1 = ÷30 FREQ_SEL Q0 nQ0 nQ1 Q1 VDDO OE nPLL_SEL VDDO Q0 nQ0 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 XTAL_IN XTAL_OUT GND REF_CLK CLK_SEL VDD VDDA FREQ_SEL 0 XTAL_OUT CLK_SEL 10 Gigabit Fibre Channel PIN ASSIGNMENT Pullup Pulldown 10 Gigabit Fibre Channel SATA BLOCK DIAGRAM OE Application ICS844252-04 16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View Pulldown The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 844252AG-04 www.icst.com/products/hiperclocks.html REV. A JANUARY 26, 2006 1 PRELIMINARY Integrated Circuit Systems, Inc. ICS844252-04 FEMTOCLOCKS™ CRYSTAL-TOLVDS CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name 1, 2 nQ1, Q1 Output Type 3, 6 VDDO Power 4 OE Input 5 nPLL_SEL Input 7, 8 Q0, nQ0 Output 9 FREQ_SEL Input 10 VDDA Power 11 VDD Power 12 CLK_SEL Input 13 REF_CLK Input Description Differential clock outputs. LVDS interface levels. Output supply pins. Output enable. When HIGH, clock outputs follow clock input. When LOW, Qx outputs are forced low, nQx outputs are forced high. Pullup LVCMOS/LVTTL interface levels. Selects between the PLL and reference clock as input to the divider. Pulldown When Low, selects PLL. When High, selects reference clock. LVCMOS/LVTTL interface levels. Differential clock outputs. LVDS interface levels. Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. Analog supply pin. Core supply pin. Clock select input. When Low, selects cr ystal inputs. When High, Pulldown selects REF_CLK. LVCMOS/LVTTL interface levels. Pulldown Reference clock input. LVCMOS/LVTTL interface levels. 14 GND Power Power supply ground. Cr ystal oscillator interface. XTAL_IN is the input, XTAL_OUT, 15, 16 Input XTAL_OUT is the output. XTAL_IN NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characterristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ 844252AG-04 Test Conditions Minimum www.icst.com/products/hiperclocks.html 2 Typical Maximum Units REV. A JANUARY 26, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS844252-04 FEMTOCLOCKS™ CRYSTAL-TOLVDS CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 89°C/W (0 lfpm) -65°C to 150°C Storage Temperature, TSTG TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 70 mA IDDA Analog Supply Current 11 mA IDDO Output Supply Current 40 mA TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH IIL Input High Current Input Low Current Test Conditions REF_CLK, CLK_SEL, FREQ_SEL, nPLL_SEL OE REF_CLK, CLK_SEL, FREQ_SEL, nPLL_SEL OE Minimum Maximum Units 2 Typical VDD + 0.3 V -0.3 0.8 V VDD = VIN = 3.465V 150 µA VDD = VIN = 3.465V 5 µA VDD = 3.465V, VIN = 0V -5 µA VDD = 3.465V, VIN = 0V -150 µA TABLE 3C. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VOD Differential Output Voltage 400 mV Δ VOD VOD Magnitude Change 40 mV VOS Offset Voltage 1.25 V Δ VOS VOS Magnitude Change 50 mV 844252AG-04 Test Conditions Minimum www.icst.com/products/hiperclocks.html 3 Typical Maximum Units REV. A JANUARY 26, 2006 PRELIMINARY ICS844252-04 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVDS CLOCK GENERATOR TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Maximum Units 30 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW Mode of Oscillation Typical Fundamental Frequency 19.33 TABLE 5. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fOUT Output Frequency t sk(o) Output Skew; NOTE 1, 2 t jit(Ø) tR / tF RMS Phase Jitter (Random); NOTE 3 Output Rise/Fall Time Test Conditions Minimum Typical 145 156.25MHz @ Integration Range: 1.875MHz - 20MHz 159.375MHz @ Integration Range: 1.875MHz - 20MHz 187.5MHz @ Integration Range: 1.875MHz - 20MHz 20% to 80% www.icst.com/products/hiperclocks.html 4 Units 187.5 MH z TBD ps 0.36 ps 0.38 ps 0.38 ps 375 ps odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plots following this section. 844252AG-04 Maximum % REV. A JANUARY 26, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS844252-04 FEMTOCLOCKS™ CRYSTAL-TOLVDS CLOCK GENERATOR TYPICAL PHASE NOISE AT 156.25MHZ ➤ 0 -10 -20 Gb Ethernet Filter -50 156.25MHz -60 -70 RMS Phase Noise Jitter 1.875MHz to 20MHz = 0.36ps (typical) -80 -90 Raw Phase Noise Data -100 -110 ➤ NOISE POWER dBc Hz -30 -40 -120 -130 ➤ -140 -150 -160 Phase Noise Result by adding a Gb Ethernet Filter Filter to raw data -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) 844252AG-04 www.icst.com/products/hiperclocks.html 5 REV. A JANUARY 26, 2006 PRELIMINARY ICS844252-04 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVDS CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION Qx 3.3V±5% POWER SUPPLY + Float GND - Noise Power Phase Noise Plot SCOPE LVDS Phase Noise Mask nQx f1 Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot 3.3V OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTER nQx nQ0, nQ1 Qx Q0, Q1 t PW t nQy Qy odc = tsk(o) PERIOD t PW x 100% t PERIOD OUTPUT SKEW OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD VDD out 80% ➤ DC Input 20% 20% tR LVDS tF 100 VOD/Δ VOD out OUTPUT RISE/FALL TIME ➤ VSW I N G Clock Outputs ➤ 80% DIFFERENTIAL OUTPUT VOLTAGE SETUP VDD out LVDS ➤ DC Input ➤ out VOS/Δ VOS ➤ OFFSET VOLTAGE SETUP 844252AG-04 www.icst.com/products/hiperclocks.html 6 REV. A JANUARY 26, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS844252-04 FEMTOCLOCKS™ CRYSTAL-TOLVDS CLOCK GENERATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS844252-04 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, V DDA, and V DDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VCCA pin. The 10Ω resistor can also be replaced by a ferrite bead. 3.3V VDD .01μF 10Ω VDDA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. The ICS844252-04 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF XTAL_OUT C1 22p X1 18pF Parallel Crystal XTAL_IN C2 22p Figure 2. CRYSTAL INPUt INTERFACE 844252AG-04 www.icst.com/products/hiperclocks.html 7 REV. A JANUARY 26, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS844252-04 FEMTOCLOCKS™ CRYSTAL-TOLVDS CLOCK GENERATOR RECOMMENDATIONS FOR UNUSED OUTPUT PINS OUTPUTS: LVDS All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, we recommend that there is no trace attached. 3.3V LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 3. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 3.3V 3.3V LVDS + R1 100 - 100 Ohm Differential Transmission Line FIGURE 3. TYPICAL LVDS DRIVER TERMINATION 844252AG-04 www.icst.com/products/hiperclocks.html 8 REV. A JANUARY 26, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS844252-04 FEMTOCLOCKS™ CRYSTAL-TOLVDS CLOCK GENERATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS844252-04. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS844252-04 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. • • Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 70mA = 242.6mW Power (output)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 40mA = 138.6mW Total Power_MAX = 242.6mW + 138.6mW = 381.2mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 81.8°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.381W * 81.8°C/W = 101°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 16-LEADTSSOP, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1°C/W 89.0°C/W 200 118.2°C/W 81.8°C/W 500 106.8°C/W 78.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 844252AG-04 www.icst.com/products/hiperclocks.html 9 REV. A JANUARY 26, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS844252-04 FEMTOCLOCKS™ CRYSTAL-TOLVDS CLOCK GENERATOR RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP θJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1°C/W 89.0°C/W 200 118.2°C/W 81.8°C/W 500 106.8°C/W 78.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS844252-04 is: 2234 844252AG-04 www.icst.com/products/hiperclocks.html 10 REV. A JANUARY 26, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS844252-04 FEMTOCLOCKS™ CRYSTAL-TOLVDS CLOCK GENERATOR PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N Maximum 16 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 E E1 5.10 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 α 0° 8° aaa -- 0.10 0.75 Reference Document: JEDEC Publication 95, MO-153 844252AG-04 www.icst.com/products/hiperclocks.html 11 REV. A JANUARY 26, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS844252-04 FEMTOCLOCKS™ CRYSTAL-TOLVDS CLOCK GENERATOR TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS844252AG-04 44251A04 16 Lead TSSOP tube 0°C to 70°C ICS844252AG-04T 44251A04 16 Lead TSSOP 2500 tape & reel 0°C to 70°C ICS844252AG-04LF TBD 16 Lead "Lead-Free" TSSOP tube 0°C to 70°C ICS844252AG-04LFT TBD 16 Lead "Lead-Free" TSSOP 2500 tape & reel 0°C to 70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 844252AG-04 www.icst.com/products/hiperclocks.html 12 REV. A JANUARY 26, 2006