ICS8705 Integrated Circuit Systems, Inc. ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS8705 is a highly versatile 1:8 Differential-to-LVCMOS/LVTTL Clock Generator and a HiPerClockS™ member of the HiPerClockS™family of High Performance Clock Solutions from ICS. The ICS8705 has two selectable clock inputs. The CLK1, nCLK1 pair can accept most standard differential input levels. The single ended CLK0 input accepts LVCMOS or LVTTL input levels.The ICS8705 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider and has an input and output frequency range of 15.625MHz to 250MHz. The reference divider, feedback divider and output divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve “zero delay” between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers. • 8 LVCMOS/LVTTL outputs, 7Ω typical output impedance ICS • Selectable CLK1, nCLK1 or LVCMOS/LVTTL clock inputs • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • CLK0 input accepts LVCMOS or LVTTL input levels • Output frequency range: 15.625MHz to 250MHz • Input frequency range: 15.625MHz to 250MHz • VCO range: 250MHz to 500MHz • External feedback for “zero delay” clock regeneration with configurable frequencies • Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 • Fully integrated PLL • Cycle-to-cycle jitter: 45ps (maximum) • Output skew: CLK0, 65ps (maximum) CLK1, nCLK1, 55ps (maximum) • Static Phase Offset: 25 ±125ps (maximum), CLK0 • Full 3.3V or 2.5V operating supply • Lead-Free package available • Industrial temperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT Q0 GND Q2 32 31 30 29 28 27 26 25 PLL Q3 Q4 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 Q5 Q6 Q7 Q6 1 Q7 Q1 CLK_SEL FB_IN VDDO 0 0 1 SEL3 CLK1 nCLK1 VDDA CLK0 VDD ÷2, ÷4, ÷8, ÷16, ÷32, ÷64, ÷128 PLL_SEL PLL_SEL SEL0 1 24 VDDO SEL1 2 23 Q5 CLK0 3 22 GND nc 4 21 Q4 CLK1 5 20 VDDO nCLK1 6 19 Q3 CLK_SEL 7 18 GND MR 8 17 Q2 ICS8705 9 10 11 12 13 14 15 16 SEL0 VDDO Q1 GND Q0 VDDO 32-Lead LQFP 7mm x 7mm x 1.4 mm Y Package Top View SEL3 MR 8705BY SEL2 SEL2 FB_IN VDD SEL1 www.icst.com/products/hiperclocks.html 1 REV. G JUNE 16, 2004 ICS8705 Integrated Circuit Systems, Inc. ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name SEL0, SEL1, SEL2 CLK0 1, 2, 11 3 Type Input Description Determines output divider values in Table 3. Pulldown LVCMOS/LVTTL interface levels. Pulldown Clock input. LVCMOS/LVTTL interface levels. Pulldown Non-inver ting differential clock input. Input 4 nc 5 CLK1 Input 6 nCLK1 Input 7 CLK_SEL Input 8 MR Input 9, 32 VDD Power 10 FB_IN Input VDDO Power Output supply pins. Output Clock output. 7Ω typical output impedance. LVCMOS/LVTTL interface levels. 12, 16, 20, 24, 28 13, 15, 17, 19, 21, 23, 25, 27 14, 18, 22, 26 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 GND No connect. Pullup Inver ting differential clock input. Clock select input. When HIGH, selects differential CLK1, nCLK1. Pulldown When LOW, selects LVCMOS CLK0. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are Pulldown reset causing the outputs to go low. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Core supply pins. LVCMOS/LVTTL feedback input to phase detector for regenerating Pulldown clocks with "zero delay". Connect to one of the outputs. LVCMOS/LVTTL interface levels. Power Power supply ground. Determines output divider values in Table 3. 29 SEL3 Input Pulldown LVCMOS/LVTTL interface levels. 30 VDDA Power Analog supply pin. Selects between the PLL and reference clock as input to the dividers. 31 PLL_SEL Input Pullup When LOW, selects the reference clock (PLL Bypass). When HIGH, selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN RPULLUP RPULLDOWN CPD Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance ROUT 8705BY Test Conditions Minimum VDD, VDDO, VDDA = 3.465V www.icst.com/products/hiperclocks.html 2 Typical Maximum Units 4 51 51 pF KΩ KΩ 23 pF 7 Ω REV. G JUNE 16, 2004 ICS8705 Integrated Circuit Systems, Inc. ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 3A. PLL ENABLE FUNCTION TABLE SEL3 SEL2 SEL1 SEL0 Reference Frequency Range (MHz) Outputs PLL_SEL = 1 PLL Enable Mode Q0:Q7 0 0 0 0 125 - 250 ÷1 Inputs 0 0 0 1 62.5 - 125 ÷1 0 0 1 0 31.25 - 62.5 ÷1 0 0 1 1 15.625 -31.25 ÷1 0 1 0 0 125 - 250 ÷2 0 1 0 1 62.5 - 125 ÷2 0 1 1 0 31.25 - 62.5 ÷2 0 1 1 1 125 - 250 ÷4 1 0 0 0 62.5 - 125 ÷4 1 0 0 1 125 - 250 ÷8 1 0 1 0 62.5 - 125 x2 1 0 1 1 31.25 - 62.5 x2 1 1 0 0 15.625 - 31.25 x2 1 1 0 1 31.25 - 62.5 x4 1 1 1 0 15.625 - 31.25 x4 1 1 1 1 15.625 - 31.25 x8 TABLE 3B. PLL BYPASS FUNCTION TABLE SEL3 SEL2 SEL1 S E L0 Outputs PLL_SEL = 0 PLL Bypass Mode Q0:Q7 0 0 0 0 ÷8 0 0 0 1 ÷8 Inputs 8705BY 0 0 1 0 ÷8 0 0 1 1 ÷ 16 0 1 0 0 ÷ 16 0 1 0 1 ÷ 16 0 1 1 0 ÷ 32 0 1 1 1 ÷ 32 1 0 0 0 ÷ 64 1 0 0 1 ÷ 128 1 0 1 0 ÷4 1 0 1 1 ÷4 1 1 0 0 ÷8 1 1 0 1 ÷2 1 1 1 0 ÷4 1 1 1 1 ÷2 www.icst.com/products/hiperclocks.html 3 REV. G JUNE 16, 2004 ICS8705 Integrated Circuit Systems, Inc. ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Minimum Typical Maximum Units VDD Core Supply Voltage Test Conditions 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 96 mA IDDA Analog Supply Current 15 mA IDDO Output Supply Current 20 mA Maximum Units 2 VDD + 0.3 V 2 VDD + 0.3 V -0.3 0.8 V -0.3 1.3 V VDD = VIN = 3.465V 150 µA VDD = VIN = 3.465V 5 µA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage Input High Current Test Conditions PLL_SEL, CLK_SEL, SEL0, SEL1, SEL2, SEL3, FB_IN, MR CLK0 PLL_SEL, CLK_SEL, SEL0, SEL1, SEL2, SEL3, FB_IN, MR CLK0 CLK0, CLK_SEL MR, FB_IN, SEL0, SEL1, SEL2, SEL3 PLL_SEL CLK0, CLK_SEL MR, FB_IN, SEL0, SEL1, SEL2, SEL3 PLL_SEL IIL Input Low Current VOH Output High Voltage; NOTE 1 Minimum Typical VDD = 3.465V, VIN = 0V -5 µA VDD = 3.465V, VIN = 0V -150 µA 2.6 V Output Low Voltage; NOTE 1 VOL NOTE 1: Outputs terminated with 50Ω to VDDO/2. In the Parameter Measurement Information Section, see "3.3V Output Load Test Circuit". 8705BY www.icst.com/products/hiperclocks.html 4 0.5 V REV. G JUNE 16, 2004 ICS8705 Integrated Circuit Systems, Inc. ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter IIH Input High Current IIL Input Low Current Maximum Units CLK1 VDD = VIN = 3.465V Test Conditions Minimum Typical 150 µA nCLK1 VDD = VIN = 3.465V 5 µA CLK1 VDD = 3.465V, VIN = 0V -5 µA nCLK1 VDD = 3.465V, VIN = 0V -150 µA VPP Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; GND + 0.5 VCMR NOTE 1, 2 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK1, nCLK1 is VDD + 0.3V. 1.3 V VDD - 0.85 V TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fMAX Output Frequency tpLH Propagation Delay, Low-to-High; NOTE 1 Test Conditions CLK0 CLK1, nCLK1 CLK0 t(Ø) Static Phase Offset; NOTE 2, 4 CLK1, nCLK1 CLK0 CLK1, nCLK1 CLK0 tsk(o) Output Skew; NOTE 3, 4 tjit(cc) Cycle-to-Cycle Jitter; NOTE 4 tL PLL Lock Time tR / tF Output Rise/Fall Time CLK1, nCLK1 PLL_SEL = 0V, f ≤ 250MHz, Qx ÷ 2 PLL_SEL = 0V, f ≤ 250MHz, Qx ÷ 2 PLL_SEL = 3.3V, fREF ≤ 200MHz, Qx ÷ 1 PLL_SEL = 3.3V, fREF ≤ 167MHz, Qx ÷ 1 PLL_SEL = 3.3V, fREF = 200MHz, Qx ÷ 1 PLL_SEL = 3.3V, fREF = 66MHz, Qx * 2 PLL_SEL = 3.3V, fREF = 66MHz, Qx * 2 PLL_SEL = 0V Minimum Typical Maximum Units 15.625 250 MHz 5 7 ns 5 7.3 ns -100 25 150 ps -15 + 135 285 ps -50 +100 250 ps -150 -25 100 ps 0 150 300 ps 65 ps PLL_SEL = 0V 55 ps fOUT > 40MHz 45 ps 1 mS 950 ps 43 57 PLL x 4 mode, fin = 45MHz, 47 53 fOUT = 180MHz All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output at VDDO/2. NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. % odc 8705BY 400 Output Duty Cycle www.icst.com/products/hiperclocks.html 5 % REV. G JUNE 16, 2004 ICS8705 Integrated Circuit Systems, Inc. ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Minimum Typical Maximum Units VDD Core Supply Voltage Test Conditions 2.375 2.5 2.625 V VDDA Analog Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 90 mA IDDA Analog Supply Current 15 mA IDDO Output Supply Current 20 mA Maximum Units 2 VDD + 0.3 V 2 VDD + 0.3 V -0.3 0.8 V -0.3 1.3 V VDD = VIN = 2.625V 150 µA VDD = VIN = 2.625V 5 µA TABLE 4E. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL IIH IIL VOH Input Low Voltage Input High Current Input Low Current Test Conditions PLL_SEL, CLK_SEL, SEL0, SEL1, SEL2, SEL3, FB_IN, MR CLK0 PLL_SEL, CLK_SEL, SEL0, SEL1, SEL2, SEL3, FB_IN, MR CLK0 CLK0, CLK_SEL MR, FB_IN, SEL0, SEL1, SEL2, SEL3 PLL_SEL CLK0, CLK_SEL MR, FB_IN, SEL0, SEL1, SEL2, SEL3 PLL_SEL Minimum Typical VDD = 2.625V, VIN = 0V -5 µA VDD = 2.625V, VIN = 0V -150 µA Output High Voltage; NOTE 1 1.8 V Output Low Voltage; NOTE 1 VOL NOTE 1: Outputs terminated with 50Ω to VDDO/2. In the Parameter Measurement Information section, see "2.5V Output Load Test Circuit" figure. 0.5 V TABLE 4F. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter IIH Input High Current IIL Input Low Current Maximum Units CLK1 VDD = VIN = 2.625V Test Conditions Minimum Typical 150 µA nCLK1 VDD = VIN = 2.625V 5 µA CLK1 VDD = 2.625V, VIN = 0V -5 µA nCLK1 VDD = 2.625V, VIN = 0V -150 µA V PP Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; GND + 0.5 VCMR NOTE 1, 2 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK1, nCLK1 is VDD + 0.3V. 8705BY www.icst.com/products/hiperclocks.html 6 1.3 V VDD - 0.85 V REV. G JUNE 16, 2004 ICS8705 Integrated Circuit Systems, Inc. ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter fMAX Output Frequency tpLH Propagation Delay, Low-to-High; NOTE 1 Test Conditions CLK0 CLK1, nCLK1 CLK0 t(Ø) Static Phase Offset; NOTE 2, 4 CLK1, nCLK1 CLK0 CLK1, nCLK1 CLK0 tsk(o) Output Skew; NOTE 3, 4 tjit(cc) Cycle-to-Cycle Jitter; NOTE 4 t jit(θ) Phase Jitter; NOTE 4, 5 tL PLL Lock Time tR / tF Output Rise/Fall Time CLK1, nCLK1 PLL_SEL = 0V, f ≤ 250MHz, Qx ÷ 2 PLL_SEL = 0V, f ≤ 250MHz, Qx ÷ 2 PLL_SEL = 2.5V, fREF ≤ 200MHz, Qx ÷ 1 PLL_SEL = 2.5V, fREF = 133MHz, Qx ÷ 1 PLL_SEL = 2.5V, fREF = 200MHz, Qx ÷ 1 PLL_SEL = 2.5V, fREF = 66MHz, Qx * 2 PLL_SEL = 2.5V, fREF = 66MHz, Qx * 2 PLL_SEL = 0V Minimum Maximum Units 15.625 Typical 250 MHz 5 7 ns 5 7.3 ns -250 25 200 ps -50 100 250 ps -100 +100 300 ps -150 -25 100 ps 0 150 300 ps 65 ps PLL_SEL = 0V 55 ps fOUT > 40MHz PLL_SEL = 2.5V, fREF = 66MHz, Qx * 2 45 ps ±50 ps 1 mS 950 ps 43 57 PLL x 4 mode, fin = 45MHz, 45 55 fOUT = 180MHz All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output at VDDO/2. NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Phase jitter is dependent on the input source used. % odc 8705BY 400 Output Duty Cycle www.icst.com/products/hiperclocks.html 7 % REV. G JUNE 16, 2004 ICS8705 Integrated Circuit Systems, Inc. ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 1.65V±5% 1.25V±5% SCOPE VDD, VDDA, VDDO Qx LVCMOS SCOPE VDD, VDDA, VDDO Qx LVCMOS GND GND -1.165V±5% -1.25V±5% 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT V DD V DDO Qx nCLK V V Cross Points PP 2 CMR V CLK DDO Qy 2 t sk(o) GND DIFFERENTIAL INPUT LEVEL OUTPUT SKEW V V DDO Q0:Q7 V DDO 2 DDO 2 n ➤ tcycle ➤ 80% 80% tR tF 2 tcycle n+1 ➤ Clock Outputs 20% 20% ➤ t jit(cc) = tcycle n –tcycle n+1 1000 Cycles CYCLE-TO-CYCLE JITTER 8705BY OUTPUT RISE/FALL TIME www.icst.com/products/hiperclocks.html 8 REV. G JUNE 16, 2004 ICS8705 Integrated Circuit Systems, Inc. ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR nCLK1 VOH CLK1 VOL VDD 2 CLK0 VOH VDDO nCLK1 2 VOL FB_IN CLK1 ➤ ➤ t (Ø) t jit(Ø) = t (Ø) — t (Ø) mean = Phase Jitter t (Ø) mean = Static Phase Offset (where t (Ø) is any random sample, and t (Ø) mean is the average of the sampled cycles measured on controlled edges) ➤ PHASE JITTER & STATIC PHASE OFFSET Q0:Q7 VDDO 2 Q0:Q7 t PD ➤ PROPAGATION DELAY VDDO VDDO VDDO 2 2 2 t PW t PERIOD odc = t PW t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 8705BY www.icst.com/products/hiperclocks.html 9 REV. G JUNE 16, 2004 ICS8705 Integrated Circuit Systems, Inc. ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8705 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a .01µF bypass capacitor should be connected to each VDDA. 3.3V VDD .01µF 10Ω VDDA .01µF 10 µF FIGURE 1. POWER SUPPLY FILTERING WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 8705BY www.icst.com/products/hiperclocks.html 10 REV. G JUNE 16, 2004 ICS8705 Integrated Circuit Systems, Inc. ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER BY FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 BY R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input Receiv er R2 84 FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER 8705BY nCLK Zo = 50 Ohm BY FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER www.icst.com/products/hiperclocks.html 11 BY REV. G JUNE 16, 2004 ICS8705 Integrated Circuit Systems, Inc. ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR LAYOUT GUIDELINE VDD R7 10 - 15 depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P.C. board. R1 SEL3 PLL_SEL The schematic of the ICS8705 layout example is shown in Figure 4A. The ICS8705 recommended PCB board layout for this example is shown in Figure 4B. This layout example is used as a general guideline. The layout in the actual system will Zo = 50 43 VDDA VDD C11 0.01u C16 10u 32 31 30 29 28 27 26 25 VDD 43 Driv er_LVCMOS R5 1K 1 2 3 4 5 6 7 8 SEL0 SEL1 CLK0 nc CLK1 nCLK1 CLK_SEL MR R4 1K ICS8705 VDD=3.3V or 2.5V 24 23 22 21 20 19 18 17 VDDO Q5 GND Q4 VDDO Q3 GND Q2 VDD FB_IN SEL2 VDDO Q0 GND Q1 VDDO R4 SEL0 SEL1 Zo = 50 9 10 11 12 13 14 15 16 Ro ~ 7 Ohm VDD PLL_SEL VDDA SEL3 VDDO Q7 GND Q6 U1 Logic Input Pin Examples RU1 1K Set Logic Input to '0' VDD Zo = 50 SEL2 Set Logic Input to '1' VDD R2 43 RU2 Not Install To Logic Input pins RD1 Not Install To Logic Input pins RD2 1K (U1-9) VDD C2 0.1uF (U1-12) C3 0.1uF (U1-16) (U1-20) C4 0.1uF C5 0.1uF (U1-24) (U1-28) C6 0.1uF (U1-32) C1 0.1uF C7 0.1uF FIGURE 4A. ICS8705 LVCMOS CLOCK GENERATOR SCHEMATIC EXAMPLE 8705BY www.icst.com/products/hiperclocks.html 12 REV. G JUNE 16, 2004 ICS8705 Integrated Circuit Systems, Inc. ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. The following component footprints are used in this layout example: All the resistors and capacitors are size 0603. POWER AND GROUNDING • The differential 50Ω output traces should have same length. Place the decoupling capacitors as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. • Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. • Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. • To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. The RC filter consisting of R7, C11, and C16 should be placed as close to the VDDA pin as possible. CLOCK TRACES AND TERMINATION Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the • Make sure no other signal traces are routed between the clock trace pair. • The series termination resistors should be located as close to the driver pins as possible. GND 50 Ohm Trace R7 C16 C11 C1 VDDA VDD R1 VIA Other signals C7 Pin 1 C6 C5 U1 C4 C2 C3 R2 50 Ohm Trace FIGURE 4B. PCB BOARD LAYOUT FOR ICS8705 8705BY www.icst.com/products/hiperclocks.html 13 REV. G JUNE 16, 2004 ICS8705 Integrated Circuit Systems, Inc. ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8705 is: 3126 8705BY www.icst.com/products/hiperclocks.html 14 REV. G JUNE 16, 2004 ICS8705 Integrated Circuit Systems, Inc. ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP TABLE 7. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. 0.80 BASIC e L 0.45 0.60 0.75 θ 0° -- 7° ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 8705BY www.icst.com/products/hiperclocks.html 15 REV. G JUNE 16, 2004 Integrated Circuit Systems, Inc. ICS8705 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS8705BY ICS8705BY 32 Lead LQFP 250 per tray 0°C to 70°C ICS8705BYT ICS8705BY 32 Lead LQFP on Tape and Reel 1000 0°C to 70°C ICS8705BYLF ICS8705BYLF 32 Lead "Lead Free" LQFP 250 per tray 0°C to 70°C ICS8705BYLFT ICS8705BYLF 32 Lead "Lead Free" LQFP on Tape and Reel 1000 0°C to 70°C The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8705BY www.icst.com/products/hiperclocks.html 16 REV. G JUNE 16, 2004 Integrated Circuit Systems, Inc. ICS8705 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR REVISION HISTORY SHEET Rev Table Page T3A 1 3 Updated Block Diagram PLL Enable Function Table - revised the Reference Frequency Range column T5A 5 3.3V AC Characteristics Table - updated the Output Frequency row from 350MHz Max. to 275MHz Max. T4D:T4F; T5B T3A 6, 7 3 T5A 5 A B C T5B 7 C T1 2 C T2 2 C T1 2 C T1 D E 2 T1, T4A, T4D 8 2, 4, 6 T5A, T5B 5, 7 1 2 T5A & T5B T5A & T5B 5&7 5&7 F G G 8705BY Date Added 2.5V tables. PLL Enable Function Table - revised the Reference Frequency Range column 3.3V AC Characteristics Table - updated the Output Frequency row from 275MHz Max. to 250MHz Max. 4/4/02 2.5V AC Characteristics Table - updated the Output Frequency row from 275MHz Max. to 250MHz Max. Pin Description Table - revised power pin descriptions. 4/10/02 Pin Characteristics Table - add 23pF (typical) in CPD row. Pin Description Table - Pin# 10 from description, replaced "Connect to pin 10." with "Connect to one of the outputs." Revised CLK0 description and MR description. Revised Output Rise/Fall Time Diagram. Revised description for VDD to read Core supply from Positive supply. AC Characteristics, added another row to "odc" with different test conditions and values. Updated format. Pin Description table - revised MR description. T2 9 2 Replaced Static Phase Offset Diagram with Phase Jitter & SPO Diagram. Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical. 14 Ordering Information Table - added "Lead-Free" par t number www.icst.com/products/hiperclocks.html 17 8/1/02 8/21/02 11/22/02 2/13/03 Throughout datasheet revised title to read "...Differential-to-LVCMOS/LVTTL..." 2.5V AC Characteristics Table - added Phase Jitter spec, and Note 5. 11 Added Differential Clock Input Interface section. 12 & 13 Added Layout Guideline 7/15/02 1/22/03 AC tables - Changed the Static Phase Offset limits for CLK1, nCLK1. AC tables - added Static Phase Offset with "fREF = 66MHz, Qx * 2". 3.3V AC table - corrected typo in SPO parameter to read NOTE 4 from NOTE 7. 7 T6 1/25/02 3/14/02 T5B G G Description of Change 3/14/03 5/15/03 6/6/03 6/16/04 REV. G JUNE 16, 2004