ICS87608I Integrated Circuit Systems, Inc. LOW VOLTAGE/LOW SKEW, 1:8 PCI/PCI-X ZERO DELAY CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS87608I has a selectable REF_CLK or crystal input. The REF_CLK input accepts HiPerClockS™ LVCMOS or LVTTL input levels. The ICS87608I has a fully integrated PLL along with frequency configurable clock and feedback outputs for multiplying and regenerating clocks with “zero delay”. • Fully integrated PLL ICS • 8 LVCMOS/LVTTL outputs, 15Ω typical output impedance • Selectable crystal oscillator interface or LVCMOS/LVTTL REF_IN clock input • Maximum output frequency: 166.67MHz • Maximum crystal input frequency: 38MHz • Maximum REF_IN input frequency: 41.67MHz The ICS87608I is a 1:8 PCI/PCI-X Clock Generator and a member of the HiPerClockSTM family of high performance clock solutions from ICS. The ICS87608I has a selectable REF_CLK or crystal input. The REF_CLK input accepts LVCMOS or LVTTL input levels. The ICS87608I has a fully integrated PLL along with frequency configurable clock and feedback outputs for multiplying and regenerating clocks with “zero delay”. The PLL’s VCO has an operating range of 250MHz-500MHz, allowing this device to be used in a variety of general purpose clocking applications. For PCI/PCI-X applications in particular, the VCO frequency should be set to 400MHz. This can be accomplished by supplying 33.33MHz, 25MHz, 20MHz, or 16.66MHz on the reference clock or crystal input and by selecting ÷12, ÷16, ÷20, or ÷24, respectively as the feedback divide value. The dividers on each of the two output banks can then be independently configured to generate 33.33MHz (÷12), 66.66MHz (÷6), 100MHz (÷4), or 133.33MHz (÷3). • Individual banks with selectable output dividers for generating 33.333MHz, 66.66MHz, 100MHz and 133.333MHz • Separate feedback control for generating PCI / PCI-X frequencies from a 16.66MHz or 20MHz crystal, or 25MHz or 33.33MHz reference frequency • VCO range: 200MHz to 500MHz • Cycle-to-cycle jitter: 120ps (maximum), @ 3.3V • Period jitter, RMS: 20ps (maximum) • Output skew: 250ps (maximum) • Bank skew: 60ps (maximum) • Static phase offset: 160ps ± 160ps • Voltage Supply Modes: VDD (core/inputs), VDDA (analog supply for PLL), VDDOA (output bank A), VDDOB (output bank B, REF_OUT, FB_OUT) The ICS87608I is characterized to operate with its core supply at 3.3V and each bank supply at 3.3V or 2.5V. The ICS87608I is packaged in a small 7x7mm body LQFP, making it ideal for use in space-constrained applications. • Lead-Free package fully RoHS compliant • -40°C to 85°C ambient operating temperature VDDOB PLL_SEL VDDA XTAL1 XTAL2 REF_IN VDDOA XTAL_SEL PIN ASSIGNMENT VDD/VDDA/VDDOA/VDDOB 3.3/3.3/3.3/3.3 3.3/3.3/2.5/3.3 3.3/3.3/3.3/2.5 3.3/3.3/2.5/2.5 32 31 30 29 28 27 26 25 QA0 1 24 QB0 QA1 2 23 QB1 GND 3 22 GND QA2 4 21 QB2 QA3 5 20 QB3 VDDOA 6 MR 7 DIV_SELA0 8 ICS87608I 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y package Top View 19 VDDOB 18 REF_OUT 17 FB_OUT 9 10 11 12 13 14 15 16 GND FB_IN VDD FBDIV_SEL1 FBDIV_SEL0 DIV_SELB1 DIV_SELB0 DIV_SELA1 87608AYI www.icst.com/products/hiperclocks.html 1 REV. B MARCH 11, 2005 ICS87608I Integrated Circuit Systems, Inc. LOW VOLTAGE/LOW SKEW, 1:8 PCI/PCI-X ZERO DELAY CLOCK GENERATOR BLOCK DIAGRAM DIV_SELA0 DIV_SELA1 XTAL_SEL REF_IN 0 0 XTAL1 OSC XTAL2 1 1 ÷3 0 0 QA0 ÷4 0 1 QA1 ÷6 1 0 QA2 ÷12 1 1 QA3 0 0 QB0 0 1 QB1 1 0 QB2 1 1 QB3 PLL FB_IN PLL_SEL D_SELB1 D_SELB0 ÷12 0 0 ÷16 0 1 ÷20 1 0 ÷24 1 1 REF_OUT FB_OUT FBDIV_SEL1 FBDIV_SEL0 MR 87608AYI www.icst.com/products/hiperclocks.html 2 REV. B MARCH 11, 2005 ICS87608I Integrated Circuit Systems, Inc. LOW VOLTAGE/LOW SKEW, 1:8 PCI/PCI-X ZERO DELAY CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number 1, 2, 4, 5 3, 16, 22 Name QA0, QA1, QA2, QA3 GND Output 6, 32 VDDOA Power 7 MR Input 8, 9, 10, 11 12, 13 14 DIV_SELA0, DIV_SELA1, DIV_SELB0, DIV_SELB1 FBDIV_SEL0, FBDIV_SEL1 VDD Power 15 FB_IN Input 17 FB_OUT Output 18 REF_OUT Output Reference clock output. LVCMOS / LVTTL interface levels. 19, 25 20, 21, 23, 24 VDDOB QB3, QB2, QB1, QB0 Power 26 PLL_SEL Input 27 VDDA Power 28 XTAL_SEL Input Output supply pins for Bank B and REF_OUT, FB_OUT outputs. Bank B clock outputs. 15Ω typical output impedance. LVCMOS / LVTTL interface levels. Selects between PLL and bypass mode. When HIGH, selects PLL. When LOW, selects reference clock. LVCMOS / LVTTL interface levels. Analog supply pin. See Applications Note for filtering. Selects between cr ystal oscillator or reference clock as the PLL reference source. Selects XTAL inputs when HIGH. Selects REF_IN when LOW. LVCMOS / LVTTL interface levels. 29, 30 31 Type Description Bank A clock outputs. 15Ω typical output impedance. LVCMOS / LVTTL interface levels. Power supply ground. Power Input Input Output supply pins for Bank A outputs. Active HIGH Master Reset. When logic HIGH, the internal dividers Pulldown are reset causing the outputs go low. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Pulldown Selects divide value for reference clock output and feedback output. LVCMOS / LVTTL interface levels. Core supply pin. Feedback input to phase detector for generating clocks with Pulldown "zero delay". LVCMOS / LVTTL interface levels. Feedback output. Connect to FB_IN. LVCMOS / LVTTL interface levels. Pulldown Output XTAL1, XTAL2 REF_IN Pullup Pullup Input Input Selects divide value for clock outputs as described in Table 3. LVCMOS / LVTTL interface levels. Cr ystal oscillator interface. XTAL1 is the input. XTAL2 is the output. Pulldown Reference clock input. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ CPD Power Dissipation Capacitance (per output); NOTE 1 9 pF 11 pF ROUT Output Impedance 4 VDD, VDDA, VDDOX = 3.465V VDD, VDDA = 3.465V; VDDOX = 2.625V 15 pF Ω VDDOX denotes VDDOA and VDDOB. 87608AYI www.icst.com/products/hiperclocks.html 3 REV. B MARCH 11, 2005 ICS87608I Integrated Circuit Systems, Inc. LOW VOLTAGE/LOW SKEW, 1:8 PCI/PCI-X ZERO DELAY CLOCK GENERATOR TABLE 3A. OUTPUT CONTROL PIN FUNCTION TABLE Inputs Outputs MR QA0:QA3 QB0:QB3, FB_OUT, REF_OUT 1 LOW LOW 0 Active Active TABLE 3C. PLL INPUT FUNCTION TABLE TABLE 3B. OPERATING MODE FUNCTION TABLE Inputs Inputs Operating Mode PLL_SEL XTAL_SEL PLL Input 0 Bypass 0 REF_IN 1 PLL 1 XTAL Oscillator TABLE 3D. CONTROL FUNCTION TABLE Outputs Inputs PLL_SEL =1 Bank B Bank B Bank A Bank A DIV_ SELB0 0 DIV_ SELA1 0 DIV_ SELA0 0 Reference Frequency Range (MHz) 16.67 - 41.67 FBDIV_ SEL1 FBDIV_ SEL0 0 0 DIV_ SELB1 0 0 0 0 1 0 1 16.67 - 41.67 0 0 1 0 1 0 16.67 - 41.67 Frequency QX0:QX3 QX0:QX3 (MHz) FB_OUT (MHz) x4 66.68 - 166.68 16.67 - 41.67 x3 50 - 125 16.67 - 41.67 x2 33.34 - 83.34 16.67 - 41.67 0 0 1 1 1 1 16.67 - 41.67 x1 16.67 - 41.67 16.67 - 41.67 0 1 0 0 0 0 12.5 - 31.25 x 5.33 66.63 - 166.56 12.5 - 31.25 0 1 0 1 0 1 12.5 - 31.25 x4 50 - 125 12.5 - 31.25 0 1 1 0 1 0 12.5 - 31.25 x 2.667 33.34 - 83.34 12.5 - 31.25 0 1 1 1 1 1 12.5 - 31.25 x 1.33 16.63 - 41.56 12.5 - 31.25 1 0 0 0 0 0 10 - 25 x 6.667 66.67 - 166.68 10 - 25 1 0 0 1 0 1 10 - 25 x5 50 - 125 10 - 25 1 0 1 0 1 0 10 - 25 x 3.33 33.30 - 83.25 10 - 25 1 0 1 1 1 1 10 - 25 x 1.66 16.60 - 41.50 10 - 25 1 1 0 0 0 0 8.33 - 20.83 x8 66.64 - 166.64 8.33 - 20.83 1 1 0 1 0 1 8.33 - 20.83 x6 50 - 125 8.33 - 20.83 1 1 1 0 1 0 8.33 - 20.83 x4 33.32 - 83.32 8.33 - 20.83 1 1 1 1 1 1 8.33 - 20.83 x2 16.66 - 41.66 8.33 - 20.83 NOTE: VCO frequency range for all configurations above is 200MHz to 500MHz. 87608AYI www.icst.com/products/hiperclocks.html 4 REV. B MARCH 11, 2005 ICS87608I Integrated Circuit Systems, Inc. LOW VOLTAGE/LOW SKEW, 1:8 PCI/PCI-X ZERO DELAY CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDOX = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter VDD Core Supply Voltage Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDOX Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 185 mA IDDA Analog Supply Current 15 mA IDDOA Output Supply Current 20 mA IDDOB Output Supply Current 20 mA VDDOX denotes VDDOA, VDDOB. TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDOX = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C Symbol VIH VIL IIH IIL VOH Parameter Test Conditions MR, DIV_ SELx0, DIV_SELx1, F BDIV_SEL0, FBDIV_SEL1, Input High Voltage XTAL_SEL, FB_IN, PLL_SEL REF_IN MR, DIV_ SELx0, DIV_SELx1, FBDIV_SEL0, FBDIV_SEL1, Input Low Voltage XTAL_SEL, FB_IN, PLL_SEL REF_IN DIV_ SELx0, DIV_SELx1, FBDIV_SEL0, FBDIV_SEL1, Input High Current MR, FB_IN XTAL_SEL, PLL_SEL DIV_ SELx0, DIV_SELx1, FBDIV_SEL0, FBDIV_SEL1, Input MR, FB_IN Low Current XTAL_SEL, PLL_SEL Output High Voltage; NOTE 1 Maximum Units 2 VDD + 0.3 V 2 VDD + 0.3 V -0.3 0.8 V -0.3 1.3 V VDD = VIN = 3.465V 150 µA VDD = VIN = 3.465V 5 µA VDD = 3.465V, Minimum Typical -5 µA VDD = 3.465V, VIN = 0V -150 µA VDD = VIN = 3.465V 2.6 V VDD = VIN = 2.625V 1.8 V VIN = 0V Output Low Voltage; NOTE 1 VOL NOTE 1: Outputs terminated with 50Ω to VDDOX/2. See Parameter Measurement Information section, "3.3V Output Load Test Circuit". 87608AYI www.icst.com/products/hiperclocks.html 5 0.5 V REV. B MARCH 11, 2005 ICS87608I Integrated Circuit Systems, Inc. LOW VOLTAGE/LOW SKEW, 1:8 PCI/PCI-X ZERO DELAY CLOCK GENERATOR TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 10 38 Equivalent Series Resistance (ESR) MHz Ω 50 Shunt Capacitance 7 pF TABLE 6. PLL INPUT REFERENCE CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter fREF Reference Frequency Test Conditions Minimum Typical 8.33 Maximum Units 41.67 MHz Maximum Units 166.67 MHz TABLE 7A. AC CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency Test Conditions t(Ø) t sk(b) t sk(o) 325 ps Bank Skew; NOTE 2, 6 60 ps Output Skew; NOTE 3, 6 250 ps tjit(cc) Cycle-to-Cycle Jitter; 6 120 ps tjit(per) Period Jitter, RMS; NOTE 4, 6, 7 t sl(o) Slew Rate tL PLL Lock Time t R / tF Output Rise/Fall Time Static Phase Offset; NOTE 1 Minimum FREF = 25MHz 0 Typical 160 1 20% to 80% 200 20 ps 4 v/ns 10 ms 700 ps odc Output Duty Cycle; NOTE 5 48 52 % All parameters measured with feedback and output dividers set to DIV by 12 unless otherwise noted. NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. Measured at VDD/2. NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOX/2. NOTE 4: Jitter performance using LVCMOS inputs. NOTE 5: Measured using REF_IN. For XTAL input, refer to Application Note. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. NOTE 7: This parameter is defined as an RMS value. TABLE 7B. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDOX = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical FREF = 25MHz -365 -105 Maximum Units 166.67 MHz 160 ps ps fMAX Output Frequency t(Ø) Static Phase Offset; NOTE 1 t sk(b) t sk(o) Bank Skew; NOTE 2, 6 60 Output Skew; NOTE 3, 6 250 ps tjit(cc) Cycle-to-Cycle Jitter; 6 170 ps tjit(per) Period Jitter, RMS; NOTE 4, 6, 7 20 ps tsl(o) Slew Rate tL PLL Lock Time t R / tF Output Rise/Fall Time 1 20% to 80% odc Output Duty Cycle; NOTE 5 See Table 7A for notes. 87608AYI www.icst.com/products/hiperclocks.html 6 4 v/ns 10 ms 200 700 ps 48 52 % REV. B MARCH 11, 2005 ICS87608I Integrated Circuit Systems, Inc. LOW VOLTAGE/LOW SKEW, 1:8 PCI/PCI-X ZERO DELAY CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 1.65V±5% 2.05V±5% 1.25V±5% SCOPE VDD, VDDA,VDDOX VDD, VDDA Qx LVCMOS SCOPE VDDOX Qx LVCMOS GND GND -1.65V±5% -1.25V±5% 3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT (Where X denotes outputs in the same Bank) VDDOX 2 V DDOX 2 VDDOX 2 V DDOX Qy 2 t sk(o) Qy t sk(b) OUTPUT SKEW BANK SKEW V DDOX 2 DDOX 2 tcycle n+1 ➤ n 2 REF_IN 2 ➤ tcycle VDD V V DDOX QAx, QBx ➤ VDD 2 FB_IN ➤ t jit(cc) = tcycle n –tcycle n+1 ➤ t (Ø) ➤ Qx Qx 1000 Cycles STATIC PHASE OFFSET CYCLE-TO-CYCLE JITTER QAx, QBx, FB_OUT, REF_OUT VDDOX VDDOX VDDOX 2 2 2 80% t PW Clock Outputs t PERIOD odc = 20% 20% tR tF t PW t PERIOD OUTPUT PULSE WIDTH/PULSE WIDTH PERIOD 87608AYI 80% OUTPUT RISE/FALL TIME www.icst.com/products/hiperclocks.html 7 REV. B MARCH 11, 2005 ICS87608I Integrated Circuit Systems, Inc. LOW VOLTAGE/LOW SKEW, 1:8 PCI/PCI-X ZERO DELAY CLOCK GENERATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS87608I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDOX should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a .01μF bypass capacitor should be connected to each VDDA. 3.3V VDD .01μF 10Ω V DDA .01μF 10 μF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE resonant crystal and were chosen to minimize the frequency ppm error. The optimum C1 and C2 values can be slightly adjusted for optimum frequency accuracy. The ICS87608I has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel XTAL2 C1 22p X1 18pF Parallel Cry stal XTAL1 C2 22p Figure 2. CRYSTAL INPUt INTERFACE 87608AYI www.icst.com/products/hiperclocks.html 8 REV. B MARCH 11, 2005 ICS87608I Integrated Circuit Systems, Inc. LOW VOLTAGE/LOW SKEW, 1:8 PCI/PCI-X ZERO DELAY CLOCK GENERATOR RELIABILITY INFORMATION TABLE 8. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS87608I is: 5495 87608AYI www.icst.com/products/hiperclocks.html 9 REV. B MARCH 11, 2005 ICS87608I Integrated Circuit Systems, Inc. PACKAGE OUTLINE - Y SUFFIX LOW VOLTAGE/LOW SKEW, 1:8 PCI/PCI-X ZERO DELAY CLOCK GENERATOR FOR 32 LEAD LQFP TABLE 9. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. 0.80 BASIC e 0.60 0.75 L 0.45 θ 0° -- 7° ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 87608AYI www.icst.com/products/hiperclocks.html 10 REV. B MARCH 11, 2005 ICS87608I Integrated Circuit Systems, Inc. LOW VOLTAGE/LOW SKEW, 1:8 PCI/PCI-X ZERO DELAY CLOCK GENERATOR TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS87608AYI ICS87608AYI 32 Lead LQFP tray -40°C to 85°C ICS87608AYIT ICS87608AYI 32 Lead LQFP 1000 tape & reel -40°C to 85°C ICS87608AYILF ICS87608AYIL 32 Lead Lead-Free LQFP tray -40°C to 85°C ICS87608AYILFT ICS87608AYIL 32 Lead Lead-Free LQFP 1000 tape & reel -40°C to 85°C The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 87608AYI www.icst.com/products/hiperclocks.html 11 REV. B MARCH 11, 2005 ICS87608I Integrated Circuit Systems, Inc. LOW VOLTAGE/LOW SKEW, 1:8 PCI/PCI-X ZERO DELAY CLOCK GENERATOR REVISION HISTORY SHEET Rev Table A Page 2 7 Description of Change Date A T10 11 Corrected MR in the Block Diagram. Parameter Measurement Information - for 3.3V Outpt Load AC Test Circuit diagram corrected GND from "-1.165V±5%" to "-1.65V±5%". Ordering Information Table - added Lead-Free par t number. B T7B 6 AC Characteristics Table - changed tjit(cc) from 120ps max to 170ps max. 1/28/05 1 Feature section, Cycle-to-Cycle Jitter note - added "@ 3.3V". 3/11/05 A b 87608AYI www.icst.com/products/hiperclocks.html 12 4/6/04 4/23/04 10/11/04 REV. B MARCH 11, 2005