ICS9148-93 Integrated Circuit Systems, Inc. Advance Information Frequency Generator & Integrated Buffers for PENTIUM/ProTM General Description The ICS9148-93 is the single chip clock solution for Desktop/ Notebook designs using the VIA MVP3 style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9148-93 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. 2 Serial programming I C interface allows changing functions, stop clock programming and frequency selection. The SD_SEL latched input allows the SDRAM frequency to follow the CPUCLK frequency(SD_SEL=1) or the AGP clock frequency(SD_SEL=0). Block Diagram Features Generates the following system clocks: - 4 CPU(2.5V/3.3V) upto 100MHz. - 6 PCI(3.3V) @ 33.3MHz - 2AGP(3.3V) @ 2 x PCI - 12 SDRAMs(3.3V) @ either CPU or AGP - 2 REF (3.3V) @ 14.318MHz Skew characteristics: - CPU CPU<250ps - SDRAM SDRAM < 250ps - CPU SDRAM < 250ps - CPU(early) PCI : 1-4ns Supports Spread Spectrum modulation +0.25, ±0.6% Serial I2C interface for Power Management, Frequency Select, Spread Spectrum. Efficient Power management scheme through PCI and CPU STOP CLOCKS. Uses external 14.318MHz crystal 48 pin 300mil SSOP. Pin Configuration Power Groups VDD1 = REF (0:1), X1, X2 VDD2 = PCICLK_F, PCICLK(0:5) VDD3 = SDRAM (0:11), supply for PLL core, 24 MHz, 48MHz VDD4 = AGP (0:1) VDDL = CPUCLK (0:3) 9148-93 Rev - 1/22/99 48-Pin SSOP * Internal Pull-up Resistor of 240K to 3.3V on indicated inputs Pentium is a trademark of Intel Corporation I2C is a trademark of Philips Corporation ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. ICS9148-93 Advance Information Pin Descriptions PIN NUMBER 1 2 3,9,16,22,27, 33,39,45 P I N NA M E VDD1 REF0 TYPE PWR OUT C P U 3 . 3 # _ 2 . 5 1,2 IN GND PWR 4 X1 IN 5 X2 OUT VDD2 PWR PCICLK_F OUT 6,14 7 FS11, 2 8 10, 11, 12, 13 15, 47 IN PCICLK0 OUT 1, 2 IN FS2 PCICLK(1:4) AGP (0:1) OUT OUT CPU_STOP#1 IN 17 SDRAM 11 OUT PCI_STOP#1 IN SDRAM 10 OUT SDRAM (0:9) OUT 19,30,36 VDD3 PWR 23 24 SDATA SCL K 24MHz IN IN OUT 18 20, 21,28, 29, 31, 32, 34, 35,37,38 25 MODE1, 2 48MHz 26 40, 41, 43, 44 42 46 48 FS0 1, 2 CPUCLK(0:3) VDDL REF1 SD_SEL VDD4 IN OUT IN OUT PWR OUT IN PWR DESCRIPTION Ref (0:2), XTAL power supply, nominal 3.3V 14.318 MHz reference clock. Indicates whether VDDL2 is 3.3V or 2.5V. High=2.5V CPU, LOW=3.3V C P U 1. L a t c h e d i n p u t 2 Ground Crystal input, has internal load cap (33pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (33pF) Supply for PCICLK_F and PCICLK (0:5), nominal 3.3V Free running PCI clock output. Synchronous with CPUCLKs with 1-4ns skew (CPU early) This is not affected by PCI_STOP# Frequency select pin. Latched Input. Along with other FS pins determines the CPU, SDRAM, PCI & AGP frequencies. PCI clock output. Synchronous CPUCLKs with 1-4ns skew (CPU early) Frequency select pin. Latched Input Along with other FS pins determines the CPU, SDRAM, PCI & AGP frequencies. PCI clock outputs. Synchronous CPUCLKs with 1-4ns skew (CPU early) Advanced Graphic Port outputs, powered by VDD4. This asynchronous input halts CPUCLK (0:3) and AGP (0:1) clocks at logic 0 level, when input low (in Mobile Mode, MODE=0) SDRAM clock output. Frequency is selected by the SD_SEL latched input. SD_SEL = 1 at power on causes SDRAM frequency = CPU frequency SD_SEL = 0 at power on causes SDRAM frequency = AGP frequency This asynchronous input halts PCICLK(0:5) clocks at logic 0 level, when input low (In mobile mode, MODE=0) SDRAM clock output. Frequency is selected by the SD_SEL latched input. SD_SEL = 1 at power on causes SDRAM frequency = CPU frenquency SD_SEL = 0 at power on causes SDRAM frequency = AGP frequency SDRAM clock outputs. Frequency is selected by the SD_SEL latched input. SD_SEL = 1 at power on causes SDRAM frequency = CPU frequency SD_SEL = 0 at power on causes SDRAM frequencies = AGP frequency Supply for SDRAM (0:11), CPU Core and 24, 48MHz clocks, nominal 3.3V. Data input for I2C serial input. Clock input of I2C input 24MHz output clock, for Super I/O timing. Pin 17, pin 18 function select pin, 1=Desktop Mode, 0=Mobile Mode. Latched Input. 48MHz output clock, for USB timing. Frequency select pin. Latched Input Along with other FS pins determines the CPU, SDRAM, PCI & AGP frequencies. CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low Supply for CPU (0:3), either 2.5V or 3.3V nominal 14.318MHz reference clock. Latched input at Power On selects either CPU (SDSEL=1) or AGP (SD_SEL=0) frequencies for the SDRAM clock outputs. Supply for AGP (0:1) Notes: 1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low. 2 ICS9148-93 Advance Information Mode Pin - Power Management Input Control MODE, Pin 25 (Latched Input) 0 1 Pin 17 Pin 18 CPU_STOP# (INPUT) SDRAM 11 (OUTPUT) PCI_STOP# (INPUT) SDRAM 10 (OUTPUT) Power Management Functionality PCICLK (0:5) PCICLK_F, REF, 24/48MHz and SDRAM Crystal OSC VCO CPU_STOP# PCI_STOP# AGP, CPUCLK Outputs 0 1 Stopped Low Running Running Running Running 1 1 Running Running Running Running Running 1 0 Running Stopped Low Running Running Running CPU 3.3#_2.5V Buffer selector for CPUCLK drivers. CPU3.3#_2.5 Input level (Latched Data) 1 0 Buffer Selected for operation at: 2.5V VDD 3.3V VDD Functionality VDD1, 2, 3, 4 = 3.3V±5%, VDDL = 2.5V ±5% or 3.3 ±5%, TA= 0 to 70°C Crystal (X1, X2) = 14.31818MHz FS2 FS1 FS0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CPU (MHz) SDRAM (MHz) 90.00 66.82 68.49 75.00 75.00 83.31 95.25 100.00 PCI (MHz) AG P ( M H z ) 30.00 33.41 34.25 37.5 30.00 33.32 31.75 33.33 60.00 66.82 68.49 75.00 60.00 66.64 63.50 66.66 3 ICS9148-93 Advance Information General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: Send the address D2(H) . Send two additional dummy bytes, a command code and byte count. Send the desired number of data bytes. See the diagram below: Clock Generator Address (7 bits) A(6:0) & R/W# ACK + 8 bits dummy command code ACK + 8 bits dummy Byte count ACK Data Byte 1 ACK Data Byte N ACK D2(H) Note that the acknowledge bit is sent by the clock chip, and pulls the data line low. There is no minimum of data bytes that must be sent. How to Read: Send the address D3(H). Send the byte count in binary coded decimal Read back the desired number of data bytes See the diagram below: Clock Generator Address (7 bits) A(6:0) & R/W# ACK Byte Count ACK Data Byte 1 ACK Data Byte N D3(H) The following specifications should be observed: 1. Operating voltage for I2C pins is 3.3V 2. Maximum data transfer rate (SCLK) is 100K bits/sec. Note 1. Default at Power-up will be for latched logic inputs, as defined by Bit 3. I2C is a trademark of Philips Corporation Serial Configuration Command Bitmap Byte0: Functionality and Frequency Select Register (default = 0) Bit Description 5% Spread Spectrum Modulation Bit 7 10 -- ±±00..62% Spread Spectrum Modulation Bit (6:4) CPU PCI AGP SDRAM (MHz) (MHz) (MHz) 000 90.00 30.00 60.00 001 66.82 33.41 66.82 Bit 010 68.49 34.25 68.49 6:4 011 75.00 37.50 75.00 100 75.00 30.00 60.00 101 83.31 33.32 66.64 110 95.25 31.75 63.50 111 100.00 33.33 66.66 0 - Frequency is selected by hardware select, Bit 3 FS(0:2) pins only 1 - Select frequencies by I2C 0 - Center Spread 1 - Down Spread al operation Bit 1 10 -- SNporrem ad Spectrum Enabled Bit 0 10- -TRriusntantienagll outputs 4 PWD 0 XXX Note 1 0 0 0 0 ICS9148-93 Advance Information Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 40 41 43 44 PWD 1 1 1 1 1 1 1 1 Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Description (Reserved) (Reserved) (Reserved) (Reserved) CPUCLK3 (Act/Inact) CPUCLK2 (Act/Inact) CPUCLK1 (Act/Inact) CPUCLK0 (Act/Inact) Pin # 7 15 13 12 11 10 8 PWD 1 1 1 1 1 1 1 1 Description (Reserved) PCICLK_F (Act/Inact) AGP0 (Act/Inact) PCICLK4 (Act/Inact) PCICLK3 (Act/Inact) PCICLK2 (Act/Inact) PCICLK1 (Act/Inact) PCICLK0(Act/Inact) Notes: 1. Inactive means outputs are held LOW and are disabled from switching. Notes: 1. Inactive means outputs are held LOW and are disabled from switching. Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable) Byte 4: SDRAM Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 28 29 31 32 34 35 37 38 PWD 1 1 1 1 1 1 1 1 Description SDRAM7 (Act/Inact) SDRAM6 (Act/Inact) SDRAM5 (Act/Inact) SDRAM4 (Act/Inact) SDRAM3 (Act/Inact) SDRAM2 (Act/Inact) SDRAM1 (Act/Inact) SDRAM0 (Act/Inact) Notes: 1. Inactive means outputs are held LOW and are disabled from switching. Pin # 47 46 2 PWD 1 1 1 1 1 1 1 1 Pin # - PWD 1 1 1 1 Bit 3 17 1 Bit 2 18 1 Bit 1 Bit 0 20 21 1 1 Description (Reserved) (Reserved) (Reserved) (Reserved) SDRAM11 (Act/Inact) (Desktop Mode Only) SDRAM10 (Act/Inact) (Desktop Mode Only) SDRAM9 (Act/Inact) SDRAM8 (Act/Inact) Notes: 1. Inactive means outputs are held LOW and are disabled from switching. Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Bit 7 Bit 6 Bit 5 Bit 4 Description (Reserved) (Reserved) (Reserved) AGP1(Act/Inact) (Reserved) (Reserved) REF1 (Act/Inact) REF0 (Act/Inact) Notes: 1. Inactive means outputs are held LOW and are disabled from switching. 5 ICS9148-93 Advance Information CPU_STOP# Timing Diagram CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS9148-93. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks. Notes: 1. All timing is referenced to the internal CPU clock. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPU clocks inside the ICS9148-93. 3. All other clocks continue to run undisturbed. (including SDRAM outputs). 6 ICS9148-93 Advance Information PCI_STOP# Timing Diagram PCI_STOP# is an asynchronous input to the ICS9148-93. It is used to turn off the PCICLK (0:5) clocks for low power operation. PCI_STOP# is synchronized by the ICS9148-93 internally. The minimum that the PCICLK (0:5) clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock. Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9148. 3. All other clocks continue to run undisturbed. 4. CPU_STOP# is shown in a high (true) state. 7 ICS9148-93 Advance Information Shared Pin Operation Input/Output Pins These figures illustrate the optimal PCB physical layout options. These configuration resistors are of such a large ohmic value that they do not effect the low impedance clock signals. The layouts have been optimized to provide as little impedance transition to the clock signal as possible, as it passes through the programming resistor pad(s). Pins 2, 7, 8, 25, 26 and 46 on the ICS9148-93 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 4-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm(10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figs. 1 and 2 show the recommended means of implementing this function. In Fig. 1 either one of the resistors is loaded onto the board (selective stuffing) to configure the devices internal logic. Figs. 2a and b provide a single resistor loading option where either solder spot tabs or a physical jumper header may be used. Fig. 1 8 ICS9148-93 Advance Information Fig. 2a Fig. 2b 9 ICS9148-93 Advance Information Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V GND 0.5 V to VDD +0.5 V 0°C to +70°C 65°C to +150°C 115°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Input frequency Input Capacitance1 Transition Time1 CONDITIONS VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; 66.8 MHz Fi VDD = 3.3 V; CIN CINX Logic Inputs X1 & X2 pins Ttrans To 1st crossing of target Freq. -5 -200 27 Ts From 1st crossing to 1% target Freq. Clk Stabilization1 TSTAB From VDD = 3.3 V to 1% target Freq. Skew MIN 2 VSS-0.3 TYP 0.1 2.0 -100 100 MAX VDD+0.3 0.8 5 160 14.318 Settling Time1 1 1 SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP TCPU-SDRAM1 VT = 1.5 V; SDRAM Leads TCPU-PCI1 VT = 1.5 V; CPU Leads 36 UNITS V V mA mA mA mA MHz 5 45 pF pF 2 ms ms -500 1 200 2.8 2 ms 500 4 ps ns Guaranteed by design, not 100% tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Operating Supply Current Skew1 1 SYMBOL IDD2.5OP CONDITIONS CL = 0 pF; 66.8 MHz MIN TYP 10 MAX 20 UNITS mA TCPU-SDRAM2 VT = 1.5 V; VTL = 1.25 V; SDRAM Leads TCPU-PCI2 VT = 1.5 V; VTL = 1.25 V; CPU Leads -500 1 200 2.7 500 4 ps ns Guaranteed by design, not 100% tested in production. 10 ICS9148-93 Advance Information Electrical Characteristics - CPU TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output High Voltage VOH2B IOH = -8 mA Output Low Voltage VOL2B IOL = 12 mA Output High Current IOH2B VOH = 1.7 V Output Low Current IOL2B VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V Rise Time tr2B1 1 VOH = 2.0 V, VOL = 0.4 V Fall Time tf2B Duty Cycle dt2B1 VT = 1.25 V Skew tsk2B1 VT = 1.25 V Jitter, Single Edge tjsed2B1 VT = 1.25 V Displacement2 Jitter, One Sigma tj1s2B1 VT = 1.25 V Jitter, Absolute tjabs2B1 VT = 1.25 V 1 2 MIN 2 19 40 -300 TYP 2.2 0.3 -20 26 1.5 1.6 47 60 MAX 1.8 1.8 55 250 UNITS V V mA mA ns ns % ps 200 250 ps 65 160 150 300 ps ps 0.4 -16 Guaranteed by design, not 100% tested in production. Edge displacement of a period relative to a 10-clock-cycle rolling average period. Electrical Characteristics - CPU TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; C L = 10 - 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current SYMBOL VOH2A VOL2A IOH2A IOL2A Rise Time tr2A1 tf2A1 d t2A1 t sk2A1 tj1s2A1 tjabs2A1 Fall Time Duty Cycle Skew Jitter, One Sigma Jitter, Absolute 1 CONDITIONS IOH = -28 mA IOL = 27 mA VOH = 2.0 V VOL = 0.8 V MIN 2.5 33 TYP 2.6 0.35 -29 37 MAX 0.4 -23 UNITS V V mA mA VOL = 0.4 V, VOH = 2.4 V 1.75 2 ns VOH = 2.4 V, VOL = 0.4 V 1.1 2 ns 50 55 % 50 250 ps VT = 1.5 V 45 VT = 1.5 V VT = 1.5 V VT = 1.5 V -250 Guaranteed by design, not 100% tested in production. 11 65 150 ps 165 250 ps ICS9148-93 Advance Information Electrical Characteristics - SDRAM TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF PARAMETER SYMBOL CONDITIONS IOH = -28 mA Output High Voltage VOH1 IOL = 23 mA Output Low Voltage VOL1 VOH = 2.0 V Output High Current IOH1 VOL = 0.8 V Output Low Current IOL1 1 Rise Time Tr1 VOL = 0.4 V, VOH = 2.4 V 1 Fall Time Tf1 VOH = 2.4 V, VOL = 0.4 V Duty Cycle1 Skew1 Jitter, One Sigma 1 1 Jitter, Absolute Jitter, Absolute1 1 MIN 2.4 41 TYP 3 0.2 -60 50 MAX 1.75 2 UNITS V V mA mA 0.4 -40 ns 1.5 2 ns 50 55 % VT = 1.5 V 200 500 ps Tj1s1 VT = 1.5 V 50 150 ps Tjabs1 Tjabs1 VT = 1.5 V (with synchronous PCI) VT = 1.5 V (with asynchronous PCI) -250 +250 ps -400 400 ps Dt1 VT = 1.5 V Tsk1 45 Guaranteed by design, not 100% tested in production. Electrical Characteristics - PCI TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current CONDITIONS IOH = -28 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V MIN 2.4 41 TYP 3 0.2 -60 50 MAX 0.4 -40 UNITS V V mA mA tr1 1 VOL = 0.4 V, VOH = 2.4 V 1.8 2 ns t f1 1 VOH = 2.4 V, VOL = 0.4 V 1.6 2 ns Duty Cycle d t1 1 VT = 1.5 V 51 55 % Skew tsk1 1 VT = 1.5 V 130 250 ps tj1s1a tj1s1b VT = 1.5 V, synchronous VT = 1.5 V, asynchronous 40 200 150 250 ps ps tab s1a tjabs1b VT = 1.5 V, synchronous VT = 1.5 V, asynchronous 135 500 250 650 ps ps Rise Time Fall Time Jitter, One Sigma Jitter, Absolute 1 SYMBOL VOH1 VOL1 IOH1 IOL1 1 1 45 Guaranteed by design, not 100% tested in production. 12 -250 -650 ICS9148-93 Advance Information Electrical Characteristics - AGP TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current SYMBOL VOH1 VOL1 IOH1 IOL1 Rise Time tr1 1 Fall Time Duty Cycle 1 TYP 3 0.2 -60 50 MAX VOL = 0.4 V, VOH = 2.4 V 1.1 2 ns 1 VOH = 2.4 V, VOL = 0.4 V 1 2 ns 1 VT = 1.4 V 49 55 % 1 VT = 1.5 V 130 250 ps tj1s1 VT = 1.5 V 2 3 % 2.5 4.5 5 6 % % TYP 2.6 0.3 -32 25 MAX UNITS V V mA mA 2 4 ns 1.9 4 ns 54 57 % 1 3 % - 5 % tf1 d t1 Skew Jitter, One Sigma1 tsk1 Jitter, Absolute1 tabs1a tjabs1b CONDITIONS IOH = -28 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V MIN 2.4 41 45 VT = 1.5 V, synchronous VT = 1.5 V, asynchronous -5 -6 0.4 -40 UNITS V V mA mA Guaranteed by design, not 100% tested in production. Electrical Characteristics - 24MHz, 48MHz, REF0 TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; C L = 10 -20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current CONDITIONS IOH = -16 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V tr5 1 VOL = 0.4 V, VOH = 2.4 V Fall Time tf5 1 VOH = 2.4 V, VOL = 0.4 V Duty Cycle d t5 1 Rise Time Jitter, One Sigma Jitter, Absolute 1 SYMBOL VOH5 VOL5 IOH5 IOL5 1 tj1s5 tjabs5 1 MIN 2.4 16 VT = 1.5 V 45 VT = 1.5 V VT = 1.5 V -5 Guaranteed by design, not 100% tested in production. 13 0.4 -22 ICS9148-93 Advance Information SSOP Package SYMBOL A A1 A2 B C D E e H h L N ∝ X COMMON DIMENSIONS MIN. NOM. MAX. .095 .101 .110 .008 .012 .016 .088 .090 .092 .008 .010 .0135 .005 .010 See Variations .292 .296 .299 0.025 BSC .400 .406 .410 .010 .013 .016 .024 .032 .040 See Variations 0° 5° 8° .085 .093 .100 VARIATIONS AC MIN. .620 D NOM. .625 N MAX. .630 48 Ordering Information ICS9148F-37 Example: ICS XXXX F - PPP Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 14 ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice.