ICS ICS9148-25

Integrated
Circuit
Systems, Inc.
ICS9148-25
Pentium/ProTM System and Cyrix™ Clock Chip
General Description
Features
The ICS9148-25 is a Clock Synthesizer chip for Pentium and
PentiumPro plus Cyrix CPU based Desktop/Notebook systems
that will provide all necessary clock timing.
•
Features include four CPU, seven PCI and eight SDRAM
clocks. Two reference outputs are available equal to the crystal
frequency, plus the IOAPIC output powered by VDDL.
Additionally, the device meets the Pentium power-up
stabilization, which requires that CPU and PCI clocks be stable
within 2ms after power-up.
High drive PCICLK and SDRAM outputs typically provide
greater than 1 V/ns slew rate into 30pF loads. CPUCLK outputs
typically provide better than 1V/ns slew rate into 20pF loads
while maintaining 50 ±5% duty cycle. The REF clock outputs
typically provide better than 0.5V/ns slew rates.
•
•
•
•
•
•
•
•
•
The ICS9148-25 accepts a 14.318MHz reference crystal or
clock as its input and runs on a 3.3V supply.
Sperad Spectrum is modulated in center-spread mode on CPU/
SDRAM/PCI clocks. Modulation amount is selectable at
power-up (latched inputs) for ±0.5, ±1.0, ±2.0 or No spreading.
•
•
Generates system clocks for CPU, IOAPIC, SDRAM,
PCI, plus 14.318 MHz ), USB, Plus Super I/O
Spread spectrum for CPU/SDRAM/PCI clocks default
Supports single or dual processor systems
Modulation of Spread Spectrum selectable as ±0.5, ±1.0,
±2.0 or none
Supports Intel 60, 66.8MHz, Cyrix 55, 75MHz plus 83.3
and 68MHz (Turbo of 66.6) speeds.
Synchronous clocks skew matched to 250ps window on
CPU, SDRAM and 500ps window on PCI clocks
CPU clocks to PCI clocks skew 1-4ns (CPU early)
MODE input pin selects optional power management
input control pins
Two fixed outputs, 48MHz and 24 MHz
Separate 2.5V and 3.3V supply pins
- 2.5V or 3.3V output: CPU, IOAPIC (Strength
selectable)
- 3.3V outputs: SDRAM, PCI, REF, 48/24 MHz
No power supply sequence requirements
48 pin 300 mil SSOP
Pin Configuration
Block Diagram
48-Pin SSOP
Power Groups
Pentium is a trademark on Intel Corporation.
9148-25 Rev B 5/20/99
VDD = Supply for PLL core.
VDD1 = REF (0:2), X1, X2
VDD2 = PCICLK_F, PCICLK (0:5)
VDD3 = SDRAM (0:5), SDRAM6/CPU_STOP#,
SDRAM7/PCI_STOP#
VDD4 = 48MHz, 24MHz
VDDL1 = IOAPIC
VDDL2 = CPUCLK (0:3)
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
ICS9148-25
Pin Descriptions
PIN NUMBER
PIN NAME
SSM1
IN
REF1
REF0
OUT
OU T
DESCRIPTION
Latched input for Spread Spectrum modulation amount
(see table)*
Reference clock output
Reference clock output
GND
PWR
Ground (common)
4
X1
IN
5
6
7,15
8
X2
MODE
VDD2
PCICLK_F
PCICLK0
OUT
IN
PWR
OUT
OUT
1
2
3, 10, 17, 24,
31, 37, 43
9
11, 12, 13, 14, 16
18
19
20
21
22
23
25
26
27
TYPE
SSM0
IN
PCI_CLK (1:5)
FS0
FS1
FS2
VDD4
48MHz
24MHz
VDD
SDRAM7
PCI_STOP#
SDRAM6
CPU_STOP#
OUT
IN
IN
IN
PWR
OUT
OUT
PWR
OU T
IN
OUT
IN
28,34
VDD3
PWR
29, 30, 32, 33, 35, 36
38, 39, 41, 42
40
44
SDRAM (0:5)
CPUCLK (0:3)
VDD2
PD#
OUT
OUT
PWR
IN
45
IOAPIC
OUT
46
VDDL1
CPU3.3_2.5#
REF2
VDD1
PWR
IN
OUT
PWR
47
48
Crystal or reference input, nominally 14.318 MHz. Includes
internal load cap to GND and feedback resistor from X2.
Crystal output, includes internal load cap to GND.
Input function selection for Power Management pins*
Supply for PCICLK_F, and PCICLK (0:5)
Free running PCI clock, not affected by PCI_STOP#
PCI clocks
Latched input for Spread Spectrum modulation amount
(see table)*
PCI clocks
Frequency select 0 input*
Frequency select 1 input*
Frequency select 2 input*
Supply for 48MHz and 24MHz clocks
48MHz driver output for USB clock
24MHz driver output for Super I/O
Supply for PLL core
SDRAM clock
Halts PCI Bus (0:5) at next logic "0" level when low*
SDRAM clock
Halts CPU clocks at next logic "0" level when low*
Supply for SDRAM (0:5), SDRAM6/CPU_STOP#,
SDRAM7/PCI_STOP
SDRAMs clock at CPU speed
CPUCLK clock output, powered by VDDL2
Supply for CPUCLK (0:3)
Powers down chip, active low*
IOAPIC clock output, powered by VDDL1, at crystal
frequency
Supply for IOAPIC
Latched 3.3 or 2.5 VDD buffer strength selection* (see table)
Reference clock output
Supply for REF (0:2), X1, X2
*Internal pull-up resistor of 120 to 150K to 3.3V on indicated inputs.
Functionality
VDD = 3.3V ±5% VDDL = 2.5V ±5% or 3.3V ±5%, TA = 0 to 70°C
Crystal (X1, X2) = 14.31818 MHz
FS2
FS 1
FS0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CPUCLK,
SDRAM
(MHz)
83.3
75
83.3
68.5
55
75
60
66.8
PCICLK
(MHz)
1/2 CPU
30 (CPU/2.5)
33.3 (CPU/2.5)
1/2 CPU
1/2 CPU
1/2 CPU
1/2 CPU
1/2 CPU
2
ICS9148-25
Mode Pin - Power Management Input Control
MODE, Pin 6
Pin 26
Pin 27
0
PCI_STOP#
Input
CPU_STOP#
Input
1
SDRAM7 Output
SDRAM 6
Output
Power Management Functionality
PCICLK(0:5)
Outputs
PCICLK_F,
REF,
24/48MHz
and SDRAM
Crystal
OSC
VCO
CPU_STOP#
PCI_STOP#
PD#
CPUCLK
Outputs
X
X
0
Stopped Low
Stopped Low
Stopped Low
Off
Off
0
0
1
Stopped Low
Stopped Low
Running
Running
Running
0
1
1
Stopped Low
Running
Running
Running
Running
1
0
1
Running
Stopped Low
Running
Running
Running
1
1
1
Running
Running
Running
Running
Running
Spread Spectrum Functionality
Latched Pin 1
SSM1
Latched Pin 9
SSM0
CPU, SDRAM
and PCICLOCKS
REF, IOAPIC
24MHz
48MHz
0
0
Normal, steady
frequency mode
14.318MHz
24MHz
48MHz
0
1
Frequency modulated in
center spread ±2.0%
14.318MHz
24MHz
48MHz
1
0
Frequency modulated in
center spread ±1.0%
14.318MHz
24MHz
48MHz
1*
1*
Frequency modulated in
center spread ±0.5%
14.318MHz
24MHz
48MHz
*default with internal pull-ups
CPU 3.3_2.5V Buffer selector for CPUCLK and IOAPIC drivers.
CPU3.3_2.5#
Latched Input Level
0
1
Buffer Selected for
Operation at:
2.5V VDD
3.3V VDD
3
ICS9148-25
Technical Pin Function Descriptions
VDD(1,2,3,4)
This is the power supply to the internal core logic of the
device as well as the clock output buffers for REF(0:1),
PCICLK, 48/24MHzA/B and SDRAM(0:7).
SDRAM(0:7)
These Output Clocks are use to drive Dynamic RAM’s and
are low skew copies of the CPU Clocks. The voltage swing of
the SDRAM’s output is controlled by the supply voltage
that is applied to VDD3 of the device, operates at 3.3 volts.
These clocks are modulated by Sperad Spectrum.
This pin operates at 3.3V volts. Clocks from the listed buffers
that it supplies will have a voltage swing from Ground to this
level. For the actual guaranteed high and low voltage levels
for the Clocks, please consult the DC parameter table in this
data sheet.
48MHz
This is a fixed frequency Clock output at 48MHz that is
typically used to drive USB devices.
VDDL1,2
This is the power supplies for the CPUCLK and IOAPCI
output buffers. The voltage level for these outputs may be
2.5 or 3.3volts. Clocks from the buffers that each supplies will
have a voltage swing from Ground to this level. For the actual
Guaranteed high and low voltage levels of these Clocks,
please consult the DC parameter table in this Data Sheet. See
control pin CPUCLK3.3_2.5# for output buffer strength
matching VDDL required for skew control.
24MHz
This pin is a fixed frequency clock output typically used to
drive Super I/O devices.
IOAPIC
This Output is a fixed frequency Output Clock that runs at
the Reference Input (typically 14.31818MHz) . Its voltage
level swing is controlled by VDDL1 and may operate at 2.5 or
3.3volts.
GND
This is the power supply ground (common or negative) return
pin for the internal core logic and all the output buffers.
REF(0:2)
The REF Outputs are fixed frequency Clocks that run at the
same frequency as the Input Reference Clock X1 or the
Crystal (typically 14.31818MHz) attached across X1 and X2.
X1
This input pin serves one of two functions. When the device
is used with a Crystal, X1 acts as the input pin for the
reference signal that comes from the discrete crystal. When
the device is driven by an external clock signal, X1 is the
device input pin for that reference clock. This pin also
implements an internal Crystal loading capacitor that is
connected to ground. See the data tables for the value of this
capacitor. Also includes feedback resistor from X2.
PCICLK_F
This Output is equal to PCICLK(0:5) and is FREE RUNNING,
and will not be stopped by PCI_STP#. This clock is modulated
by Spread Spectrum.
PCICLK (0:5)
These Output Clocks generate all the PCI timing requirements
for a Pentium/Pro based system. They conform to the current
PCI specification. They run at 1/2 CPU frequency, or CPU/2.5,
see frequency table. These clocks are modulated by Sperad
Spectrum.
X2
This Output pin is used only when the device uses a Crystal
as the reference frequency source. In this mode of operation,
X2 is an output signal that drives (or excites) the discrete
Crystal. The X2 pin will also implement an internal Crystal
loading capacitor that is connected to ground. See the Data
Sheet for the value of this capacitor.
FS (0,1,2)
These Input pins control the frequency of the Clocks at the
CPU, PCICLK and SDRAM output pins. See frequency table.
These pins are all Full-time inputs with a pull-up to VDD.
CPUCLK (0:3)
These Output pins are the Clock Outputs that drive processor
and other CPU related circuitry that requires clocks which are
in tight skew tolerance with the CPU clock. The voltage
swing of these Clocks are controlled by the Voltage level
applied to the VDDL2 pin of the device. See the Functionality
Table for a list of the specific frequencies that are available
for these Clocks and the selection codes to produce them.
See control pin CPUCLK3.3_2.5# for output buffer strength
matching VDDL required for CPU to SDRAM skew control.
These clocks are modulated by Sperad Spectrum.
MODE
This Input pin is used to select the Input function of the
Power Management I/O pins 26 and 27. An active Low will
place pins in the Input mode and enable those stop clock
functions. This pin is a full-time input with a pull-up to VDD.
4
ICS9148-25
Technical Pin Function Descriptions
CPU3.3_2.5#
This Input pin controls the CPU and IOAPIC output buffer
strength for skew matching CPU and SDRAM outputs to
compensate for the external VDDL supply condition. It is
important to use this function when selecting power supply
requirements for VDDL1,2. A logic “0” (ground) will indicate
2.5V operation and a logic “1” will indicate 3.3V operation.
This pin has an internal pull-up to VDD. This pin is a latched
input.
SSM (0:1)
These pins define the input condition for the Spread Spectrum
amount of modulation. See Spread Spectrum functionality
table. Note that spreading is only done on the CPU/SDRAM/
PCI clocks no modulation is done on the REF, IOAPIC or
PLL2 (24, 48MHz) outputs.
These latched input pins are defined at power-on for logic Hi
or logic Low condition by external pull-up or pull-down
resistors, or the internal pull-up resistor to VDD. See shared
pin operation of Input/output pins on next page.
PD#
This is an asynchronous active Low Input pin used to Power
Down the device into a Low Power state by not removing the
power supply. The internal Clocks are disabled and the VCO
and Crystal are stopped. Powered Down will also place all the
Outputs in a low state at the end of their current cycle. The
latency of Power Down will not be greater than 3ms. This pin
is a Full-time input with a pull-up to VDD.
CPU_STOP#
This is a active Low Input pin used to stop the CPUCLK
clocks in an active low state. All other clocks will continue to
run while this function is enabled. The CPUCLK’s will have a
turn OFF latency and a turn ON latency of 2 or 3 CPU clocks.
This pin is a Full-time input with a pull-up to VDD.
PCI_STOP#
This is a synchronous active Low Input pin used to stop the
PCICLK (0:5) clocks in a low state. It will not effect PCICLK_F
or any other outputs. There is only one full PCI clock output
for Turn OFF or Turn ON latency. This pin is a Full-time input
with a pull-up to VDD.
5
ICS9148-25
Shared Pin Operation Input/Output Pins
Pins 1, 9 & 47 on the ICS9148-25 serve as dual signal
functions to the device. During initial power-up, they act as
input pins. The logic level (voltage) that is present on these
pins at this time is read and stored into a 4-bit internal data
latch. At the end of Power-On reset, (see AC characteristics
for timing values), the device changes the mode of operations
for these pins to an output function. In this mode the pins
produce the specified buffered clocks to external loads.
Figs. 1 and 2 show the recommended means of implementing
this function. In Fig. 1 either one of the resistors is loaded
onto the board (selective stuffing) to configure the device’s
internal logic. Figs. 2a and b provide a single resistor loading
option where either solder spot tabs or a physical jumper
header may be used.
These figures illustrate the optimal PCB physical layout
options. These configuration resistors are of such a large
ohmic value that they do not effect the low impedance clock
signals. The layouts have been optimized to provide as little
impedance transition to the clock signal as possible, as it
passes through the programming resistor pad(s).
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
There is no degradation to the output clocks from resistors
as low as 2K ohm. The internal pull-up resistors can be used
as the logic high program input.
Fig. 1
6
ICS9148-25
Fig. 2a
Fig. 2b
7
ICS9148-25
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
Supply Current
Power Down
Supply Current
Input frequency
Input Capacitance
Transition Time
Settling Time
1
1
Clk Stabilization
1
Skew
1
1
SYMBOL
VIH
VIL
IIH
IIL1
IIL2
IDD3.3OP
IDD3.3P D
VIN = VDD
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
CL = 0 pF; Select @ 66M
MIN
2
VSS-0.3
-5
-200
CL = 0 pF; With input address to Vdd or GND
Fi
VDD = 3.3 V;
CIN
CINX
Logic Inputs
X1 & X2 pins
Ttrans
To 1st crossing of target Freq.
Ts
1
CONDITIONS
TYP
0.1
2.0
-100
75
8
MAX UNITS
VDD +0.3
V
0.8
V
µA
5
µA
µA
95
mA
600
µA
14.318
27
From 1st crossing to 1% target Freq.
5
45
pF
pF
3
ms
5
TSTAB
From VDD = 3.3 V to 1% target Freq.
TCP U-SDRAM1 VT = 1.5 V
TCP U-P CI1 VT = 1.5 V;
TREF-IOAP IC VT = 1.5 V;
36
MHz
200
1
2
900
ms
3
500
ms
ps
4.5
ns
ps
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Operating
Supply Current
SYMBOL
IDD2.5OP
CONDITIONS
CL = 0 pF; Select @ 66M
MIN
TCP U-SDRAM2 VT = 1.5 V; VTL = 1.25 V; SDRAM Leads
1
Skew
1
TREF-IOAP IC VT = 1.5 V; VTL = 1.25 V; SDRAM Leads
TCP U-P CI2 VT = 1.5 V; VTL = 1.25 V; CPU Leads
Guarenteed by design, not 100% tested in production.
8
1
TYP
8
MAX
9.5
UNITS
mA
250
500
ps
260
2
4
ps
ns
ICS9148-25
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
Output Impedance
1
RDSP 2B
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
1
RDSN2B
VOH2B
VOL2B
IOH2B
IOL2B
tr2B
1
1
Fall Time
tf2B
Duty Cycle
1
d t2B
Skew
t sk2B
tj1s2B
1
1
tjabs2B
1
MIN
TYP
MAX UNITS
VO = VDD *(0.5)
10
25
Ω
VO = VDD *(0.5)
IOH = -13.0 mA
IOL = 14 mA
VOH = 1.7 V
VOL = 0.7 V
10
2
25
Ω
V
V
mA
mA
2.2
0.3
-25
26
0.4
-16
VOL = 0.4 V, VOH = 2.0 V
1.35
1.6
ns
VOH = 2.0 V, VOL = 0.4 V
1.2
1.6
ns
50
55
ns
VT = 1.25 V
60
250
ps
VT = 1.25 V
150
250
ps
VT = 1.25 V
30
150
ps
-250
80
+250
ps
MIN
TYP
22
VT = 1.25 V
1
1
tjcyc-cyc2B
Jitter
CONDITIONS
45
VT = 1.25 V
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
Fall Time
Duty Cycle
Skew
Jitter
1
SYMBOL
CONDITIONS
MAX UNITS
RDSP1
1
VO = VDD*(0.5)
12
55
Ω
RDSN1
VOH1
VOL1
IOH1
IOL1
1
VO = VDD*(0.5)
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
12
2.6
55
Ω
V
V
mA
mA
40
3.1
0.15
-62
55
0.4
-40
tr1
1
VOL = 0.4 V, VOH = 2.4 V
1.5
2
ns
tf1
1
VOH = 2.4 V, VOL = 0.4 V
1.4
2
ns
1
VT = 1.5 V
50
60
%
1
VT = 1.5 V
200
500
ps
1
VT = 1.5 V
VT = 1.5 V
10
150
ps
65
250
ps
dt1
tsk1
tj1s1
tjabs11
45
-250
Guarenteed by design, not 100% tested in production.
9
ICS9148-25
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
Fall Time
Duty Cycle
Skew
Jitter
SYMBOL
RDSP 3
RDSN3
VOH3
VOL3
IOH3
IOL3
Tr3
Tf3
1
1
1
Dt3
1
Tsk3
Tj1s3
CONDITIONS
1
1
MIN
TYP
MAX UNITS
VO = VDD *(0.5)
10
24
Ω
VO = VDD *(0.5)
IOH = -30 mA
IOL = 23 mA
VOH = 2.0 V
VOL = 0.8 V
10
2.6
24
Ω
V
V
mA
mA
2.8
0.3
-62
55
0.4
-40
VOL = 0.4 V, VOH = 2.4 V
1.5
2
ns
VOH = 2.4 V, VOL = 0.4 V
1.4
2
ns
50
60
%
VT = 1.5 V
200
500
ps
VT = 1.5 V
50
150
ps
100
250
ps
40
VT = 1.5 V
1
Tjabs3
1
1
45
VT = 1.5 V
-250
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
Output Impedance
1
RDSP 4B
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
1
RDSN4B
VOH4\B
VOL4B
IOH4B
IOL4B
t r4B
1
1
MIN
VO = VDD *(0.5)
10
VO = VDD *(0.5)
IOH = -8 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
10
2
TYP
MAX UNITS
30
Ω
30
Ω
V
V
mA
mA
2.5
0.3
-25
23
0.5
-16
VOL = 0.4 V, VOH = 2.0 V
1.4
1.6
ns
VOH = 2.0 V, VOL = 0.4 V
1.2
1.6
ns
53
60
%
19
Fall Time
tf4B
Duty Cycle
1
d t4B
VT = 1.25 V
1
t jcyc-cyc4B
VT = 1.25 V
1400
VT = 1.25 V
300
400
ps
800
1000
ps
Jitter
tj1s4B
1
1
tjabs4B
1
CONDITIONS
40
VT = 1.25 V
-1000
Guarenteed by design, not 100% tested in production.
10
ps
ICS9148-25
Electrical Characteristics-REF1, 48MHz, & 24MHz
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 45 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
Fall Time
Duty Cycle
SYMBOL
RDSP 7
RDSN7
VOH7
VOL7
IOH7
IOL7
Tr7
Tf7
1
1
Dt7
1
Tj1s7
1
Tjabs7
1
1
1
MIN
10
10
2.6
40
TYP
2.75
0.3
-62
50
MAX UNITS
24
Ω
24
Ω
V
0.4
V
-40
mA
mA
VOL = 0.4 V, VOH = 2.4 V
1.4
2
ns
VOH = 2.4 V, VOL = 0.4 V
1.4
2
ns
54
55
%
VT = 1.5 V
tjcyc-cyc7
Jitter
CONDITIONS
VO = VDD *(0.5)
VO = VDD *(0.5)
IOH = -30 mA
IOL = 23 mA
VOH = 2.0 V
VOL = 0.8 V
45
VT = 1.5 V
1400
VT = 1.5 V
210
400
ps
-1000
450
1000
ps
MIN
10
10
2.6
TYP
MAX UNITS
24
Ω
24
Ω
V
0.4
V
-54
mA
mA
VT = 1.5 V
ps
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - REF0
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 45 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
Fall Time
Duty Cycle
SYMBOL
RDSP7
RDSN7
VOH7
VOL7
IOH7
IOL7
1
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -30 mA
IOL = 23 mA
VOH = 2.0 V
VOL = 0.8 V
41
2.75
0.3
-62
50
Tr7
1
VOL = 0.4 V, VOH = 2.4 V
1.8
2.2
ns
Tf7
1
VOH = 2.4 V, VOL = 0.4 V
1.8
2.2
ns
Dt7
1
54
60
%
tjcyc-cyc7
Jitter
CONDITIONS
1
Tj1s7
Tjabs71
VT = 1.5 V
1
40
VT = 1.5 V
1400
VT = 1.5 V
VT = 1.5 V
350
400
ps
900
1000
ps
-1000
Guarenteed by design, not 100% tested in production.
11
ps
ICS9148-25
General Layout Precautions:
1) Use a ground plane on the top layer
of the PCB in all areas not used by
traces.
2) Make all power traces and vias as
wide as possible to lower inductance.
Notes:
1) All clock outputs should have series
terminating resistor. Not shown in
all places to improve readibility of
diagram.
2) 47 ohm / 56pf RC termination
should be used on all over 50MHz
outputs.
3) Optional crystal load capacitors are
recommended.
Connections to VDD:
12
ICS9148-25
SSOP Package
SYMBOL
A
A1
A2
B
C
D
E
e
H
h
L
N
∝
X
COMMON DIMENSIONS
MIN.
NOM.
MAX.
.095
.101
.110
.008
.012
.016
.088
.090
.092
.008
.010
.0135
.005
.006
.0085
See Variations
.292
.296
.299
0.025 BSC
.400
.406
.410
.010
.013
.016
.024
.032
.040
See Variations
0°
5°
8°
.085
.093
.100
VARIATIONS
AC
AD
MIN.
.620
.720
D
NOM.
.625
.725
N
MAX.
.630
.730
48
56
This table in inches
Ordering Information
ICS9148F-25
Example:
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
13
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.