Integrated Circuit Systems, Inc. ICS9248- 81 Frequency Generator & Integrated Buffers General Description The ICS9248-81 is the single chip clock solution for Desktop/ Notebook designs using the SIS style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-81 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection. The SD_SEL latched input allows the SDRAM frequency to follow the CPUCLK frequency(SD_SEL=1) or other clock frequencies (SD_SEL=0) Block Diagram Features Generates the following system clocks: - 3 CPU(2.5V/3.3V) up to 133.3MHz. - 6 PCI(3.3V) (including 1 free-running) - 13 SDRAMs(3.3V) up to 133.3MHz. - 3 REF (3.3V) @ 14.318MHz - 1 clock @ 24/14.3 MHz selectable output for SIO - 1 Fixed clock at 48MHz (3.3V) - 1 IOAPIC @ 2.5V / 3.3V Skew characteristics: - CPU CPU<175ps - SDRAM SDRAM < 250ps - CPUSDRAM < 500ps - CPU(early) PCI : 1-4ns (typ. 3ns) - PCI PCI <500ps Supports Spread Spectrum modulation ±0.25 & ±0.5% center spread Serial I2C interface for Power Management, Frequency Select, Spread Spectrum. Efficient Power management scheme through PCI, SDRAM, CPU STOP CLOCKS and PD#. Uses external 14.318MHz crystal 48 pin 300mil SSOP. Pin Configuration Power Groups VDDREF = REF [2:0], X1, X2 VDDPCI = PCICLK_F, PCICLK [4:0] VDDSD/C = SDRAM [11:0], supply for PLL core, 24 MHz, 48MHz VDD/CPU = CPUCLK [3:1] VDDLAPIC = IOAPIC GNDFIX = Ground for fixed clock PLL and output buffers 9248-81 Rev E 10/12/99 48-Pin SSOP * Internal Pull-up Resistor of 120K to 3.3V on indicated inputs Pentium is a trademark of Intel Corporation I2C is a trademark of Philips Corporation ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9248 -81 Pin Descriptions Pin number Pin name Type Description 1 VDDR/X REF0 Mode Power Output Input Isolated 3.3 V power for crystal & reference 3.3V, 14.318 MHz reference clock output. Function select pin, 1=desk top mode, 0=mobile mode. Latched input. GND Power 3.3 V Ground X1 X2 VDDPCI FS1 PCICLK_F PCICLK 0 FS2 PCICLK [4:1] SDRAM 12, SDRAM [7:0] SDRAM 11 Input Output Power Input Output Output Input Output 14.318 MHz crystal input 14.318 MHz crystal output 3.3 V power for the PCI clock outputs Logic input frequency select bit. Input latched at power-on. 3.3 V free running PCI clock output, will not be stopped by the PCI_STOP# 3.3 V PCI clock outputs, generating timing requirements for Pentium II Logic input frequency select bit. Input latched at power-on. 3.3 V PCI clock outputs, generating timing requirements for Pentium II Output SDRAM clock outputs. Frequency is selected by SD-Sel latched input. Output CPU_STOP# Input SDRAM 10 Output PCI-STOP# Input VDDSD/C SDRAM 9 Power Output SDRAM_STOP# Input SDRAM 8 Output PD# Input SDATA SCLK Input Input SEL24_14# Input SIO FS0 Output Input 48 MHz Output VDDSDR CPUCLK [3:1] VDDLCPU REF2 Power 0utput Power Output CPU3.3#_2.5 Input GNDL REF1 SD_SEL IOAPIC VDDLAPIC Power Output Input Output Power SDRAM clock outputs. Frequency is selected by SD-Sel latched input. Asynchronous active low input pin used to stop the CPUCLK in low state, all other clocks will continue to run. The CPUCLK will have a "Turnon" latency of at least 3 CPU clocks. SDRAM clock outputs. Frequency is selected by SD-SEL latched input. Synchronous active low input used to stop the PCICLK in a low state. It will not effect PCICLK_F or any other outputs. 3.3 V power for SDRAM outputs and core SDRAM clock outputs. Frequency is selected by SD-Sel latched input. Asynchronous active low input used to stop the SDRAM in a low state. It will not effect any other outputs. SDRAM clock outputs. Frequency is selected by SD-Sel latched input. Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. Data input for I 2C serial input. Clock input of I 2C input This input pin controls the frequency of the SIO. If logic 0 at power on SIO=14.318 MHz . If logic 1 at power-on SIO=24MHz. Super I/O output. 24 or 14.318 MHz. Selectable at power-up by SEL24_14MHz Logic input frequency select bit. Input latched at power-on. 3.3 V 48 MHz clock output, fixed frequency clock typically used with USB devices 3.3 V power for SDRAM outputs 2.5 V CPU and Host clock outputs 2.5 V power for CPU 3.3V, 14.318 MHz reference clock output. This pin selects the operating voltage for the CPU. If logic 0 at power on CPU=3.3 V and if logic 1 at power on CPU=2.5 V operating voltage. 2.5 V Ground for the IOAPIC or CPU 3.3V, 14.318 MHz reference clock output. This input pin controls the frequency of the SDRAM. 2.5V fixed 14.318 MHz IOAPIC clock outputs 2.5 V power for IOAPIC 21,2 3,9,16,22, 27,33,39 4 5 6,14 71,2 81,2 13, 12, 11, 10 15,28,29,31,32, 34,35,37,38 17 1 18 1 19 20 1 21 1 23 24 25 26 1,2 1,2 30,36 40,41,43 42 44 1,2 45 46 1,2 47 48 Notes: 1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low. 2 ICS9248-81 Mode Pin - Power Management Input Control MODE, Pin 2 (Latched Input) 0 1 Pin 17 Pin 18 Pin 20 Pin 21 CPU_STOP# (INPUT) SDRAM 11 (OUTPUT) PCI_STOP# (INPUT) SDRAM 10 (OUTPUT) SDRAM_STOP# (INPUT) SDRAM9 (OUTPUT) PD# (INPUT) SDRAM8 (OUTPUT) Power Management Functionality PD# CPU_STOP# PCI_STOP# SDRAM_STOP PCICLK (0:4) SDRAM (0:12) PCICLK_F CPUCLK Crystal OSC VCO Stopped Low Running Stopped Low Stopped Low Running Stopped Low Running Stopped Low Running Stopped Low Running Running Running Running Running Running Running Running Running Running Stopped Low Running Running Running Running Running Running Running Running Running Running Running Running 0 X X X 1 1 1 1 Stopped Low Running 1 1 1 0 Running 1 1 0 1 1 1 0 0 1 0 1 1 Running Running Running 1 0 1 0 Running Stopped Low Running 1 0 0 1 Running Running 1 0 0 0 Stopped Low Running Stopped Low Stopped Low Stopped Low Stopped Low Stopped Low Stopped Low Stopped Low Stopped Low CPU 3.3#_2.5V Buffer selector for CPUCLK drivers. CPU3.3#_2.5 Input level (Latched Data) Buffer Selected for operation at: 1 2.5V VDD 0 3.3V VDD 3 ICS9248 -81 Functionality VDD1, 2, 3, 4 = 3.3V±5%, VDDL = 2.5V ±5% or 3.3 ±5%, TA= 0 to 70°C Crystal (X1, X2) = 14.31818MHz SD_SEL FS2 FS1 FS0 CPU MHZ SDRAM MHZ PCI MHZ REF, IOAPIC MHZ 0 0 0 0 90.00 90.00 30.00 14.318 0 0 0 1 66.70 100.05 33.35 14.318 0 0 1 0 95.00 63.33 31.66 14.318 0 0 1 1 100.00 66.66 33.33 14.318 0 1 0 0 100.00 75.00 30.00 14.318 0 1 0 1 112.00 74.66 37.33 14.318 0 1 1 0 124.00 82.66 31.00 14.318 0 1 1 1 133.30 88.86 33.32 14.318 1 0 0 0 66.70 66.70 33.35 14.318 1 0 0 1 75.00 75.00 30.00 14.318 1 0 1 0 83.30 83.30 33.32 14.318 1 0 1 1 95.00 95.00 31.66 14.318 1 1 0 0 100.00 100.00 33.33 14.318 1 1 0 1 112.00 112.00 37.33 14.318 1 1 1 0 124.00 124.00 31.00 14.318 1 1 1 1 133.30 133.30 33.33 14.318 4 ICS9248-81 General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit How to Write: Controller (Host) Start Bit Address D2(H) ICS (Slave/Receiver) How to Read: Controller (Host) Start Bit Address D3(H) ACK Dummy Command Code ACK ICS (Slave/Receiver) ACK Byte Count Dummy Byte Count ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK Stop Bit Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Byte 5 Byte 5 Stop Bit Notes: 1. 2. 3. 4. 5. 6. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 5 ICS9248 -81 Serial Configuration Command Bitmap Byte 0: Functionality and frequency select register (Default = 0) Bit Bit 7 PWD Description 0 - ±0.25% Center Spread Spectrum 1 - ±0.5% Center Spread Spectrum Bit (2, 6:4) CPUCLK SDRAM 1 PCICLK 0000 90.00 30.00 90.00 0001 66.70 33.35 100.05 0010 95.00 31.66 63.33 0011 100.00 33.33 66.66 0100 100.00 30.00 75.00 0101 112.00 37.33 74.66 0110 124.00 31.00 82.66 Bit 0111 133.30 33.32 88.86 (2, 6:4) 1000 66.70 33.35 66.70 1001 75.00 30.00 75.00 1010 83.30 33.32 83.30 1011 95.00 31.66 95.00 1100 100.00 33.33 100.00 1101 112.00 37.33 112.00 1110 124.00 31.00 124.00 1111 133.30 33.33 133.30 hardware select, latched inputs Bit 3 10 -- FFrreeqquueennccyy iiss sseelleecctteedd bbyy B it 2, 6:4 al Bit 1 10 -- SNporrem ad spectrum enabled Bit 0 10 -- TRruisntnaitnegall outputs Note 1: Default at power-up will be for latched logic inputs to define frequency. Note 2: PWD = Power-Up Default 6 XXXX Note 1 0 1 0 ICS9248-81 Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 40 41 43 - PWD 1 1 1 1 1 1 1 X Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Description (Reserved) (Reserved) (Reserved) (Reserved) CPUCLK3 CPUCLK2 CPUCLK1 FS0# Notes: 1. Inactive means outputs are held LOW and are disabled from switching. Pin # 28 29 31 32 34 35 37 38 PWD 1 1 1 1 1 1 1 1 Description SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD 1 X 1 1 X 1 1 1 Pin # 25 26 15 17 18 20 21 PWD 1 1 1 1 1 1 1 1 Description (Reserved) 24/14MHz 48MHz SDRAM12 SDRAM11 SDRAM10 SDRAM9 SDRAM8 Notes: 1. Inactive means outputs are held LOW and are disabled from switching. Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable) Pin # 47 44 46 2 Description FS1# PCICLK_F (Reserved) PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 Byte 4: SDRAM Active/Inactive Register (1 = enable, 0 = disable) Notes: 1. Inactive means outputs are held LOW and are disabled from switching. Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD X 1 1 1 1 1 1 1 Notes: 1. Inactive means outputs are held LOW and are disabled from switching. Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 7 13 12 11 10 8 Description (Reserved) FS2# (Reserved) IOAPIC SD_SEL# REF2 REF1 REF0 Notes: 1. Inactive means outputs are held LOW and are disabled from switching. 7 ICS9248 -81 CPU_STOP# Timing Diagram CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS9248-81. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks. Notes: 1. All timing is referenced to the internal CPU clock. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPU clocks inside the ICS9248-81. 3. All other clocks continue to run undisturbed. (including SDRAM outputs). 8 ICS9248-81 SDRAM_STOP# Timing Diagram SDRAM_STOP# is an sychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. SDRAM_STOP# is synchronized by the ICS9248-81. All other clocks will continue to run while the SDRAM clocks are disabled. The SDRAM clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. Notes: 1. All timing is referenced to the internal CPU clock. 2. SDRAM is an asynchronous input and metastable conditions may exist. This signal is synchronized to the SDRAM clocks inside the ICS9248-81. 3. All other clocks continue to run undisturbed. 9 ICS9248 -81 PCI_STOP# Timing Diagram PCI_STOP# is an synchronous input to the ICS9248-81. It is used to turn off the PCICLK (0:4) clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-81 internally. The minimum that the PCICLK (0:4) clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK (0:4) clocks. PCICLK (0:4) clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK (0:4) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock. Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9248. 3. All other clocks continue to run undisturbed. 4. CPU_STOP# is shown in a high (true) state. 10 ICS9248-81 Shared Pin Operation Input/Output Pins header may be used. These figures illustrate the optimal PCB physical layout options. These configuration resistors are of such a large ohmic value that they do not effect the low impedance clock signals. The layouts have been optimized to provide as little impedance transition to the clock signal as possible, as it passes through the programming resistor pad(s). The I/O pins designated by (input/output) on the ICS924881 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 4-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm(10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figs. 1 and 2 show the recommended means of implementing this function. In Fig. 1 either one of the resistors is loaded onto the board (selective stuffing) to configure the devices internal logic. Figs. 2a and b provide a single resistor loading option where either solder spot tabs or a physical jumper Fig. 1 11 ICS9248 -81 Fig. 2a Fig. 2b 12 ICS9248-81 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V GND 0.5 V to VDD +0.5 V 0°C to +70°C 65°C to +150°C 115°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN Input High Voltage VIH 2 Input Low Voltage VIL VSS-0.3 Input High Current IIH VIN = VDD Input Low Current IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 VIN = 0 V; Inputs with pull-up resistors -200 Input Low Current IIL2 Operating IDD3.3OP66 CL = 0 pF; Select @ 66MHz Supply Current IDD3.3OP100 CL = 0 pF; Select @ 100MHz Power Down IDD3.3PD CL = 0 pF; With input address to Vdd or GND Supply Current VDD = 3.3 V; 11 Input frequency Fi Input Capacitance1 CIN Logic Inputs CINX X1 & X2 pins 27 Transition Time1 Ttrans To 1st crossing of target Freq. Clk Stabilization1 TSTAB From VDD = 3.3 V to 1% target Freq. tCPU-SDRAM1 VT = 1.5 V Skew1 tCPU-PCI1 VT = 1.5 V 1 TYP 0.1 2.0 -100 60 66 70 14.318 36 200 3 MAX UNITS VDD+0.3 V 0.8 V µA 5 µA µA 180 mA 180 mA µA 600 16 5 45 3 3 500 4 1 Guaranteed by design, not 100% tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Operating Supply Current 1 Skew 1 SYMBOL IDD2.5OP66 IDD2.5OP100 tCPU-SDRAM2 tCPU-PCI2 CONDITIONS CL = 0 pF; Select @ 66.8 MHz CL = 0 pF; Select @ 100 MHz VT = 1.5 V; VTL = 1.25 V VT = 1.5 V; VTL = 1.25 V Guaranteed by design, not 100% tested in production. 13 MIN 1 TYP 16 23 200 3 MAX UNITS 72 mA 100 mA 500 ps 4 ns MHz pF pF ms ms ps ns ICS9248 -81 Electrical Characteristics - CPUCLK TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output High Voltage VOH1a IOH = -12.0 mA IOL = 12 mA Output Low Voltage VOL1a Output High Current IOH1a VOH = 2 V Output Low Current IOL1a VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V Rise Time tr1a1 1 Fall Time tf1a VOH = 2.4 V, VOL = 0.4 V 1 VT = 1.5 V Duty Cycle dt1a VT = 1.5 V Skew tsk1a1 1 VT = 1.5 V Jitter, Cycle-to-cycle tjcyc-cyc1a 1 VT = 1.5 V Jitter, One Sigma tj1s1a VT = 1.5 V tjabs1a1 Jitter, Absolute MIN 2.4 TYP 2.6 0.2 -41 37 1.5 1.5 48 30 150 40 140 MAX UNITS V 0.4 V -19 mA mA 2 ns 2 ns 55 % 175 ps 250 ps 150 ps +250 ps TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP IOH = -12.0 mA 2 2.3 Output High Voltage VOH1B Output Low Voltage VOL1B IOL = 12 mA 0.2 Output High Current IOH1B VOH = 1.7 V -41 Output Low Current IOL1B VOL = 0.7 V 19 37 1 Rise Time tr1B VOL = 0.4 V, VOH = 2.0 V 1.25 VOH = 2.0 V, VOL = 0.4 V 1 Fall Time tf1B1 1 VT = 1.25 V 45 48 Duty Cycle dt1B VT = 1.25 V 30 Skew tsk1B1 1 VT = 1.25 V 150 Jitter, Cycle-to-cycle tjcyc-cyc1B 1 VT = 1.25 V 40 Jitter, One Sigma tj1s1B tjabs1B1 VT = 1.25 V Jitter, Absolute -250 140 MAX UNITS V 0.4 V -19 mA mA 1.6 ns 1.6 ns 55 % 175 ps 250 ps 150 ps +250 ps 19 45 -250 1 Guaranteed by design, not 100% tested in production. Electrical Characteristics - CPUCLK 1 Guaranteed by design, not 100% tested in production. 14 ICS9248-81 Electrical Characteristics - PCICLK TA = 0 - 70C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5%; CL = 30 pF PARAMETER SYMBOL CONDITIONS Output High Voltage VOH2 IOH = -11 mA IOL = 9.4 mA Output Low Voltage VOL2 Output High Current IOH2 VOH = 2.0 V Output Low Current IOL2 VOL = 0.8 V Rise Time Fall Time 1 1 Duty Cycle 1 1 Skew Jitter, Cycle-to-cycle 1 Jitter, One Sigma Jitter, Absolute1 1 MIN 2.4 16 TYP 3.1 0.1 -62 57 MAX UNITS V 0.4 V -22 mA mA tr2 VOL = 0.4 V, VOH = 2.4 V 1.5 2.6 ns tf2 VOH = 2.4 V, VOL = 0.4 V 1.1 2 ns dt2 VT = 1.5 V 50 55 % tsk2 tjcyc-cyc2 VT = 1.5 V VT = 1.25 V 140 250 500 500 ps ps tj1s2 VT = 1.5 V 17 150 ps tjabs2 VT = 1.5 V -350 70 350 ps MIN 2.4 TYP 3.1 0.1 -62 57 45 Guaranteed by design, not 100% tested in production. Electrical Characteristics -SDRAM TA = 0 - 70C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5%; CL = 30 pF PARAMETER SYMBOL CONDITIONS Output High Voltage VOH3 IOH = -11 mA Output Low Voltage VOL3 IOL = 9.4 mA Output High Current IOH3 VOH = 2.0 V Output Low Current IOL3 VOL = 0.8 V Rise Time1 tr3 Fall Time1 tf3 dt3a dt3b dt3c tsk3a tsk3b tsk3c Duty Cycle1 Skew1 (Window) Jitter, Cycle-to-cycle 1 Jitter, One Sigma Jitter, Absolute1 1 tjcyc-cyc3 16 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V; Divide by 2 seclects<124MHz VT = 1.5 V; Divide by 3 seclects VT = 1.5 V; Selects >= 124MHz VT = 1.5 V; SDRAM0,8,9 VT = 1.5 V; All except SDRAM8 and 9 VT = 1.5 V; All SDRAMs VT = 1.25 V tj1s3 VT = 1.5 V tjabs3 VT = 1.5 V 47% 45 43 -250 Guaranteed by design, not 100% tested in production. 15 MAX UNITS V 0.4 V -22 mA mA 1.5 2.6 ns 1.1 ns 50 2.2 57% 55 53 140 250 200 250 400 500 ps 17 150 ps 70 250 ps % ps ICS9248 -81 Electrical Characteristics - REF/48MHz/SIO TA = 0 - 70C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5%; CL = 20 pF PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time 1 1 Duty Cycle 1 Jitter, One Sigma Jitter, Absolute 1 1 1 SYMBOL VOH4 VOL4 IOH4 IOL4 CONDITIONS IOH = -12 mA IOL = 10 mA VOH = 2.0 V VOL = 0.8 V MIN 2.4 16 TYP 2.6 0.3 -32 25 MAX UNITS V 0.4 V -22 mA mA tr4 VOL = 0.4 V, VOH = 2.4 V 2 4 ns tf4 VOH = 2.4 V, VOL = 0.4 V 1.9 4 ns d t4 VT = 1.5 V 53 55 % tj1s4 VT = 1.5 V 500 650 ps tjabs4 VT = 1.5 V 1 ns 45 -1 Guaranteed by design, not 100% tested in production. 16 ICS9248-81 General Layout Precautions: 1) Use a ground plane on the top layer of the PCB in all areas not used by traces. Ferrite Bead VDD 2) Make all power traces and ground traces as wide as the via pad for lower inductance. Ferrite Bead C2 22µF/20V Tantalum 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 VDD C3 C1 Notes: 1) All clock outputs should have a series terminating resistor, and a 20pF capacitor to ground between the resistor and clock pin. Not shown in all places to improve readibility of diagram. C2 22µF/20V Tantalum C1 2.5V Power Route 1 C4 Clock Load C3 3.3V Power Route 2) Optional crystal load capacitors are recommended. They should be included in the layout but not inserted unless needed. Connections to VDD: 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 Ground 3.3V Power Route = Routed Power = Ground Connection Key (component side copper) = Ground Plane Connection = Power Route Connection = Solder Pads = Clock Load 17 ICS9248 -81 SYMBOL A A1 A2 B C D E e H h L N µ X COMMON DIMENSIONS MIN. NOM. MAX. .095 .101 .110 .008 .012 .016 .088 .090 .092 .008 .010 .0135 .005 .010 See Variations .292 .296 .299 0.025 BSC .400 .406 .410 .010 .013 .016 .024 .032 .040 See Variations 0° 5° 8° .085 .093 .100 VARIATIONS MIN. .620 AC D NOM. .625 N MAX. .630 48 SSOP Package Ordering Information ICS9248yF-81 Example: ICS XXXX y F - PPP Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 18 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.