Integrated Circuit Systems, Inc. ICS9250-23 Frequency Generator & Integrated Buffers for Celeron & PII/III™ Recommended Application: 810/810E type chipset Output Features: • 2 - CPUs @ 2.5V, up to 166MHz. • 13 - SDRAM @ 3.3V, up to 166MHz. • 2 - 3V66 @ 3.3V, 2x PCI MHz. • 8 - PCI @3.3V. • 1 - 48MHz, @3.3V fixed. • 1 - 24MHz @ 3.3V • 2 - REF @3.3V, 14.318MHz. Pin Configuration Features: • Up to 166MHz frequency support • Support power management through PD#. • Spread spectrum for EMI control (± 0.25%) center spread. • Uses external 14.318MHz crystal • FS pins for frequency select Key Specifications: • CPU Output Jitter: <250ps • IOAPIC Output Jitter: <500ps • 48MHz, 3V66, PCI Output Jitter: <500ps • Ref Output Jitter. <1000ps • CPU Output Skew: <175ps • PCI Output Skew: <500ps • 3V66 Output Skew <175ps • For group skew timing, please refer to the Group Timing Relationship Table. 56-Pin 300 mil SSOP 1. These pins will have 2X drive strength. * 120K ohm pull-up to VDD on indicated inputs. Block Diagram Power Groups GNDREF, VDDREF = REF, Crystal GND3V66, VDD3V66 = 3V66 GNDPCI, VDDPCI = PCICLKs GNDCOR, VDDCOR = PLLCORE GND48, VDD48 = 48 GNDSDR, VDDSDR = SDRAM GNDLCPU, VDDLCPU = CPUCLK GNDLPCI, VDDLAPIC = IOAPIC 9250-23 Rev A 4/3/01 Third party brands and names are the property of their respective owners. ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9250-23 General Description The ICS9250-23 is a single chip clock solution for desktop designs using the 810/810E style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-23 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection. Pin Configuration PIN P I N NA M E NUMBER 1 REF1 2, 9, 10, 18, 25, VDD 32, 33, 37, 45 TYPE DESCRIPTION OUT 3.3V, 14.318MHz reference clock output. PWR 3.3V power supply. 3 X1 IN 4 X2 OUT Crystal input, has internal load cap (33pF) and feedback resistor from X2. Crystal output, nominally 14.318MHz. Has internal load cap (33pF) GND PWR Ground pins for 3.3V supply. 3V66 [1:0] OUT 3 . 3 V F i xe d 6 6 M H z c l o c k o u t p u t s f o r H U B . 1 OUT IN 3.3V PCI clock outputs, with Synchronous CPUCLKS. Logic input frequency select bit. Input latched at power on. PCICLK11 OUT 3.3V PCI clock outputs, with Synchronous CPUCLKS. 5, 6, 14, 21, 28, 29, 36, 41, 49 8, 7 11 12 20, 19, 17, 16, 15, 13 PCICLK0 FS0 FS1 PCICLK [7:2] IN OUT Logic input frequency select bit. Input latched at power on. 3.3V PCI clock outputs, with Synchronous CPUCLKS. 22 PD# IN Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. 23 SCLK IN Clock input of I2C input. 24 SDATA I/O Data pin for I2C circuitry 5V tolerant. 48MHz OUT 34 35 FS3 FS2 IN IN 3 . 3 V F i xe d 4 8 M H z c l o c k o u t p u t f o r U S B . Logic input frequency select bit. Input latched at power on. Logic input frequency select bit. Input latched at power on. 24MHz OUT 3.3V fixed 24MHz output. 38 26, 27, 30, 31, 39, 40, 42, 43, 44, 46, 47, 48 50 SDRAM_F OUT 3.3V free running 100MHz SDRAM not affected by I2C. SDRAM [11:0] OUT 3.3V output running 100MHz. All SDRAM outputs can be turned off t h r o u g h I 2C . GNDL PWR Ground for 2.5V power supply for CPU & APIC. 51, 52 CPUCLK [1:0] OUT 2.5V Host bus clock output. Output frequency derived from FS pins. 53, 55 54 VDDL IOAPIC FS4 PWR OUT IN 2.5V power suypply for CPU, IOAPIC. 2.5V clock outputs running at 16.67MHz. Logic input frequency select bit. Input latched at power on. REF01 OUT 3.3V, 14.318MHz reference clock output. 56 Third party brands and names are the property of their respective owners. 2 ICS9250-23 Frequency Selection FS4 FS3 FS2 FS1 FS0 CPU MHz SDRAM MHz 3V66 MHz PCI MHz IOAPIC MHz 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 69.00 70.00 71.00 66.90 72.00 75.00 76.60 85.00 68.00 74.00 140.00 133.33 150.00 155.00 166.00 166.00 111.77 104.78 109.51 100.90 117.00 123.75 133.33 142.50 136.00 140.00 143.00 133.90 146.67 149.33 153.30 166.67 103.50 105.00 106.50 100.35 108.00 112.50 114.90 127.50 102.00 111.00 140.00 133.33 150.00 155.00 166.00 166.00 111.77 104.78 109.51 100.90 117.00 123.75 133.33 142.50 102.25 105.00 107.50 100.68 110.00 112.00 115.29 125.32 69.00 70.00 71.00 66.90 72.00 75.00 76.60 85.00 68.00 74.00 70.00 66.67 75.00 77.50 83.00 111.00 74.52 69.86 73.01 67.27 78.50 82.50 88.89 95.00 68.50 70.00 72.00 67.45 73.33 74.67 77.24 83.34 34.50 35.00 35.50 33.45 36.00 37.50 38.40 42.50 34.00 37.00 35.00 33.33 37.50 38.75 41.50 55.80 37.26 34.93 36.50 33.63 39.25 41.25 44.44 47.50 34.25 35.00 36.00 33.73 36.67 37.33 38.62 41.67 17.25 17.50 17.75 16.73 18.00 18.75 19.20 21.25 17.00 18.50 17.50 16.67 18.75 19.38 22.75 27.90 18.63 17.46 18.25 16.82 19.63 20.62 22.22 23.75 17.13 17.50 18.00 16.86 18.33 18.67 19.30 20.83 Clock Enable Configuration PD# CPUCLK SDRAM IOAPIC 66MHz PCICLK REF, 48MHz Osc VCOs 0 LOW LOW LOW LOW LOW LOW OFF OFF 1 ON ON ON ON ON ON ON ON Third party brands and names are the property of their respective owners. 3 ICS9250-23 Power Down Waveform Note 1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the output clocks are driven Low on their next High to Low tranistiion. 2. Power-up latency <3ms. 3. Waveform shown for 100MHz Third party brands and names are the property of their respective owners. 4 ICS9250-23 Shared Pin Operation Input/Output Pins Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. When no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, then only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used both to provide the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Via to VDD Programming Header 2K W Via to Gnd Device Pad 8.2K W Clock trace to load Series Term. Res. Fig. 1 Third party brands and names are the property of their respective owners. 5 ICS9250-23 General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: How to Read: • • • • • • • • • • • • • • • • Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 • ICS clock will acknowledge each byte one at a time. • Controller (host) sends a Stop bit Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit How to Write: Controller (Host) Start Bit Address D2(H) ICS (Slave/Receiver) How to Read: Controller (Host) Start Bit Address D3(H) ACK Dummy Command Code ACK ICS (Slave/Receiver) ACK Byte Count Dummy Byte Count ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK Stop Bit Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Byte 5 Byte 5 Stop Bit Notes: 1. 2. 3. 4. 5. 6. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. Third party brands and names are the property of their respective owners. 6 ICS9250-23 Byte 0: Functionality and frequency select register (Default=0) (1 = enable, 0 = disable) Bit Bit (2,7:4) Bit (2, 7:4) Bit 3 Bit 1 Bit 0 PWD Description CPUCLK MHz SDRAM MHz 3V66 MHz PCICLK IOAPIC MHz 0 0 0 0 0 69.00 103.50 69.00 34.50 17.25 0 0 0 0 1 70.00 105.00 70.00 35.00 17.50 0 0 0 1 0 71.00 106.50 71.00 35.50 17.75 0 0 0 1 1 66.90 100.35 66.90 33.45 16.73 0 0 1 0 0 72.00 108.00 72.00 36.00 18.00 0 0 1 0 1 75.00 112.50 75.00 37.50 18.75 0 0 1 1 0 76.60 114.90 76.60 38.40 19.20 0 0 1 1 1 85.00 127.50 85.00 42.50 21.25 0 1 0 0 0 68.00 102.00 68.00 34.00 17.00 0 0 0 0 0 1 1 1 1 1 0 0 0 1 1 0 1 1 0 0 1 0 1 0 1 74.00 140.00 133.33 150.00 155.00 111.00 140.00 133.33 150.00 155.00 74.00 70.00 66.67 75.00 77.50 37.00 35.00 33.33 37.50 38.75 18.50 17.50 16.67 18.75 19.38 83.00 111.00 74.52 69.86 73.01 67.27 78.50 82.50 88.89 95.00 68.50 70.00 72.00 67.45 73.33 74.67 77.24 83.34 41.50 55.80 37.26 34.93 36.50 33.63 39.25 41.25 44.44 47.50 34.25 35.00 36.00 33.73 36.67 37.33 38.62 41.67 22.75 27.90 18.63 17.46 18.25 16.82 19.63 20.62 22.22 23.75 17.13 17.50 18.00 16.86 18.33 18.67 19.30 20.83 0 1 1 1 0 166.00 166.00 0 1 1 1 1 166.00 166.00 1 0 0 0 0 111.77 111.77 1 0 0 0 1 104.78 104.78 1 0 0 1 0 109.51 109.51 1 0 0 1 1 100.90 100.90 1 0 1 0 0 117.00 117.00 1 0 1 0 1 123.75 123.75 1 0 1 1 0 133.33 133.33 1 0 1 1 1 142.50 142.50 1 1 0 0 0 136.00 102.25 1 1 0 0 1 140.00 105.00 1 1 0 1 0 143.00 107.50 1 1 0 1 1 133.90 100.68 1 1 1 0 0 146.67 110.00 1 1 1 0 1 149.33 112.00 1 1 1 1 0 153.30 115.29 1 1 1 1 1 166.67 125.32 0-Frequency is selected by hardware select, latched inputs 1- Frequency is selected by Bit 2,6:4 0- Normal 1- Spread spectrum enable ± 0.25% Center Spread 0- Running 1- Tristate all outputs Notes: 1. Default at power-up will be for latched logic inputs to define frequency, as diplayed by Bit 3. Third party brands and names are the property of their respective owners. 7 00100 Note 1 0 1 0 ICS9250-23 Byte 2: Control Register (1 = enable, 0 = disable) Byte 1: Control Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 35 34 38 PWD 0 0 0 1 1 1 1 1 Description FS3# FS0# FS2# 24MHz (Reserved) 48MHz (Reserved) SDRAM_F Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 3: Control Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 20 19 17 16 15 13 12 11 PWD 1 1 1 1 1 1 1 1 Pin# 39 40 42 43 44 46 47 48 PWD 1 1 1 1 1 1 1 1 Description SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0 Byte 4: Control Register (1 = enable, 0 = disable) Description PCICLK7 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 7 8 54 51 52 PWD 1 1 1 0 1 0 1 1 Description (Reserved) 3V66_0 3V66_1 FS4# IOAPIC FS1# CPUCLK1 CPUCLK0 Byte 5: Control Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 26 27 30 31 PWD 1 1 1 1 1 1 1 1 Description (Reserved) (Reserved) (Reserved) (Reserved) SDRAM11 SDRAM10 SDRAM9 SDRAM8 Notes: 1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. PWD = Power on Default Third party brands and names are the property of their respective owners. 8 ICS9250-23 Absolute Maximum Ratings Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 V 3.6V GND –0.5 V to VDD +0.5 V 0°C to +70°C –65°C to +150°C 115°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Group Timing Relationship Table Group CPU 66MHz CPU 100MHz CPU 133MHz Offset Tolerance Offset Tolerance Offset Tolerance CPU to SDRAM 2.5ns 500ps 5.0ns 500ps 0.0ns 500ps CPU to 3V66 7.5ns 500ps 5.0ns 500ps 0.0ns 500ps SDRAM to 3V66 0.0ns 500ps 0.0ns 500ps 0.0ns 500ps 3V66 to PCI 1.5-3.5ns 500ps 1.5-3.5ns 500ps 1.5-3.5ns 500ps USB & DOT Asynch N/A Asynch N/A Asynch N/A Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input High Voltage VIH 2 VDD+0.3 V Input Low Voltage VIL VSS-0.3 0.8 V Input High Current IIH VIN = VDD -5 5 µA Input Low Current IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 µA Input Low Current IIL2 VIN = 0 V; Inputs with pull-up resistors -200 µA Operating IDD3.3V Cl = 0 pF; Select @ 66M 119 280 mA Supply Current IDDL2.5V Cl = 0 pF; Select @ 66M 3 25 Power Down Current IDD3.3VPD Cl = 0 pF; With Input to Vdd or Gnd µA 600 Input frequency Fi VDD = 3.3 V 14.318 MHz Input Capacitance1 CIN Logic Inputs 5 pF CINX X1 & X2 pins 27 45 pF Transition Time1 TTrans To 1st crossing of target Freq. 3 ms Settling Time1 TS From 1st crossing to 1% target Freq. 1 3 ms Clk Stabilization1 TStab From VDD = 3.3 V to 1% target Freq. 3 ms TPZH,TPZL output enable delay(all outputs) 1 10 ns Delay1 TPHZ,TPLZ output disable delay(all outputs) 1 10 ns 1 Guaranteed by design, not 100% tested in production. Third party brands and names are the property of their respective owners. 9 ICS9250-23 Electrical Characteristics - CPUCLK TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless Electrical Characteristics - IOAPIC PARAMETER SYMBOL CONDITIONS TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) Output High Voltage VOH2B IOH = -1 mA PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Low Voltage VOL2B IOL = 1 mA Output High Voltage VOH4B IOH = -18 mA 2.4 2.9VOH V @MIN = 1 V IOH2B 0.25 Output High Current Output Low Voltage VOL4B IOL = 9 mA 0.4 V VOH@MAX = 2.375V I Output High Current VOH = 2.0 V -58VOL -22 = 1.2mA OH4B V @MIN Output Low Current VOL@MIN = 1.0 V 31IOL2B 34.1V =0.3V I Output Low Current mA OL@MAX OL4B VOL@MAX =0.2V 7.85 31 VOL = 1 V, VOH = 2.0 V Rise Time tr2B1 Rise Time1 Tr4B VOL = 0.4 V, VOH = 2.0 V 0.4t 1 1.28V = 2.0 2 V, V ns= 0.4 V Fall Time f2B OH OL 1 Fall Time Tf4B VOH = 2.0 V, VOL = 0.4 V 0.4d 1 1.2V = 1.25 1.6 V ns Duty Cycle t2B T 1 Duty Cycle Dt4B VT = 1.25 V 45tsk2B1 49.6VT = 1.25 55 V % Skew 1 432 Jitter, Cycle-to-Cycle tjcyc-cyc4B1 VT = 1.25 V 750 V (CPU ps 133, SDRAM 100 tjcyc-cyc2B VT = 1.25 Jitter, Cycle-to-Cycle 1 1 Jitter, Cycle-to-Cycle tjcyc-cyc VT = 1.25 V (all other select B) Guaranteed by design, not 100% tested in production. 1 Guaranteed by design, not 100% tested in production. Third party brands and names are the property of their respective owners. 10 ICS9250-23 Electrical Characteristics - PCICLK TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 60 pF for PCI0 & PCI1, CL = 30 pF for other PCIs PARAMETER Output High Voltage Output Low Voltage SYMBOL VOH1 VOL1 Output High Current IOH1 Output Low Current IOL1 Rise Time1 tr1 VOL = 0.4 V, VOH = 2.4 V 0.5 1.65 2 ns 1 Fall Time 1 CONDITIONS IOH = -1 mA IOL = 1 mA VOH@MIN = 1 V VOH@MAX = 3.135V VOL@MIN = 1.95 V VOL@MAX =0.4V MIN 2.4 -33 38 TYP 3.25 0.03 -71 -10 74 22 MAX UNITS V 0.55 V -33 mA 30 mA tf1 VOH = 2.4 V, VOL = 0.4 V 0.5 1.53 2 ns Duty Cycle1 dt1 VT = 1.5 V 45 51.1 55 % Skew1 Jitter, Cycle-to-Cycle tsk1 tjcyc-cyc1 VT = 1.5 V VT = 1.5 V 331 185 500 500 ps ps Guaranteed by design, not 100% tested in production. Electrical Characteristics - 3V66 TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 30 pF PARAMETER Output High Voltage Output Low Voltage Output High Current IOH1 Output Low Current IOL1 Fall Time tr1 VOL = 0.4 V, VOH = 2.4 V tf1 VOH = 2.4 V, VOL = 0.4 V dt1 VT = 1.5 V tsk1 VT = 1.5 V tjcyc-cyc1 VT = 1.5 V 1 1 Skew Jitter 1 11 VOL@MAX =0.4V 1 Duty Cycle 1 CONDITIONS IOH = -1 mA IOL = 1 mA VOH@MIN = 1 V VOH@MAX = 3.135V VOL@MIN = 1.95 V 1 Rise Time Third party brands and names are the property of their respective owners. SYMBOL VOH1 VOL1 ,Cycle-to-Cycle Guaranteed by design, not 100% tested in production. ICS9250-23 Electrical ElectricalCharacteristics Characteristics - 48MHz, - 24M Hz REF TA = 0 - 70º C; C; V VDD = 3.3 3.3 V V +/-5%, +/-5%,VVDDL = 2.5 2.5 VV+/-5%; +/-5%;CCLL==20 20pF pF(unless (unle DD = DDL = PARAMETER PA RA M ETER Output Output High Voltage Output Output Low Voltage SYMBOL SYM BOL V VOOH5 H5 V VOOL5 L5 Output High Current Output Current IIOOH5 H5 Output Low Current Output IIOOL5 L5 11 Ris Risee Time Time 11 Fall Time Time Duty Duty Cycle 1 CONDITIONS CONDITIONS IOOHH == -1 mA IOL = 11 mA OL = = 11 V VOH@ VOH MIN = @MIN VOH@MAX = 3.135V 3.135V 1.95 V V VOL@MIN @MIN = 1.95 VOL@MAX =0.4V ttr5 r5 VOOLL = 0.4 V, V, V VOOH = 2.4 2.4VV H = tf5 f5 VOOHH = 2.4 V, V, V VOOL = 0.4 0.4VV L = VTT == 1.5 1.5 VV VT = 1.5 V, 24MHz 24M Hz Jitter1, Cycle-to-Cycle 1 V = 1.5 V, 48MHz Guaranteed by des ign, nottjcyc-cyc5 100% tes tedT in production. Jitter1, Cycle-to-Cycle VT = 1.5 V, REF tjcyc-cyc5 11 Jitter ,Cy , Cycle-to-Cycle Jitter cle-to-Cy cle 1 Third party brands and names are the property of their respective owners. 12 ddt5 t5 ttjcy c-cyc5 jcyc-cyc5 Guaranteed by design, not 100% tested in production. ICS9250-23 Electrical Characteristics - SDRAM TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL =30 pF PARAMETER Output High Voltage Output Low Voltage SYMBOL VOH1 VOL1 Output High Current IOH1 Output Low Current IOL1 Rise Time1 tr1 VOL = 0.4 V, VOH = 2.4 V 0.4 1.25 1.6 ns 1 Fall Time 1 CONDITIONS IOH = -1 mA IOL = 1 mA VOH@MIN = 2 V VOH@MAX = 3.135V VOL@MIN = 1 V VOL@MAX =0.4V MIN 2.4 -46 54 TYP 3.28 0.03 -85 -12 63 27 MAX UNITS V 0.4 V -54 mA 53 mA tf1 VOH = 2.4 V, VOL = 0.4 V 0.4 1.53 1.6 ns Duty Cycle1 Skew dt1 tsk1 VT = 1.5 V VT = 1.5 V 45 53.2 267 55 380 % ps Jitter1, Cycle-to-Cycle tjcyc-cyc1 VT = 1.5 V 176 250 ps Guaranteed by design, not 100% tested in production. (No Skew Window is needed for Group Skew spec.) TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% 24MHz, 48MHz, REF, CPU & IOAPIC load = 20 pF; PCI, SDRAM & 3V66 load = 30 pF. Refer to Group Offset Waveform diagram for definition of transition edges. Group Skews (CPU = 66 MHz; SDRAM = 100MHz) PARAMETER SYMBOL CONDITIONS 1 T CPU @ 1.25 V, SDRAM @ 1.5 V CPU to SDRAM Skew sk1 CPU-SDRAM 1 Tsk1 CPU-3V66 CPU @ 1.25 V, 3V66 @ 1.5 V CPU to 3V66 Skew 1 T SDRAM @1.5V, 3V66 @ 1.5 V SDRAM to 3V66 Skew sk1 SDRAM-3V66 1 Tsk1 3V66-PCI 3V66 @1.5V, PCI @ 1.5 V 3V66 to PCI Skew MIN 2.0 7 -500 1.5 TYP MIN 4.5 4.5 -500 1.5 TYP 4.63 396 2.58 MAX UNITS 5.5 ns 5.5 ns 500 ps 3.5 ns MIN -500 -500 -500 1.5 TYP -322 -284 389 2.61 MAX UNITS 500 ps 500 ps 500 ps 3.5 ns 394 2.58 MAX UNITS 3.0 ns 8 ns 500 ps 3.5 ns Group Skews (CPU = 100 MHz; SDRAM = 100MHz) PARAMETER SYMBOL CONDITIONS 1 Tsk1 CPU-SDRAM CPU @ 1.25 V, SDRAM @ 1.5 V CPU to SDRAM Skew Tsk1 CPU-3V66 CPU @ 1.25 V, 3V66 @ 1.5 V CPU to 3V66 Skew1 1 T SDRAM @1.5V, 3V66 @ 1.5 V SDRAM to 3V66 Skew sk1 SDRAM-3V66 Tsk1 3V66-PCI 3V66 @1.5V, PCI @ 1.5 V 3V66 to PCI Skew1 Group Skews (CPU = 133 MHz; SDRAM = 100MHz) PARAMETER SYMBOL CONDITIONS CPU to SDRAM Skew1 Tsk1 CPU-SDRAM CPU @ 1.25 V, SDRAM @ 1.5 V Tsk1 CPU-3V66 CPU @ 1.25 V, 3V66 @ 1.5 V CPU to 3V66 Skew1 1 SDRAM to 3V66 Skew Tsk1 SDRAM-3V66 SDRAM @1.5V, 3V66 @ 1.5 V Tsk1 3V66-PCI 3V66 @1.5V, PCI @ 1.5 V 3V66 to PCI Skew1 Third party brands and names are the property of their respective owners. 13 ICS9250-23 25ns 0ns CPU 66 Period CPU/ITP/HCLK [66MHz (2.5V)] CPU 100 Period CPU/ITP/HCLK [100MHz (2.5V)] SDRAM 100 Period SDRAM [11:0, F] & DCLKWR [100MHz (3.3V)] 3V66-PCI 3V66 Link (ICH / MGCH) [66MHz (3.3V)] PCI [7:0] LPC/SIO [33MHz (3.3V)] Ref Clock [14.318MHz (3.3V)] USB [48MHz (3.3V)] APIC (CPU/MCH) [16.67MHz (2.5V)] Group Offset Waveforms Third party brands and names are the property of their respective owners. 14 50ns 75ns ICS9250-23 c N SYMBOL L E1 INDEX AREA E 1 2 h x 45° D A A A1 b c D E E1 e h L N α In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0° 8° In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° A1 -Ce N SEATING PLANE b .10 (.004) C 56 VARIATIONS D mm. MIN MAX 18.31 18.55 D (inch) MIN .720 MAX .730 Reference Doc.: JEDEC Publication 95, MO-118 10-0034 300 mil SSOP Package Ordering Information ICS9250yF-23 Example: ICS XXXX y F - PPP Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator Device Type Prefix ICS, AV = Standard Device Third party brands and names are the property of their respective owners. 15 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.