ICS952621 Integrated Circuit Systems, Inc. Programmable Timing Control Hub™ for Next Gen P4™ processor Recommended Application: CK409 48-pin part Output Features: • 2 - 0.7V current-mode differential CPU pairs • 1 - 0.7V current-mode differential CPU pairs for ITP • 1 - 0.7V current-mode differential SRC pair • 9 - PCI (33MHz), including 3 free running PCI • 1 - USB, 48MHz • 1 - DOT, 48MHz • 2 - REF, 14.318MHz • 3 - 3V66, 66.66MHz • Supports CPU clks up to 400MHz in test mode • Uses external 14.318MHz crystal • Supports undriven differential CPU, SRC pair in PD# and CPU_STOP# for power management. 1 - 3V66/VCH, selectable 48MHz or 66MHz Key Specifications: • CPU/SRC outputs cycle-cycle jitter < 125ps • 3V66 outputs cycle-cycle jitter < 250ps • PCI outputs cycle-cycle jitter < 250ps • CPU outputs skew: < 100ps • +/- 300ppm frequency accuracy on CPU & SRC clocks Functionality USB/ FS2 DOT CPU SRC 3V66 PCI REF MHz B6b5 FS_A FS_B MHz MHz MHz MHz MHz 0 0 100.00 100/200 66.66 33.33 14.318 48.00 0 1 200.00 100/200 66.66 33.33 14.318 48.00 0 1 0 133.33 100/200 66.66 33.33 14.318 48.00 1 1 166.66 100/200 66.66 33.33 14.318 48.00 0 0 200.00 100/200 66.66 33.33 14.318 48.00 0 1 400.00 100/200 66.66 33.33 14.318 48.00 1 1 0 266.66 100/200 66.66 33.33 14.318 48.00 1 1 333.33 100/200 66.66 33.33 14.318 48.00 Pin Configuration FS_A/REF1 FS_B/REF0 VDDREF X1 X2 GND PCICLK_F0 PCICLK_F1 PCICLK_F2 VDDPCI GND PCICLK0 PCICLK1 PCICLK2 PCICLK3 VDDPCI GND PCICLK4 PCICLK5 PD# 48MHz_DOT 48MHz_USB GND VDD48 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ICS952621 • Features/Benefits: • Supports tight ppm accuracy clocks for Serial-ATA • Supports spread spectrum modulation, 0 to -0.5% down spread and +/- 0.25% center spread 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDA GND IREF CPUCLKT_ITP CPUCLKC_ITP GND CPUCLKT1 CPUCLKC1 VDDCPU CPUCLKT0 CPUCLKC0 GND SRCCLKT SRCCLKC VDD VttPWR_GD# SDATA SCLK 3V66_0 3V66_1 GND VDD3V66 3V66_2 3V66_3/VCH **120KΩ pull-down 48-pin SSOP 0756A—09/10/04 ICS952621 Integrated Circuit Systems, Inc. Pin Description PIN # PIN NAME PIN TYPE 1 FS_A/REF1 I/O 2 FS_B/REF0 I/O 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 VDDREF X1 X2 GND PCICLK_F0 PCICLK_F1 PCICLK_F2 VDDPCI GND PCICLK0 PCICLK1 PCICLK2 PCICLK3 VDDPCI GND PCICLK4 PCICLK5 PWR IN OUT PWR OUT OUT OUT PWR PWR OUT OUT OUT OUT PWR PWR OUT OUT 20 PD# IN 21 22 23 24 48MHz_DOT 48MHz_USB GND VDD48 OUT OUT PWR PWR 25 3V66_3/VCH OUT 26 27 28 29 30 31 32 3V66_2 VDD3V66 GND 3V66_1 3V66_0 SCLK SDATA OUT PWR PWR OUT OUT IN I/O 33 VttPWR_GD# IN 34 VDD OUT 35 SRCCLKC OUT 36 SRCCLKT OUT 37 GND PWR 38 CPUCLKC0 OUT 39 CPUCLKT0 OUT 40 VDDCPU PWR 41 CPUCLKC1 OUT 42 CPUCLKT1 OUT 43 GND PWR 44 CPUCLKC_ITP OUT 45 CPUCLKT_ITP OUT 46 IREF OUT 47 48 GND VDDA PWR PWR DESCRIPTION FS_A latched input for frequency select Reference output, 14.318Hz FS_B latched input for frequency select Reference output, 14.318Hz Ref, XTAL power supply, nominal 3.3V Crystal input, Nominally 14.318MHz. Crystal output, Nominally 14.318MHz Ground pin. Free running PCI clock not affected by PCI_STOP# . Free running PCI clock not affected by PCI_STOP# . Free running PCI clock not affected by PCI_STOP# . Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output. PCI clock output. PCI clock output. PCI clock output. Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output. PCI clock output. Asynchronous active low input pin, with 120Kohm internal pull-up resistor, used to power down the device. The internal clocks are disabled and the VCO and the crystal are stopped. 48.008MHz Dot clock output 48.008MHz USB clock output Ground pin. Power for 48MHz output buffers and fixed PLL core. 3.3V 66.66MHz clock output VCH: 48MHz VCH clock output 3.3V 66.66MHz clock output Power pin for the 3V66 clocks. Ground pin. 3.3V 66.66MHz clock output 3.3V 66.66MHz clock output Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 5V tolerant. This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. This is an active low input. Power supply, nominal 3.3V Complementary clock of differential pair for S-ATA support. +/- 300ppm accuracy required. True clock of differential pair for S-ATA support. +/- 300ppm accuracy required. Ground pin. Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Ground pin. "Complementary" clocks of differential pair CPU outputs for ITP.. These are current mode outputs. External resistors are required for voltage bias. "True" clocks of differential pair CPU outputs for ITP. These are current mode outputs. External resistors are required for voltage bias. This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin. 3.3V power for the PLL core. 0756A—09/10/04 2 ICS952621 Integrated Circuit Systems, Inc. General Description ICS962621 is a programmable 48 pin clock chip following Intel CK409 Yellow Cover specification. This clock synthesizer provides a single chip solution for next generation P4 Intel processors and Intel chipsets. ICS962621 is driven with a 14.318MHz crystal. It generates CPU outputs up to 200MHz. It also provides a tight ppm accuracy output for Serial ATA support. Block Diagram PLL2 X1 X2 Frequency Dividers 48MHz, USB, DOT, VCH XTAL REF (1:0) CPUCLKT (1:0) CPUCLKC (1:0) SRCCLKT0 Programmable Spread PLL1 SCLK SDATA Programmable Frequency Dividers STOP Logic SRCCLKC0 3V66(3:0) PCICLK (5:0), PCICLK_F (2:0) VTTPWRGD# Control Logic PD# CPUCLKT_ITP FS_A CPUCLKC_ITP FS_B I REF MODE RESET# Power Groups Pin Number Description VDD 3 27 10,16 34 48 24 -- GND 6 28 11,17 37 47 23 47 Xtal, Ref 3V66 [0:3] PCICLK outputs SRCCLK outputs Master clock, CPU Analog 48MHz, Fix Digital, Fix Analog IREF 40 43 CPUCLK clocks 0756A—09/10/04 3 ICS952621 Integrated Circuit Systems, Inc. Absolute Max Symbol VDD_A VDD_In Ts Tambient Tcase ESD prot Parameter 3.3V Core Supply Voltage 3.3V Logic Input Supply Voltage Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection human body model Min Max VDD + 0.5V VDD + 0.5V 150 70 115 -0.5 -65 0 Units V V °C °C °C 2000 V Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN Input High Voltage VIH 3.3V +/-5% Input Low Voltage VIL 3.3V +/-5% Input High Current IIH VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors 2 VSS 0.3 -5 IIL1 Input Low Current IIL2 Operating Supply Current IDD3.3OP Full Active, CL = Full load; Powerdown Current IDD3.3PD Input Frequency3 Pin Inductance1 Fi Lpin CIN COUT CINX all diff pairs driven all differential pairs tri-stated VDD = 3.3 V TYP MAX VDD + 0.3 V 0.8 V 5 uA -5 uA -200 uA 260 0.3 350 mA 35 12 mA mA MHz nH pF pF pF 3 1 1 1 1 ms 1,2 kHz 1 us 1 ns ns 1 2 14.31818 7 5 6 5 Logic Inputs Output pin capacitance X1 & X2 pins From VDD Power-Up or deTSTAB 1.8 Clk Stabilization1,2 assertion of PD# to 1st clock. Modulation Frequency Triangular Modulation 30 33 CPU output enable after Tdrive_PD# 300 PD# de-assertion Tfall_Pd# PD# fall time of 5 Trise_Pd# PD# rise time of 5 1 Guaranteed by design, not 100% tested in production. 2 See timing diagrams for timing requirements. 3 Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. Input Capacitance1 0756A—09/10/04 4 UNITS NOTES ICS952621 Integrated Circuit Systems, Inc. Electrical Characteristics - CPU & SRC 0.7V Current Mode Differential Pair TA = 0 - 70°C; VDD = 3.3V +/-5%; CL =2pF PARAMETER SYMBOL CONDITIONS MIN Current Source Output Impedance Zo VO = Vx 3000 Voltage High VHigh Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. 660 1 Voltage Low VLow Max Voltage Min Voltage Crossing Voltage (abs) Vovs Vuds Vcross(abs) Crossing Voltage (var) d-Vcross Long Accuracy ppm Average period Tperiod Absolute min period Tabsmin Rise Time Fall Time Rise Time Variation Fall Time Variation tr tf d-tr d-tf Variation of crossing over all edges see Tperiod min-max values 200MHz nominal 200MHz spread 166.66MHz nominal 166.66MHz spread 133.33MHz nominal 133.33MHz spread 100.00MHz nominal 100.00MHz spread 200MHz nominal 166.66MHz nominal/spread 133.33MHz nominal/spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V TYP 749 MAX UNITS NOTES Ω 1 850 1 mV -150 3 150 1150 -300 250 756 -7 350 550 mV 1 1 1 12 140 mV 1 ppm ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps 1,2 2 2 2 2 2 2 2 2 1,2 1,2 1,2 1,2 1 1 1 1 -300 4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 4.8735 5.8732 7.3728 9.8720 175 175 0 5.0000 300 5.0015 5.0266 6.0000 6.0018 6.0320 7.5000 7.5023 5.4000 10.0000 10.0030 10.0533 279 280 30 30 700 700 125 125 1 mV Measurement from differential 45 50.9 55 % wavefrom VT = 50% tsk3 8 100 ps Skew Measurement from differential tjcyc-cyc Jitter, Cycle to cycle 40 125 ps wavefrom 1 Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz SRC clock outputs run at only 100MHz or 200MHz, specs for 133.33 and 166.66 do not apply to SRC clock pair. Duty Cycle dt3 0756A—09/10/04 5 1 1 1 ICS952621 Integrated Circuit Systems, Inc. Electrical Characteristics - 3V66 Mode: 3V66 [3:0] TA = 0 - 70°C; VDD = 3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Long Accuracy ppm see Tperiod min-max values 66.66MHz output nominal Tperiod Clock period 66.66MHz output spread IOH = -1 mA VOH Output High Voltage VOL IOL = 1 mA Output Low Voltage V OH = 1.0 V IOH Output High Current VOH = 3.135 V VOL = 1.95 V IOL Output Low Current VOL = 0.4 V Edge Rate Rising edge rate Edge Rate Falling edge rate VOL = 0.4 V, VOH = 2.4 V tr1 Rise Time tf1 VOH = 2.4 V, VOL = 0.4 V Fall Time dt1 VT = 1.5 V Duty Cycle Skew tsk1 VT = 1.5 V Jitter tjcyc-cyc VT = 1.5 V 3V66 MIN -300 14.9955 14.9955 2.4 TYP MAX 300 15.0045 15.0799 Notes 1,2 2 2 38 4 4 2 2 55 UNITS ppm ns ns V V mA mA mA mA V/ns V/ns ns ns % 250 ps 1 250 ps 1 0.55 -33 -33 30 1 1 0.5 0.5 45 1.78 1.72 49.9 80 172 1 1 1 1 1 1 Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz Electrical Characteristics - PCICLK TA = 0 - 70°C; VDD = 3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN Long Accuracy ppm see Tperiod min-max values -300 29.9910 33.33MHz output nominal Tperiod Clock period 29.9910 33.33MHz output spread VOH IOH = -1 mA Output High Voltage 2.4 VOL IOL = 1 mA Output Low Voltage V OH = 1.0 V IOH Output High Current VOH = 3.135 V -33 VOL = 1.95 V 30 IOL Output Low Current VOL = 0.4 V Edge Rate Edge Rate Rise Time Fall Time Duty Cycle Skew Jitter tr1 tf1 dt1 tsk1 tjcyc-cyc Rising edge rate Falling edge rate VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V 3V66 1 1 1 0.5 0.5 45 TYP MAX 300 30.0090 30.1598 0.55 -33 1.78 1.72 51.2 59 140 38 4 4 2 2 55 500 250 UNITS ppm ns ns V V mA mA mA mA V/ns V/ns ns ns % ps ps Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz 0756A—09/10/04 6 Notes 1,2 2 2 1 1 1 1 1 1 1 ICS952621 Integrated Circuit Systems, Inc. Electrical Characteristics - VCH, USB TA = 0 - 70°C; VDD = 3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL Long Accuracy Clock period Output High Voltage Output Low Voltage ppm Tperiod VOH VOL CONDITIONS MIN TYP MAX UNITS Notes see Tperiod min-max values -200 200 ppm 48.008MHz output nominal 20.8257 20.8340 ns IOH = -1 mA 2.4 V IOL = 1 mA 0.55 V V OH = 1.0 V -29 mA IOH Output High Current VOH = 3.135 V -23 mA VOL = 1.95 V 29 mA IOL Output Low Current VOL = 0.4 V 27 mA Rising edge rate 1 2 V/ns Edge Rate Edge Rate Falling edge rate 1 2 V/ns tr1 VOL = 0.4 V, VOH = 2.4 V Rise Time 1 1.45 2 ns tf1 VOH = 2.4 V, VOL = 0.4 V Fall Time 1 1.37 2 ns V = 1.5 V d 45 52.5 55 % Duty Cycle t1 T VT = 1.5 V tsk1 1 ns Skew 125us period jitter 0.628 6 ns Long Term Jitter (8kHz frequency modulation amplitude) 1 Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz 1,2 2 1 1 1 1 1 1 1 Electrical Characteristics - 48MHz DOT Clock TA = 0 - 70°C; VDD = 3.3V +/-5%; CL = 5-10 pF (unless otherwise specified) PARAMETER Long Accuracy Clock period Output High Voltage Output Low Voltage SYMBOL ppm Tperiod VOH VOL Output High Current IOH Output Low Current IOL Notes 1,2 2 27 4 4 UNITS ppm ns V V mA mA mA mA V/ns V/ns 1 ns 1 VOH = 2.4 V, VOL = 0.4 V 0.5 0.89 1 ns VT = 1.5 V 45 52.3 55 % VT = 1.5 V 1 ns 125us period jitter 0.636 2 ns Long Term Jitter (8kHz frequency modulation amplitude) 1 Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz 1 1 1 Edge Rate Edge Rate Rise Time Fall Time Duty Cycle Skew tr1 CONDITIONS see Tperiod min-max values 48.008MHz output nominal IOH = -1 mA IOL = 1 mA V OH = 1.0 V VOH = 3.135 V VOL = 1.95 V VOL = 0.4 V Rising edge rate Falling edge rate MIN -200 20.8257 2.4 VOL = 0.4 V, VOH = 2.4 V 0.5 tf1 dt1 tsk1 0756A—09/10/04 7 TYP MAX 200 20.8340 0.55 -29 -23 29 2 2 0.87 1 1 1 ICS952621 Integrated Circuit Systems, Inc. Electrical Characteristics - REF-14.318MHz TA = 0 - 70°C; VDD = 3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Long Accuracy ppm see Tperiod min-max values Tperiod Clock period 14.318 MHz output nominal 1 IOH = -1 mA Output High Voltage VOH 1 IOL = 1 mA Output Low Voltage VOL V OH = 1.0 V IOH Output High Current VOH = 3.135 V VOL = 1.95 V IOL Output Low Current VOL = 0.4 V 1 V = 0.4 V, VOH = 2.4 V Rise Time tr1 OL 1 VOH = 2.4 V, VOL = 0.4 V Fall Time tf1 1 VT = 1.5 V Skew tsk1 1 VT = 1.5 V Duty Cycle dt1 Jitter 1 1 MIN TYP MAX -300 300 69.8270 69.8550 2.4 0.4 -33 -33 30 38 0.5 1.93 2 0.5 1.92 2 14 500 45 VT = 1.5 V tjcyc-cyc UNITS ppm ns V V mA mA mA mA ns ns ps 55 % 1 400 1000 ps 1 Group to Group Skews at Common Transition Edges SYMBOL S3V66-PCI SDOT_USB SDOT_VCH CONDITIONS 3V66 (4:0) leads 33MHz PCI 180 degrees out of phase in phase 0756A—09/10/04 8 MIN 1.50 0.00 0.00 1 1 1 53.8 Guaranteed by design, not 100% tested in production. GROUP 3V66 to PCI DOT-USB DOT-VCH Notes 1 TYP 2.0 MAX 3.50 1.00 1.00 UNITS ns ns ns ICS952621 Integrated Circuit Systems, Inc. 2 I C Table: Read-Back Register Pin # Byte 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 - Bit 0 - Name Control Function RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Freq Select 1 Read FSB Back Freq Select 0 Read FSA Back Type R R R R R 0 1 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED READBACK of CPU(2:0) Frequency PWD X X X X X X X X 2 I C Table: Spreading and Device Behavior Control Register Name Control Function Pin # Byte 1 SRC Free-Running SRC/SRC# Bit 7 Control SRC Output Control Bit 6 RESERVED Bit 5 RESERVED Bit 4 RESERVED Bit 3 RESERVED Bit 2 CPUT1/CPUC1 Output Control Bit 1 CPUT0/CPUC0 Output Enable Bit 0 Type RW RW R R R R RW RW 0 1 FREE- STOPPAB RUN LE Disable Enable RESERVED RESERVED RESERVED RESERVED Disable Enable Disable Enable PWD 0 1 X X X X 1 1 2 I C Table: Output Control Register Pin # Byte 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name SRC_PD# Drive Mode SRC_Stop# Drive Mode RESERVED CPUT1_PD# Drive Mode CPUT0_PD# Drive Mode RESERVED RESERVED RESERVED Control Function Type 0 1 PWD 0: Driven in PD# RW Driven Hi-Z 0 RW Driven Hi-Z 0 RW RW - RESERVED Driven Hi-Z Driven Hi-Z RESERVED RESERVED RESERVED X 0 0 X X X 0: Driven in PCI_Stop# RESERVED 0:driven in PD# 1: Tri-stated RESERVED RESERVED RESERVED 2 I C Table: Output Control Register Pin # Byte 3 Name Bit 7 PCI_Stop# Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESERVED PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 Control Function PCI_Stop# Control 0:all stoppable PCI are stopped RESERVED Output Control Output Control Output Control Output Control Output Control Output Control 0756A—09/10/04 9 Type 0 1 PWD RW Enable Disable 1 RW RW RW RW RW RW RESERVED Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable X 1 1 1 1 1 1 ICS952621 Integrated Circuit Systems, Inc. 2 I C Table: Output Control Register Byte 4 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Control Function Type 0 1 PWD 48MHz_USB 2x output drive 48MHz_USB RESERVED RESERVED RESERVED PCICLK_F2 PCICLK_F1 PCICLK_F0 0=2x drive RW 2x drive 1xdrive 1 Output Control RESERVED RESERVED RESERVED Output Control Output Control Output Control RW RW RW RW Disable Enable RESERVED RESERVED RESERVED stoppable Free-run stoppable Free-run stoppable Free-run 1 X X X 1 1 1 Control Function Output Control Output Control Type RW RW 0 Disable Disable 1 Enable Enable PWD 1 1 Output Select RW 3V66 VCH 0 2 I C Table: Output Control Register Pin # Byte 5 Name DOT_48MHZ Bit 7 CPU_T/C_ITP Bit 6 3V66_3/VCH Bit 5 Frequency Select Bit 4 3V66_3/VCH Frequency Select Output Control RW Disable Enable 1 Bit 3 Bit 2 Bit 1 Bit 0 RESERVED 3V66_2 3V66_1 3V66_0 RESERVED Output Control Output Control Output Control RW RW RW RESERVED Disable Enable Disable Enable Disable Enable X 1 1 1 Control Function Test Clock Mode FS_A and FS_B Operation SRC Frequency Select Down/Center Spread Spectrum Enable Output Control Output Control Type - 0 Disable - 1 Enable - PWD 0 0 - Normal Test Mode 0 - 100MHz 200MHz 0 - Center Spread ON Enable Enable 0 RW RW Down Spread OFF Disable Disable 1 1 Control Function Type R R R R R R R R 0 - 1 - PWD 0 0 0 0 0 0 0 1 2 I C Table: Output Control and Fix Frequecy Register Pin # Name Byte 6 Test Clock Mode Bit 7 RESERVED Bit 6 Bit 5 CPU *2 Test Clock Bit 4 SRC Frequency Select Bit 3 Spread Spectrum Type Bit 2 Spread Spectrum Mode Bit 1 Bit 0 REF1 REF0 0 2 I C Table: Vendor & Revision ID Register Name Pin # Byte 7 RID3 Bit 7 RID2 Bit 6 RID1 Bit 5 RID0 Bit 4 VID3 Bit 3 VID2 Bit 2 VID1 Bit 1 VID0 Bit 0 REVISION ID VENDOR ID 0756A—09/10/04 10 ICS952621 Integrated Circuit Systems, Inc. 2 I C Table: Byte Count Register Byte 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # - Name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Control Function Type 0 1 PWD Writing to this register will configure how many bytes will be read back, default is 08 = 8 bytes. RW RW RW RW RW RW RW RW - - 0 0 0 0 1 0 0 0 0756A—09/10/04 11 ICS952621 Integrated Circuit Systems, Inc. PD#, Power Down PD# is an asynchronous active low input used to shut off all clocks cleanly prior to clock power. When PD# is asserted low all clocks will be driven low before turning off the VCO. In PD# de-assertion all clocks will start without glitches. PWRDWN# CPU CPU # SRC SRC# 3V66 PCIF/PCI USB/DOT REF 1 Normal Normal Normal Normal 66MHz 33MHz 48MHz 14.318MHz 0 Iref * 2 or Float Float Iref * 2 or Float Float Low Low Low Low Note Notes: 1. Refer to tristate control of CPU and SRC clocks in section 7.7 for tristate timing and operation. 2. Refer to Control Registers in section 16 for CPU_Stop, SRC_Stop and PwrDwn SMBus tristate control addresses. PD# Assertion PD# should be sampled low by 2 consecutive CPU# rising edges before stopping clocks. All single ended clocks will be held low on their next high to low transition. All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven. When the drive mode but corresponding to the CPU or SRC clock of interest is set to '0' the true clock will be driven high at 2 x Iref and the complementary clock will be tristated. If the control register is programmed to '1' both clocks will the tristated. PWRDWN# CPU, 133MHz CPU#, 133MHz SRC, 100MHz SRC#, 100MHz 3V66, 66MHz USB, 48MHz PCI, 33MHz REF, 14.31818 0756A—09/10/04 12 ICS952621 Integrated Circuit Systems, Inc. PD# De-assertion The time from the de-assertion of PD# or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive mode control bit for PD# tristate is programmed to '1' the stopped differential pair must first be driven high to a minimum of 200mV in less than 300µs of PD# deassertion. Tstable <1.8mS PWRDWN# CPU, 133MHz CPU#, 133MHz SRC, 100MHz SRC# 100MHz 3V66, 66MHz USB, 48MHz PCI, 33MHz REF, 14.31818 Tdrive_PwrDwn# <300µS, >200mV 3V66_3/VCH Pin Functionality The 3V66_4/VCH pin can be configured to be a 66.66MHz modulated output or a non-spread 48MHz output. The default is 3V66 clock. The switching is controlled by Byte 5 Bit 5. If it is set to '1' this pin will output the 48MHz VCH clock. The output will go low on the falling edge of 3V66 for a minimum of 7.49ns. Then the output will transition to 48MHz on the next rising edge of DOT_48 clock. 3V66 3V66_4/VCH DOT_48 7.49nS min 0756A—09/10/04 13 ICS952621 Integrated Circuit Systems, Inc. Shared Pin Operation Input/Output Pins Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Via to VDD Programming Header 2K Via to Gnd Device Pad 8.2K Clock trace to load Series Term. Res. Fig. 1 0756A—09/10/04 14 ICS952621 Integrated Circuit Systems, Inc. c N SYMBOL L E1 A A1 b c D E E1 e h L N α E INDEX AREA 1 2 α h x 45° D A In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0° 8° In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° A1 -Ce VARIATIONS N SEATING PLANE b 48 .10 (.004) C D mm. MIN 15.75 D (inch) MAX 16.00 MIN .620 Reference Doc.: JEDEC Publication 95, MO-118 10-0034 Ordering Information ICS952621yFLF-T Example: ICS XXXX y F LF- T Designation for tape and reel packaging Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 0756A—09/10/04 15 MAX .630