ICS9DB106 Preliminary Product Preview Integrated Circuit Systems, Inc. 6 Output PCI Express* Buffer with CLKREQ# Function Pin Configuration Output Features: • 6 - 0.7V current mode differential output pairs (HSCL) • SMBus for complete device control Key Specifications: • Cycle-to-cycle jitter < 40ps • Output-to-output skew < 30 ps Features/Benefits: • CLKREQ# pin for outputs 1 and 4/output enable for Express Card applications • PLL or bypass mode/PLL can dejitter incoming clock • Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL’s • Spread Spectrum Compatible/tracks spreading input clock for low EMI • SMBus Interface/unused outputs can be disabled 0833A—07/26/04 PLL_BW 1 28 VDDA CLK_INT 2 27 GNDA CLK_INC 3 26 IREF *CLKREQ1# 4 25 **CLKREQ4# PCIEXT0 5 24 PCIEXT5 PCIEXC0 6 23 PCIEXC5 VDD 7 22 VDD GND 8 21 GND PCIEXT1 9 20 PCIEXT4 PCIEXC1 10 19 PCIEXC4 PCIEXT2 11 18 PCIEXT3 PCIEXC2 12 17 PCIEXC3 VDD 13 16 VDD SMBDAT 14 15 SMBCLK Note: Pins preceeded by '**' have internal 120K ohm pull down resistors ICS9DB106 Recommended Application: 1-to-6 Zero-delay or fanout buffer for PCI Express 28-pin SSOP & TSSOP *Other names and brands may be claimed as the property of others. PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. ICS9DB106 Preliminary Product Preview Integrated Circuit Systems, Inc. Pin Description PIN # PIN NAME PIN TYPE 1 PLL_BW IN 2 3 CLK_INT CLK_INC IN IN 4 **CLKREQ1# IN 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PCIEXT0 PCIEXC0 VDD GND PCIEXT1 PCIEXC1 PCIEXT2 PCIEXC2 VDD SMBDAT SMBCLK VDD PCIEXC3 PCIEXT3 PCIEXC4 PCIEXT4 GND VDD PCIEXC5 PCIEXT5 OUT OUT PWR IN OUT OUT OUT OUT PWR I/O IN PWR OUT OUT OUT OUT PWR PWR OUT OUT 25 **CLKREQ4# IN 26 IREF OUT 27 28 GNDA VDDA PWR PWR DESCRIPTION 3.3V input for selecting PLL Band Width 0 = low, 1= high "True" reference clock input. "Complimentary" reference clock input. Output enable for PCI Express output pair '1' 0 = enabled, 1 = tri-stated True clock of differential PCI_Express pair. Complement clock of differential PCI_Express pair. Power supply, nominal 3.3V Ground pin. True clock of differential PCI_Express pair. Complement clock of differential PCI_Express pair. True clock of differential PCI_Express pair. Complement clock of differential PCI_Express pair. Power supply, nominal 3.3V Data pin of SMBUS circuitry, 5V tolerant Clock pin of SMBUS circuitry, 5V tolerant Power supply, nominal 3.3V Complement clock of differential PCI_Express pair. True clock of differential PCI_Express pair. Complement clock of differential PCI_Express pair. True clock of differential PCI_Express pair. Ground pin. Power supply, nominal 3.3V Complement clock of differential PCI_Express pair. True clock of differential PCI_Express pair. Output enable for PCI Express output pair '4' 0 = enabled, 1 = tri-stated This pin establishes the reference current for the differential currentmode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the PLL core. 3.3V power for the PLL core. Note: Pins preceeded by '**' have internal 120K ohm pull down resistors 0833A—07/26/04 2 ICS9DB106 Preliminary Product Preview Integrated Circuit Systems, Inc. General Description The ICS9DB106 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB106 is driven by a differential SRC output pair from an ICS CK409/CK410-compliant main clock generator such as the ICS952601 or ICS954101. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (OE#) pins make the ICS9DB106 suitable for Express Card applications. Block Diagram CLKREQ1# CLKREQ4# PCIEX1 CLK_INT C LK_INC SPREAD COMPATIBLE PLL PCIEX4 PCIEX(0,2,3,5) PLL_BW SMBDAT CONTROL LOGIC SMBCLK IREF Power Groups Pin Number VDD GND 7, 13, 16, 22 8,21 TBD TBD N/A 27 28 27 Description PCI Express Outputs SMBUS IREF Analog VDD & GND for PLL core 0833A—07/26/04 3 ICS9DB106 Preliminary Product Preview Integrated Circuit Systems, Inc. Absolute Max Symbol VDDA VDD Parameter 3.3V Core Supply Voltage 3.3V Output Supply Voltage Ts Tambient Tcase Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection human body model ESD prot Min Max VDD + 0.5V VDD + 0.5V GND - 0.5 -65 0 Units V V ° C °C °C 150 70 115 2000 V Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN Input High Voltage VIH 3.3 V +/-5% 2 VDD + 0.3 V 1 Input Low Voltage Input High Current VIL IIH 3.3 V +/-5% VIN = VDD VIN = 0 V; Inputs with no pullup resistors VIN = 0 V; Inputs with pull-up resistors Full Active, CL = Full load; all differential pairs tri-stated VDD = 3.3 V VSS - 0.3 -5 0.8 5 V uA 1 1 -5 uA 1 -200 uA 1 150 40 101 7 5 4.5 mA mA MHz nH pF pF 1 1 1.8 ms 1 30 33 kHz 1 2.7 5.5 0.4 V V 1 1 mA 1 1000 ns 1 300 ns 1 IIL1 Input Low Current IIL2 Operating Supply Current I DD3.3OP Input Frequency Pin Inductance Fi Lpin CIN COUT Input Capacitance Clk Stabilization Input Spread Spectrum Modulation Frequency SMBus Voltage Low-level Output Voltage Current sinking at VOL = 0.4 V SCLK/SDATA Clock/Data Rise Time SCLK/SDATA Clock/Data Fall Time TSTAB Logic Inputs Output pin capacitance From VDD reaching 3.1V and input clock stable Triangular Modulation VDD VOL 99 @ IPULLUP IPULLUP TRI2C TFI2C TYP 130 30 100 MAX 4 (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) 1 Guaranteed by design and characterization, not 100% tested in production. 0833A—07/26/04 4 UNITS Notes 1 1 1 ICS9DB106 Preliminary Product Preview Integrated Circuit Systems, Inc. Electrical Characteristics - PCIEX 0.7V Current Mode Differential Outputs TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2η , RP=49.9η Ρ REFηΡ 9, PARAMETER SYMBOL CONDITIONS MIN Current Source Output Impedance Zo1 VO = V x 3000 Voltage High VHigh Statistical measurement on single ended signal using oscilloscope math function. 660 Voltage Low VLow Max Voltage Min Voltage Crossing Voltage (abs) Vovs Vuds Vcross(abs) Crossing Voltage (var) d-Vcross Long Accuracy ppm Average period Tperiod Absolute min period Rise Time Fall Time Rise Time Variation Fall Time Variation Tabsmin tr tf d-tr d-tf tpd tpdbyp Input to Output Delay Duty Cycle dt3 Output-to-Output Skew tsk3 Jitter, Cycle to cycle tjcyc-cyc Measurement on single ended signal using absolute value. Variation of crossing over all edges see Tperiod min-max values 100.00MHz nominal 100.00MHz spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V V OH = 0.525V VOL = 0.175V PLL Mode. Bypass mode Measurement from differential wavefrom VT = 50% PLL mode, Measurement from differential wavefrom BYPASS mode as additive jitter TYP MAX UNITS NOTES η 1 850 1,3 mV -150 150 1150 1,3 550 mV 1,3 1,3 1,3 140 mV 1,3 0 10.0030 10.0533 100 3.2 700 700 125 125 150 3.7 ppm ns ns ns ps ps ps ps ps ns 1,2 2 2 1,2 1 1 1 1 1 1 45 55 % 1 30 ps 1 40 ps 1 25 ps 1 -300 250 9.9970 9.9970 9.8720 175 175 mV 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that the input clock complies with CK409/CK410 accuracy requirements 3 I REF = VDD/(3xRR). For RR = 475η (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50η . 0833A—07/26/04 5 ICS9DB106 Preliminary Product Preview Integrated Circuit Systems, Inc. SMBusTable: Device Control Register, READ/WRITE ADDRESS (DC/DD) Byte 0 0 1 PWD Pin # Name Control Function Type PLL controlled Enables SMBus PLL controlled SW_EN RW by SMBus 1 Bit 7 Control by device pins registers RW X RESERVED Bit 6 RW X RESERVED Bit 5 RW X RESERVED Bit 4 RESERVED RW X Bit 3 RESERVED RW X Bit 2 Selects PLL PLL BW #adjust RW Low BW High BW 1 Bit 1 Bandwidth Bypasses PLL for PLL bypassed PLL enabled 1 PLL Enable RW Bit 0 (fan out mode) (ZDB mode) board test SMBusTable: Output Enable Register Pin # Name Control Function Type Byte 1 RESERVED RW Bit 7 RW RESERVED Bit 6 PCIEX5 Output Control RW 24,23 Bit 5 RW RESERVED Bit 4 PCIEX3 Output Control RW 18,17 Bit 3 PCIEX2 Output Control RW 11,12 Bit 2 RW RESERVED Bit 1 PCIEX0 Output Control RW 5,6 Bit 0 SMBusTable: Function Select Register Pin # Name Control Function Type Byte 2 RW RESERVED Bit 7 RW RESERVED Bit 6 RESERVED RW Bit 5 RW RESERVED Bit 4 RW RESERVED Bit 3 RESERVED RW Bit 2 RESERVED RW Bit 1 RESERVED RW Bit 0 0833A—07/26/04 6 0 1 - Disable Enable - Disable Disable Enable Enable - Disable Enable 0 1 - PWD X X 1 X 1 1 X 1 PWD X X X X X X X X ICS9DB106 Preliminary Product Preview Integrated Circuit Systems, Inc. SMBusTable: Vendor & Revision ID Register Byte 3 Pin # Name Control Function Type RID3 R Bit 7 RID2 R Bit 6 REVISION ID RID1 R Bit 5 RID0 R Bit 4 VID3 R Bit 3 VID2 R Bit 2 VENDOR ID VID1 R Bit 1 VID0 R Bit 0 SMBusTable: DEVICE ID Byte 4 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Control Function Type R R R Device ID R = 06 Hex R R R R 0 - 0 1 - PWD X X X X 0 0 0 1 1 PWD 0 0 0 0 0 1 1 0 - SMBusTable: Byte Count Register Pin # Byte 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - Name Control Function Type 0 1 PWD BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Writing to this register will configure how many bytes will be read back, default is 06 = 6 bytes. RW RW RW RW RW RW RW RW - - 0 0 0 0 0 1 1 0 0833A—07/26/04 7 ICS9DB106 Preliminary Product Preview Integrated Circuit Systems, Inc. 209 mil SSOP SYMBOL A A1 A2 b c D E E1 e L N a In Millimeters COMMON DIMENSIONS MIN MAX -2.00 0.05 -1.65 1.85 0.22 0.38 0.09 0.25 SEE VARIATIONS 7.40 8.20 5.00 5.60 0.65 BASIC 0.55 0.95 SEE VARIATIONS 0° 8° In Inches COMMON DIMENSIONS MIN MAX -.079 .002 -.065 .073 .009 .015 .0035 .010 SEE VARIATIONS .291 .323 .197 .220 0.0256 BASIC .022 .037 SEE VARIATIONS 0° 8° VARIATIONS D mm. N MIN 9.90 28 D (inch) MAX 10.50 MIN .390 Reference Doc.: JEDEC Publication 95, MO-150 10-0033 Ordering Information ICS9DB106yFLF-T Example: ICS XXXX y F LF-T Designation for tape and reel packaging Lead Free (optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 0833A—07/26/04 8 MAX .413 ICS9DB106 Preliminary Product Preview Integrated Circuit Systems, Inc. c N 4.40 mm. Body, 0.65 mm. Pitch TSSOP (173 mil) L E1 INDEX AREA E 1 2 α D A A2 A1 -Ce SEATING PLANE b aaa C SYMBOL A A1 A2 b c D E E1 e L N a aaa (25.6 mil) In Millimeters COMMON DIMENSIONS MIN MAX -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 SEE VARIATIONS 6.40 BASIC 4.30 4.50 0.65 BASIC 0.45 0.75 SEE VARIATIONS 0° 8° -0.10 In Inches COMMON DIMENSIONS MIN MAX -.047 .002 .006 .032 .041 .007 .012 .0035 .008 SEE VARIATIONS 0.252 BASIC .169 .177 0.0256 BASIC .018 .030 SEE VARIATIONS 0° 8° -.004 VARIATIONS N 28 D mm. MIN 9.60 D (inch) MAX 9.80 MIN .378 Reference Doc.: JEDEC Publication 95, MO-153 10-0035 Ordering Information ICS9DB106yGLF-T Example: ICS XXXX yG LF-T Designation for tape and reel packaging Lead Free (optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 0833A—07/26/04 9 MAX .386