DATASHEET ICS9DB801C Eight Output Differential Buffer for PCI Express (50-200MHz) Description Features/Benefits The 9DB801C is a DB800 Version 2.0 Yellow Cover part with PCI Express support. It can be used in PC or embedded systems to provide outputs that have low cycle-to-cycle jitter (50ps), low output-to-output skew (100ps), and are PCI Express gen 1 compliant. The 9DB801C supports a 1 to 8 output configuration, taking a spread or non spread differential HCSL input from a CK410(B) main clock such as 954101 and 932S401, or any other differential HCSL pair. 9DB801C can generate HCSL or LVDS outputs from 50 to 200MHz in PLL mode or 0 to 400Mhz in bypass mode. There are two de-jittering modes available selectable through the HIGH_BW# input pin, high bandwidth mode provides de-jittering for spread inputs and low bandwidth mode provides extra de-jittering for non-spread inputs. The SRC_STOP#, PD#, and individual OE# real-time input pins provide completely programmable power management control. • • • Key Specifications • • • • • • • • Output Features • • • Spread spectrum modulation tolerant, 0 to -0.5% down spread and +/- 0.25% center spread. Supports undriven differential outputs in PD# and SRC_STOP# modes for power management. Supports polarity inversion to the output enables, SRC_STOP and PD. Outputs cycle-cycle jitter < 50ps Outputs skew: 50ps 50 - 200MHz operation Extended frequency range in bypass mode to 400 MHz PCI Express Gen I compliant Real time PLL lock detect output pin 48-pin SSOP/TSSOP package Available in RoHS compliant packaging 8 - 0.7V current-mode differential output pairs Supports zero delay buffer mode and fanout mode Bandwidth programming available Funtional Block Diagram 8 OE_(7:0) SPREAD COMPATIBLE PLL SRC_IN SRC_IN# M U X STOP LOGIC 8 DIF(7:0)) SRC_STOP# HIGH_BW# BYPASS#/PLL PD# CONTROL LOGIC IREF SDATA SCLK LOCK Note: Polarities shown for OE_INV = 0. IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) ICS9DB801C 1 REV C 08/16/07 ICS9DB801C Eight Output Differential Buffer for PCI Express (50-200MHz) Pin Configuration 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDA GNDA IREF LOCK OE_7 OE_4 DIF_7 DIF_7# OE_INV VDD DIF_6 DIF_6# OE_6 OE_5 DIF_5 DIF_5# GND VDD DIF_4 DIF_4# HIGH_BW# SRC_STOP# PD# GND SRC_DIV# VDD GND SRC_IN SRC_IN# OE0# OE3# DIF_0 DIF_0# GND VDD DIF_1 DIF_1# OE1# OE2# DIF_2 DIF_2# GND VDD DIF_3 DIF_3# BYPASS#/PLL SCLK SDATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 ICS9DB801 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ICS9DB801 (Same as ICS9DB108) SRC_DIV# VDD GND SRC_IN SRC_IN# OE_0 OE_3 DIF_0 DIF_0# GND VDD DIF_1 DIF_1# OE_1 OE_2 DIF_2 DIF_2# GND VDD DIF_3 DIF_3# BYPASS#/PLL SCLK SDATA VDDA GNDA IREF LOCK OE7# OE4# DIF_7 DIF_7# OE_INV VDD DIF_6 DIF_6# OE6# OE5# DIF_5 DIF_5# GND VDD DIF_4 DIF_4# HIGH_BW# SRC_STOP PD GND OE_INV = 1 OE_INV = 0 Polarity Inversion Pin List Table OE_INV Pins 0 1 6 OE_0 OE0# 7 OE_3 OE3# 14 OE_1 OE1# 15 OE_2 OE2# 26 PD# PD 27 DIF_STOP# DIF_STOP 35 OE_5 OE5# 36 OE_6 OE6# 43 OE_4 OE4# 44 OE_7 OE7# IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) ICS9DB801C 2 REV C 08/16/07 ICS9DB801C Eight Output Differential Buffer for PCI Express (50-200MHz) Pin Description for OE_INV = 0 PIN # PIN NAME PIN TYPE DESCRIPTION 1 SRC_DIV# INPUT Active low Input for determining SRC output frequency SRC or SRC/2. 0 = SRC/2, 1= SRC 2 3 4 5 VDD GND SRC_IN SRC_IN# POWER POWER INPUT INPUT 6 OE_0 INPUT 7 OE_3 INPUT 8 9 10 11 12 13 DIF_0 DIF_0# GND VDD DIF_1 DIF_1# OUTPUT OUTPUT POWER POWER OUTPUT OUTPUT 14 OE_1 INPUT 15 OE_2 INPUT 16 17 18 19 20 21 DIF_2 DIF_2# GND VDD DIF_3 DIF_3# OUTPUT OUTPUT POWER POWER OUTPUT OUTPUT 22 BYPASS#/PLL INPUT 23 24 SCLK SDATA INPUT I/O Power supply, nominal 3.3V Ground pin. 0.7 V Differential SRC TRUE input 0.7 V Differential SRC COMPLEMENTARY input Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs 0.7V differential true clock outputs 0.7V differential complement clock outputs Ground pin. Power supply, nominal 3.3V 0.7V differential true clock outputs 0.7V differential complement clock outputs Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs 0.7V differential true clock outputs 0.7V differential complement clock outputs Ground pin. Power supply, nominal 3.3V 0.7V differential true clock outputs 0.7V differential complement clock outputs Input to select Bypass(fan-out) or PLL (ZDB) mode 0 = Bypass mode, 1= PLL mode Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 5V tolerant. IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) ICS9DB801C 3 REV C 08/16/07 ICS9DB801C Eight Output Differential Buffer for PCI Express (50-200MHz) Pin Description for OE_INV = 0 PIN # 25 PIN NAME GND PIN TYPE POWER 26 PD# INPUT 27 SRC_STOP# INPUT 28 HIGH_BW# INPUT 29 30 31 32 33 34 DIF_4# DIF_4 VDD GND DIF_5# DIF_5 OUTPUT OUTPUT POWER POWER OUTPUT OUTPUT 35 OE_5 INPUT 36 OE_6 INPUT 37 38 39 DIF_6# DIF_6 VDD OUTPUT OUTPUT POWER 40 OE_INV INPUT 41 42 DIF_7# DIF_7 OUTPUT OUTPUT 43 OE_4 INPUT 44 OE_7 INPUT 45 LOCK OUTPUT 46 IREF INPUT 47 48 GNDA VDDA POWER POWER DESCRIPTION Ground pin. Asynchronous active low input pin, with 120Kohm internal pullup resistor, used to power down the device. The internal clocks are disabled and the VCO and the crystal are stopped. Active low input to stop SRC outputs. 3.3V input for selecting PLL Band Width 0 = High, 1= Low 0.7V differential complement clock outputs 0.7V differential true clock outputs Power supply, nominal 3.3V Ground pin. 0.7V differential complement clock outputs 0.7V differential true clock outputs Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs 0.7V differential complement clock outputs 0.7V differential true clock outputs Power supply, nominal 3.3V This latched input selects the polarity of the OE pins. 0 = OE pins active high, 1 = OE pins active low (OE#) 0.7V differential complement clock outputs 0.7V differential true clock outputs Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs 3.3V output indicating PLL Lock Status. This pin goes high when lock is achieved. This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the PLL core. 3.3V power for the PLL core. IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) ICS9DB801C 4 REV C 08/16/07 ICS9DB801C Eight Output Differential Buffer for PCI Express (50-200MHz) Pin Description for OE_INV = 1 PIN # PIN NAME PIN TYPE 1 SRC_DIV# INPUT 2 3 4 5 VDD GND SRC_IN SRC_IN# POWER POWER INPUT INPUT 6 OE0# INPUT 7 OE3# INPUT 8 9 10 11 12 13 DIF_0 DIF_0# GND VDD DIF_1 DIF_1# OUTPUT OUTPUT POWER POWER OUTPUT OUTPUT 14 OE1# INPUT 15 OE2# INPUT 16 17 18 19 20 21 DIF_2 DIF_2# GND VDD DIF_3 DIF_3# OUTPUT OUTPUT POWER POWER OUTPUT OUTPUT 22 BYPASS#/PLL INPUT 23 24 SCLK SDATA INPUT I/O DESCRIPTION Active low Input for determining SRC output frequency SRC or SRC/2. 0 = SRC/2, 1= SRC Power supply, nominal 3.3V Ground pin. 0.7 V Differential SRC TRUE input 0.7 V Differential SRC COMPLEMENTARY input Active low input for enabling DIF pair 0. 1 = tri-state outputs, 0 = enable outputs Active low input for enabling DIF pair 3. 1 = tri-state outputs, 0 = enable outputs 0.7V differential true clock outputs 0.7V differential complement clock outputs Ground pin. Power supply, nominal 3.3V 0.7V differential true clock outputs 0.7V differential complement clock outputs Active low input for enabling DIF pair 1. 1 = tri-state outputs, 0 = enable outputs Active low input for enabling DIF pair 2. 1 = tri-state outputs, 0 = enable outputs 0.7V differential true clock outputs 0.7V differential complement clock outputs Ground pin. Power supply, nominal 3.3V 0.7V differential true clock outputs 0.7V differential complement clock outputs Input to select Bypass(fan-out) or PLL (ZDB) mode 0 = Bypass mode, 1= PLL mode Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 5V tolerant. IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) ICS9DB801C 5 REV C 08/16/07 ICS9DB801C Eight Output Differential Buffer for PCI Express (50-200MHz) Pin Description for OE_INV = 1 PIN # PIN NAME 25 GND 26 PD 27 SRC_STOP 28 HIGH_BW# 29 30 31 32 33 34 DIF_4# DIF_4 VDD GND DIF_5# DIF_5 35 OE5# 36 OE6# 37 38 39 DIF_6# DIF_6 VDD 40 OE_INV 41 42 DIF_7# DIF_7 43 OE4# 44 OE7# 45 LOCK 46 IREF 47 48 GNDA VDDA PIN TYPE DESCRIPTION PWR Ground pin. Asynchronous active high input pin used to power down the IN device. The internal clocks are disabled and the VCO is stopped. IN Active high input to stop SRC outputs. 3.3V input for selecting PLL Band Width IN 0 = High, 1= Low OUT 0.7V differential complement clock outputs OUT 0.7V differential true clock outputs PWR Power supply, nominal 3.3V PWR Ground pin. OUT 0.7V differential complement clock outputs OUT 0.7V differential true clock outputs Active low input for enabling DIF pair 5. IN 1 = tri-state outputs, 0 = enable outputs Active low input for enabling DIF pair 6. IN 1 = tri-state outputs, 0 = enable outputs OUT 0.7V differential complement clock outputs OUT 0.7V differential true clock outputs PWR Power supply, nominal 3.3V This latched input selects the polarity of the OE pins. IN 0 = OE pins active high, 1 = OE pins active low (OE#) OUT 0.7V differential complement clock outputs OUT 0.7V differential true clock outputs Active low input for enabling DIF pair 4 IN 1 = tri-state outputs, 0 = enable outputs Active low input for enabling DIF pair 7. IN 1 = tri-state outputs, 0 = enable outputs 3.3V output indicating PLL Lock Status. This pin goes high OUT when lock is achieved. This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision IN resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. PWR Ground pin for the PLL core. PWR 3.3V power for the PLL core. IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) ICS9DB801C 6 REV C 08/16/07 ICS9DB801C Eight Output Differential Buffer for PCI Express (50-200MHz) Absolute Max Symbol VDD_A VDD_In VIL VIH Parameter 3.3V Core Supply Voltage 3.3V Logic Supply Voltage Input Low Voltage Input High Voltage Ts Tambient Tcase Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection human body model ESD prot Min Max 4.6 4.6 GND-0.5 V DD+0.5V -65 0 Units V V V V ° C °C °C 150 70 115 2000 V Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage Input Low Voltage Input High Current SYMBOL VIH VIL IIH IIL1 Input Low Current IIL2 Operating Supply Current IDD3.3PLL IDD3.3ByPass Powerdown Current IDD3.3PD Input Frequency FiPLL Input Frequency FiBypass Input Frequency FiBypass Pin Inductance 1 CONDITIONS MIN 3.3 V +/-5% 2 GND - 0.3 3.3 V +/-5% VIN = VDD -5 VIN = 0 V; Inputs with no pull-up -5 resistors VIN = 0 V; Inputs with pull-up -200 resistors uA 50 200 175 70 4 200 mA mA mA mA MHz 0 333.33 MHz 0 400 MHz 7 4 4 nH pF pF 1 1 1 3 3.4 MHz 1 1 1.4 MHz 1 0.5 1 ms 1,2 33 kHz 1 15 ns 1,3 300 us 1,3 5 ns 1 5 ns 2 Lpin CIN COUT Logic Inputs 1.5 1 Input Capacitance Output pin capacitance PLL Bandwidth when 2.4 PLL_BW=0 PLL Bandwidth BW PLL Bandwidth when 0.7 PLL_BW=1 From VDD Power-Up and after 1,2 TSTAB input clock stabilization or deClk Stabilization assertion of PD# to 1st clock Modulation Frequency fMOD Triangular Modulation 30 DIF output enable after Tdrive_SRC_STOP# SRC_Stop# de-assertion DIF output enable after Tdrive_PD# PD# de-assertion Fall time of PD# and Tfall SRC_STOP# Rise time of PD# and Trise SRC_STOP# 1 Guaranteed by design and characterization, not 100% tested in production. 2 See timing diagrams for timing requirements. 3 Time from deassertion until outputs are >200 mV IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) MAX UNITS NOTES VDD + 0.3 V 0.8 V 5 uA uA 175 160 50 1 Full Active, CL = Full load; all diff pairs driven all differential pairs tri-stated PLL Mode Bypass Mode (Revision B/REV ID = 1H) Bypass Mode (Revision C/REV ID = 2H) TYP 10 ICS9DB801C 7 REV C 08/16/07 ICS9DB801C Eight Output Differential Buffer for PCI Express (50-200MHz) Electrical Characteristics - DIF 0.7V Current Mode Differential Pair TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω PARAMETER Current Source Output Impedance SYMBOL CONDITIONS MIN Zo VO = Vx 3000 Voltage High VHigh Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. 660 1 Voltage Low VLow Max Voltage Min Voltage Crossing Voltage (abs) Vovs Vuds Vcross(abs) Crossing Voltage (var) d-Vcross Long Accuracy Rise Time Fall Time Rise Time Variation Fall Time Variation ppm tr tf d-tr d-tf Variation of crossing over all edges see Tperiod min-max values VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V TYP MAX UNITS NOTES Ω 1 850 1,3 mV -150 150 1150 -300 250 175 175 1,3 550 mV 1 1 1 140 mV 1 0 700 700 125 125 ppm ps ps ps ps 1,2 1 1 1 1 mV Measurement from differential 45 55 % wavefrom tsk3 VT = 50% Skew 50 ps PLL mode, 50 ps Measurement from differential tjcyc-cyc Jitter, Cycle to cycle wavefrom BYPASS mode as additive jitter 50 ps 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that the input clock complies with CK409/CK410 accuracy requirements 3 IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω. Duty Cycle dt3 IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) ICS9DB801C 8 1 1 1 1 REV C 08/16/07 ICS9DB801C Eight Output Differential Buffer for PCI Express (50-200MHz) SRC Reference Clock Common Recommendations for Differential Routing Dimension or Value L1 length, Route as non-coupled 50 ohm trace. 0.5 max L2 length, Route as non-coupled 50 ohm trace. 0.2 max L3 length, Route as non-coupled 50 ohm trace. 0.2 max Rs 33 Rt 49.9 Unit inch inch inch ohm ohm Figure 1 1 1 1 1 Down Device Differential Routing L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Dimension or Value 2 min to 16 max 1.8 min to 14.4 max Unit inch inch Figure 1 1 Differential Routing to PCI Express Connector L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Dimension or Value 0.25 to 14 max 0.225 min to 12.6 max Unit inch inch Figure 2 2 Figure 1 Down device routing. L1 L2 L4 Rs L1’ L4’ L2’ Rs Rt HSCL Output Buffer L3’ Rt PCI Ex Board Down Device REF_CLK Input L3 Figure 1 Figure 2 PCI Express Connector Routing. L1 L2 L4 Rs L1’ L2’ Rs HSCL Output Buffer L4’ Rt L3’ Rt L3 PCI Ex Add In Board REF_CLK Input Figure 2 IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) ICS9DB801C 9 REV C 08/16/07 ICS9DB801C Eight Output Differential Buffer for PCI Express (50-200MHz) Alternative termination for LVDS and other common differential signals. Figure 3. Vdiff Vp-p 0.45 v 0.22v 0.58 0.28 0.80 0.40 0.60 0.3 R1a = R1b = R1 Vcm 1.08 0.6 0.6 1.2 R1 33 33 33 33 R2 150 78.7 78.7 174 R3 100 137 none 140 R4 100 100 100 100 Note ICS874003i-02 input compatible Standard LVDS Figure_3. L1 L2 R3 L4 R1a L1’ L4’ L2’ R1b R2a HSCL Output Buffer R4 R2b Down Device REF_CLK Input L3 L3’ R2a = R2b = R2 Cable connected AC coupled application, figure 4 Component R5a,R5b R6a,R6b Cc Vcm Value 8.2K 5% 1K 5% 0.1 uF 0.350 volts Note 3.3 Volts R5a R5b L4 L4’ Cc Cc R6a R6b PCIe Device REF_CLK Input Figure_4. IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) ICS9DB801C 10 REV C 08/16/07 ICS9DB801C Eight Output Differential Buffer for PCI Express (50-200MHz) General SMBus serial interface information for the ICS9DB801C How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address DC (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Index Block Read Operation Index Block Write Operation Controller (Host) starT bit T Slave Address DC(H) WRite WR Controller (host) will send start bit. Controller (host) sends the write address DC (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address DD (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Controller (Host) T starT bit Slave Address DC(H) WR WRite ICS (Slave/Receiver) ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address DD(H) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK P X Byte ACK stoP bit Byte N + X - 1 N P IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) Not acknowledge stoP bit ICS9DB801C 11 REV C 08/16/07 ICS9DB801C Eight Output Differential Buffer for PCI Express (50-200MHz) SMBus Table: Byte 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Frequency Select Register, READ/WRITE ADDRESS (DC/DD) Control Function Type Pin # Name PD_Mode PD# drive mode RW STOP_Mode SRC_Stop# drive mode RW Reserved Reserved RW Reserved Reserved RW Reserved Reserved RW PLL_BW# Select PLL BW RW BYPASS# BYPASS#/PLL RW SRC_DIV# SRC Divide by 2 Select RW 0 1 driven Hi-Z driven Hi-Z Reserved Reserved Reserved High BW Low BW fan-out ZDB x/2 1x PWD 0 0 X X X 1 1 1 SMBus Table: Output Control Register Byte 1 Pin # Name 42,41 DIF_7 Bit 7 38,37 DIF_6 Bit 6 34,33 DIF_5 Bit 5 30,29 DIF_4 Bit 4 20,21 DIF_3 Bit 3 16,17 DIF_2 Bit 2 12,13 DIF_1 Bit 1 8,9 DIF_0 Bit 0 Control Function Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control Type RW RW RW RW RW RW RW RW 0 Disable Disable Disable Disable Disable Disable Disable Disable 1 Enable Enable Enable Enable Enable Enable Enable Enable PWD 1 1 1 1 1 1 1 1 SMBus Table: Output Control Register Byte 2 Pin # Name 42,41 DIF_7 Bit 7 38,37 DIF_6 Bit 6 34,33 DIF_5 Bit 5 30,29 DIF_4 Bit 4 20,21 DIF_3 Bit 3 16,17 DIF_2 Bit 2 12,13 DIF_1 Bit 1 8,9 DIF_0 Bit 0 Control Function Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control Type RW RW RW RW RW RW RW RW 0 Free-run Free-run Free-run Free-run Free-run Free-run Free-run Free-run 1 Stoppable Stoppable Stoppable Stoppable Stoppable Stoppable Stoppable Stoppable PWD 0 0 0 0 0 0 0 0 SMBus Table: Output Control Register Byte 3 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW 0 1 PWD X X X X X X X X IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ICS9DB801C 12 REV C 08/16/07 ICS9DB801C Eight Output Differential Buffer for PCI Express (50-200MHz) SMBus Table: Byte 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Vendor & Revision ID Register Pin # Name RID3 RID2 RID1 RID0 VID3 VID2 VID1 VID0 - SMBus Table: Byte 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DEVICE ID Pin # - SMBus Table: Byte 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte Count Register Pin # Name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 - Name Control Function Type R R R R R R R R 0 - 1 - PWD X X X X 0 0 0 1 Control Function Device ID 7 (MSB) Device ID 6 Device ID 5 Device ID 4 Device ID 3 Device ID 2 Device ID 1 Device ID 0 Type R R R R R R R R 0 1 PWD 1 0 0 0 0 0 0 1 Control Function Type RW RW RW RW RW RW RW RW 0 - 1 - PWD 0 0 0 0 0 1 1 1 REVISION ID VENDOR ID Writing to this register configures how many bytes will be read back. IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ICS9DB801C 13 REV C 08/16/07 ICS9DB801C Eight Output Differential Buffer for PCI Express (50-200MHz) Note: Polarities in timing diagrams are shown OE_INV = 0. They are similar to OE_INV = 1. PD#, Power Down The PD# pin cleanly shuts off all clocks and places the device into a power saving mode. PD# must be asserted before shutting off the input clock or power to insure an orderly shutdown. PD is asynchronous active-low input for both powering down the device and powering up the device. When PD# is asserted, all clocks will be driven high, or tri-stated (depending on the PD# drive mode and Output control bits) before the PLL is shut down. PD# Assertion When PD# is sampled low by two consecutive rising edges of DIF#, all DIF outputs must be held High, or tri-stated (depending on the PD# drive mode and Output control bits) on the next High-Low transition of the DIF# outputs. When the PD# drive mode bit is set to ‘0’, all clock outputs will be held with DIF driven High with 2 x IREF and DIF# tri-stated. If the PD# drive mode bit is set to ‘1’, both DIF and DIF# are tri-stated. PWRDWN# DIF DIF# PD# De-assertion Power-up latency is less than 1 ms. This is the time from de-assertion of the PD# pin, or VDD reaching 3.3V, or the time from valid SRC_IN clocks until the time that stable clocks are output from the device (PLL Locked). If the PD# drive mode bit is set to ‘1’, all the DIF outputs must driven to a voltage of >200 mV within 300 us of PD# de-assertion. Tstable <1mS PWRDWN# DIF DIF# Tdrive_PwrDwn# <300uS, >200mV IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) ICS9DB801C 14 REV C 08/16/07 ICS9DB801C Eight Output Differential Buffer for PCI Express (50-200MHz) SRC_STOP# The SRC_STOP# signal is an active-low asynchronous input that cleanly stops and starts the DIF outputs. A valid clock must be present on SRC_IN for this input to work properly. The SRC_STOP# signal is de-bounced and must remain stable for two consecutive rising edges of DIF# to be recognized as a valid assertion or de-assertion. SRC_STOP# - Assertion Asserting SRC_STOP# causes all DIF outputs to stop after their next transition (if the control register settings allow the output to stop). When the SRC_STOP# drive bit is ‘0’, the final state of all stopped DIF outputs is DIF = High and DIF# = Low. There is no change in output drive current. DIF is driven with 6xIREF. DIF# is not driven, but pulled low by the termination. When the SRC_STOP# drive bit is ‘1’, the final state of all DIF output pins is Low. Both DIF and DIF# are not driven. SRC_STOP# - De-assertion (transition from '0' to '1') All stopped differential outputs resume normal operation in a glitch-free manner. The de-assertion latency to active outputs is 2-6 DIF clock periods, with all DIF outputs resuming simultaneously. If the SRC_STOP# drive control bit is ‘1’ (tri-state), all stopped DIF outputs must be driven High (>200 mV) within 10 ns of de-assertion. SRC_STOP_1 (SRC_Stop = Driven, PD = Driven) 1mS SRC_Stop# PWRDWN# DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) SRC_STOP_2 (SRC_Stop =Tristate, PD = Driven) 1mS SRC_Stop# PWRDWN# DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) ICS9DB801C 15 REV C 08/16/07 ICS9DB801C Eight Output Differential Buffer for PCI Express (50-200MHz) SRC_STOP_3 (SRC_Stop = Driven, PD = Tristate) 1mS SRC_Stop# PWRDWN# DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) SRC_STOP_4 (SRC_Stop = Tristate, PD = Tristate) 1mS SRC_Stop# PWRDWN# DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) ICS9DB801C 16 REV C 08/16/07 ICS9DB801C Eight Output Differential Buffer for PCI Express (50-200MHz) c N SYMBOL L E1 E INDEX AREA 1 2 α h x 45° D A A A1 b c D E E1 e h L N α In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0° 8° In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° A1 VARIATIONS D mm. MIN MAX 15.75 16.00 -Ce SEATING PLANE b .10 (.004) C N 48 D (inch) MIN .620 MAX .630 Reference Doc.: JEDEC Publication 95, MO-118 10-0034 Ordering Information ICS9DB801CFLFT Example: ICS XXXX C F LF T Designation for tape and reel packaging Lead Free, RoHS Compliant Package Type F = SSOP Revision Designator Device Type (consists of 3 to 7 digit numbers) Prefix ICS = Standard Device IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) ICS9DB801C 17 REV C 08/16/07 ICS9DB801C Eight Output Differential Buffer for PCI Express (50-200MHz) c N 48-Lead, 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) L E1 INDEX AREA SYMBOL E A A1 A2 b c D E E1 e L N a aaa 1 2 a D A A2 A1 -Ce SEATING PLANE aaa C In Millimeters COMMON DIMENSIONS MIN MAX -1.20 0.05 0.15 0.80 1.05 0.17 0.27 0.09 0.20 SEE VARIATIONS 8.10 BASIC 6.00 6.20 0.50 BASIC 0.45 0.75 SEE VARIATIONS 0° 8° -0.10 In Inches COMMON DIMENSIONS MIN MAX -.047 .002 .006 .032 .041 .007 .011 .0035 .008 SEE VARIATIONS 0.319 BASIC .236 .244 0.020 BASIC .018 .030 SEE VARIATIONS 0° 8° -.004 VARIATIONS N b (20 mil) 48 D mm. MIN 12.40 D (inch) MAX 12.60 MIN .488 MAX .496 Reference Doc.: JEDEC Publication 95, MO-153 10-0039 Ordering Information ICS9DB801CGLFT Example: ICS XXXX C G LF T Designation for tape and reel packaging Lead Free, RoHS Compliant Package Type G = TSSOP Revision Designator Device Type (consists of 3 to 7 digit numbers) Prefix ICS = Standard Device IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) ICS9DB801C 18 REV C 08/16/07 ICS9DB801C Eight Output Differential Buffer for PCI Express (50-200MHz) Revision History Rev. Issue Date Description 0.10 04/04/05 0.20 A 04/08/05 04/08/05 B C 09/07/06 08/16/07 Page # 1. Updated Operating Supply Current Spec from Input/Supply/Common Output Parameters table. 2. Updated Ordering Information from "Lead Free" to "Annealed Lead Free". 1. Updated Min/Max BW spec 2. Added 50-200MHz nomenclature to data sheet to indicate B rev limits 3. Released Release to Final 1. Added Polarity Table. 2. Updated Electrical Characteristics. 3. Updated LF Ordering Information from "Annealed Lead Free" to "RoHS Compliant". Fixed Typo on TSSOP Ordering Information. 7,16-17 1, 7 1, 7, 16-17 18 Innovate with IDT and accelerate your future networks. Contact: www.IDT.com TM For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 408-284-6578 [email protected] Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 19