ICS ICS9FG1904BK-1LFT

ICS9FG1904B-1
Integrated
Circuit
Systems, Inc.
Frequency Generator for CPU, PCIe Gen 1, PCIe Gen 2 & FBD
Recommended Application:
Functionality at Power Up (PLL Mode)
CLK_IN (CPU FSB)
1
FS_A_410
MHz
1
100 <= CLK_IN < 200
0
200<= CLK_IN <= 400
DB1900GS/GSO with 15:4 output grouping
Features:
specifications in the Input/Supply/Common Output Parameters Table for
correct values.
Power Down Functionality
INPUTS
CKPWRGD/
CLK_IN/
PD#
CLK_IN#
1
Running
0
X
Key Specifications:
OUTPUTS
PLL State
DIF/DIF#
Running
Hi-Z
ON
OFF
DIF output cycle-to-cycle jitter < 50ps
DIF output-to-output skew < 100ps within a group
DIF_14
DIF_14#
CKPWRGD/PD#
DIF_15
DIF_15#
VDD
GND
DIF_17
DIF_17#
DIF_18
DIF_18#
OE_17_18#
CLK_IN
Pin Configuration
CLK_IN#
SMB_A2_PLLBYP#
•
•
OE_15_16#
•
•
•
•
1. FS_A_410 is a low-threshold input. Please see the VIL_FS and VIH_FS
DIF_ 16
•
Power up default is all outputs in 1:1 mode
DIF_(14:0) can be “gear-shifted” from the input CPU
Host Clock
DIF_(18:15) can be “gear-shifted” from the input CPU
Host Clock
Spread spectrum compatible
Supports output clock frequencies up to 400 MHz
8 Selectable SMBus addresses
SMBus address determines PLL or Bypass mode
DIF_16#
•
•
DIF_(18:0)
MHz
CLK_IN
CLK_IN
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
IREF
GNDA
VDDA
HIGH_BW#
FS_A_410
DIF_0
DIF_0#
DIF_1
DIF_1#
GND
VDD
DIF_2
DIF_2#
DIF_3
DIF_3#
DIF_4
DIF_4#
OE_01234#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
ICS9FG1904-1
OE14#
DIF_13#
DIF_13
OE13#
DIF_12#
DIF_12
OE12#
VDD
GND
DIF_11#
DIF_11
OE11#
DIF_10#
DIF_10
OE10#
DIF_9#
DIF_9
OE9#
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
SMB_A1
SMB_A0
DIF_8#
DIF_8
OE8#
DIF_7#
DIF_7
OE7#
GND
VDD
DIF_6#
DIF_6
OE6#
DIF_5#
DIF_5
OE5#
SMBDAT
SMBCLK
72-pin MLF
1255B—08/03/07
Other names and brands may be claimed as the property of others.
Integrated
Circuit
Systems, Inc.
ICS9FG1904B-1
Pin Description
PIN #
PIN NAME
PIN TYPE
1
IREF
OUT
2
3
GNDA
VDDA
PWR
PWR
4
HIGH_BW#
IN
5
FS_A_410
IN
6
7
8
9
10
11
12
13
14
15
16
17
DIF_0
DIF_0#
DIF_1
DIF_1#
GND
VDD
DIF_2
DIF_2#
DIF_3
DIF_3#
DIF_4
DIF_4#
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
18
OE_01234#
IN
19
20
SMBCLK
SMBDAT
IN
I/O
21
OE5#
IN
22
23
DIF_5
DIF_5#
24
OE6#
25
26
27
28
DIF_6
DIF_6#
VDD
GND
29
OE7#
30
31
DIF_7
DIF_7#
32
OE8#
33
34
35
36
DIF_8
DIF_8#
SMB_A0
SMB_A1
OUT
OUT
IN
OUT
OUT
PWR
PWR
IN
OUT
OUT
IN
OUT
OUT
IN
IN
DESCRIPTION
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in order
to establish the appropriate current. 475 ohms is the standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
3.3V tolerant low threshold input for CPU frequency selection. This pin
requires CK410 FSA. Refer to input electrical characteristics for Vil_FS and
Vih_FS threshold values.
0.7V differential true clock output
0.7V differential complement clock output
0.7V differential true clock output
0.7V differential complement clock output
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential complement clock output
0.7V differential true clock output
0.7V differential complement clock output
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pairs 0, 1, 2, 3 and 4.
1 = tri-state outputs, 0 = enable outputs
Clock pin of SMBUS circuitry, 5V tolerant
Data pin of SMBUS circuitry, 5V tolerant
Active low input for enabling DIF pair 5.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 6.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
Ground pin.
Active low input for enabling DIF pair 7.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 8.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
SMBus address bit 0 (LSB)
SMBus address bit 1
1255B—08/03/07
2
Integrated
Circuit
Systems, Inc.
ICS9FG1904B-1
Pin Description (Continued)
PIN #
PIN NAME
PIN TYPE
37
OE9#
IN
38
39
DIF_9
DIF_9#
OUT
OUT
40
OE10#
IN
41
42
DIF_10
DIF_10#
43
OE11#
44
45
46
47
DIF_11
DIF_11#
GND
VDD
48
OE12#
49
50
DIF_12
DIF_12#
51
OE13#
52
53
DIF_13
DIF_13#
54
OE14#
55
56
DIF_14
DIF_14#
57
CKPWRGD/PD#
58
59
DIF_15
DIF_15#
60
OE_15_16#
61
62
63
64
65
66
67
68
DIF_ 16
DIF_16#
VDD
GND
DIF_17
DIF_17#
DIF_18
DIF_18#
69
OE_17_18#
IN
70
71
CLK_IN
CLK_IN#
IN
IN
72
SMB_A2_PLLBYP#
IN
OUT
OUT
IN
OUT
OUT
PWR
PWR
IN
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
DESCRIPTION
Active low input for enabling DIF pair 9.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 10.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 11.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Ground pin.
Power supply, nominal 3.3V
Active low input for enabling DIF pair 12.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 13.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 14.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
A rising edge samples latched inputs and release Power Down Mode, a low
puts the part into power down mode and tristates all outputs.
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 15 and 16.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential complement clock output
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 17, 18.
1 = tri-state outputs, 0 = enable outputs
Input for reference clock.
"Complementary" reference clock input.
SMBus address bit 2. When Low, the part operates as a fanout buffer with the
PLL bypassed. When High, the part operates as a zero-delay buffer (ZDB) with
the PLL operating.
0 = fanout mode (PLL bypassed), 1 = ZDB mode (PLL used)
1255B—08/03/07
3
Integrated
Circuit
Systems, Inc.
ICS9FG1904B-1
General Description
ThThe ICS9FG1904-1 follows the Intel DB1900GS Differential Buffer Specification, except for the output groupings and gear
table. The gear table is a blend of the GS and GSO gearing. This buffer provides 19 output clocks for CPU Host Bus, PCIExpress, or Fully Buffered DIMM applications. The outputs are configured with two groups. Both groups, DIF_(14:0) and
DIF_(18:15) can be equal to or have a gear ratio to the input clock. A differential CPU clock from a CK410B+ main clock
generator, such as the ICS932S421, drives the ICS9FG1904-1. The ICS9FG1904-1 can provide outputs up to 400MHz.
Block Diagram
OE_17_18#
OE_15_16#
OE(14:5)#,
OE_01234#
2
SPREAD
COMPATIBLE
1:1 PLL
4
SPREAD
COMPATIBLE
GEARING PLL
15
DIF(18:15)
11
CLK_IN
CLK_IN#
HIGH_BW#
FS_A_410
CKPWRGD/PD#
SMB_A0
SMB_A1
SMB_A2_PLLBYP#
SMBDAT
SMBCLK
DIF(14:0)
CONTROL
LOGIC
IREF
Power Groups
Pin Number
VDD
GND
3
2
11,27,47,63 10,28,46,64
Description
Main PLLs, Analog
DIF clocks
1255B—08/03/07
4
Integrated
Circuit
Systems, Inc.
ICS9FG1904B-1
ICS 9FG1904B-1 Programmable Gear Ratios
CLK_IN
(CPU FSB)
MHz
Geared DIF
Outputs
MHz
100.00
100.00
100.00
100.00
100.00
100.00
133.33
133.33
133.33
133.33
133.33
166.67
166.67
166.67
160/
166.67
166.67
200.00
200.00
200.00
200.00
200.00
266.67
266.667/
320.00
266.67
333.33
320/
333.33
333.33
400.00
400.00
400.00
400.00
400.00
133.33
166.67
200.00
266.67
333.33
400.00
166.67
200.00
266.67
333.33
100.00
133.33
200.00
266.67
320/
333.33
400.00
133.33
166.67
266.67
333.33
400.00
133.33
166.67/
200.00
200.00
133.33
160/
166.67
200.00
133.33
160.00
166.67
320.00
333.33
M
Gear
n
Ratio n/M
3
3
1
3
3
1
4
2
1
2
4
5
5
5
4
5
2
8
10
4
5
3
2
5
3
4
6
8
1.333
1.667
2.000
2.667
3.333
4.000
1.250
1.500
1.250
1.500
0.750
0.800
1.200
1.600
(FS_A_410#)
Byte 0,
bit 4
FS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
2
2.000
5
3
6
3
3
1
2
12
2
5
4
5
2
1
8
Byte 0, Byte 0, Byte 0, Byte 0,
bit 3
bit 2
bit 1
bit 0
FS3
FS2
FS1
FS0
Notes
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1,2
2.400
0.667
0.833
1.333
1.667
2.000
0.500
0
1
1
1
1
1
1
1
0
0
0
0
0
0
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
1
1
1
1
1
1
5
0.625
1
0
1
1
0
1, 6
4
5
3
2
0.750
0.400
1
1
0
1
1
0
1
0
1
0
1
1
2
1
0.500
1
1
0
0
1
1,5
5
3
5
12
5
6
3
1
2
5
4
5
0.600
0.333
0.400
0.417
0.800
0.833
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
1
1,4
1
1
1
1
Notes:
1. Targetted input/output frequency pairs
2. This Gear is also used for 160MHz/320 MHz.
3. Gear Ratio 5/4 is power up default for FS_A_410 = 1
4. Gear Ratio 3/1 is power up default for FS_A_410 = 0
5. This Gear is also used for 400MHz/200MHz
6. This Gear is also used for 320MHz/200MHz
1255B—08/03/07
5
1
1
1,3
1
Integrated
Circuit
Systems, Inc.
ICS9FG1904B-1
ICS 9FG1904B-1 1:1 PLL Programming
Byte 9,
bit 2
FSC
Byte9,
bit 1
FSB
Byte 9,
bit 0
FS_A_410
1
0
1
0
0
1
0
1
1
0
1
0
0
0
0
1
0
0
1
1
1
1
0
1
CLK_IN
1:1 DIF
(CPU FSB)
Outputs
MHz
MHz
100.00
100.00
133.33
133.33
166.67
166.67
200.00
200.00
266.67
266.67
333.33
333.33
400.00
400.00
Reserved
Notes
3
3
1
3
3
3
2
Notes:FS_A_410 = 1
1. Powerup Default for FS_A_410 = 1
2. Powerup Default for FS_A_410 = 0
3. Setting the exact FSB frequency after Power is required for best phase noise performance.
Output Divider Ratios
Binary
Desired
Value to
Decimal
write to
Value
Register
2
0000
3
0001
5
0010
7
0011
4
0100
6
0101
10
0110
14
0111
8
1000
12
1001
20
1010
28
1011
16
1100
24
1101
40
1110
56
1111
1255B—08/03/07
6
Integrated
Circuit
Systems, Inc.
ICS9FG1904B-1
Absolute Max
PARAMETER
3.3V Core Supply Voltage
3.3V Logic Supply Voltage
SYMBOL
VDD_A
VDD_In
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
Ts
Tambient
Tcase
ESD prot
CONDITIONS
MIN
GND - 0.5
GND - 0.5
TYP
-65
0
Human Body Model
MAX
UNITS
VDD + 0.5V
V
V
VDD + 0.5V
C
°C
°C
V
Notes
1
1
1
1
1
1
MAX
VDD + 0.3
UNITS
V
Notes
1
0.8
5
V
uA
1
150
70
115
2000
°
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
Input High Voltage
VIH
Input Low Voltage
Input High Current
VIL
IIH
Input Low Current
I IL1
Low Threshold InputHigh Voltage
VIH_FS
Low Threshold InputLow Voltage
Operating Current
Powerdown Current
Input Frequency
Pin Inductance
Input Capacitance
Clk Stabilization
VIL_FS
IDD3.3OP
IDD3.3PD
Fi
Lpin
CIN
COUT
TSTAB
Modulation Frequency
Tdrive_PD#
Tfall_Pd#
Trise_Pd#
SMBus Voltage
Low-level Output Voltage
Current sinking at
VOL = 0.4 V
SCLK/SDATA
Clock/Data Rise Time
SCLK/SDATA
Clock/Data Fall Time
VMAX
VOL
CONDITIONS
3.3 V +/-5%
MIN
2
3.3 V +/-5%
VIN = VDD
VIN = 0 V; Inputs with no pull-up
resistors
VSS - 0.3
-5
3.3 V +/-5%, Applies to FS_A_410
pin
TFI2C
-5
uA
0.7
3.3 V +/-5%, Applies to FS_A_410
VSS - 0.3
pin
all outputs driven
all differential pairs tri-stated
VDD = 3.3 V
100
Logic Inputs
Output pin capacitance
From VDD Power-Up or deassertion of PD# to 1st clock
Triangular Modulation
DIF output enable after
PD# de-assertion
PD# fall time of
PD# rise time of
Maximum input voltage
@ I PULLUP
IPULLUP
TRI2C
TYP
VDD + 0.3
V
1
0.35
V
1
500
30
400
7
5
mA
mA
MHz
nH
pF
pF
1
1
3
1
1
1
1.8
ms
1
33
kHz
1
300
us
1
5
5
5.5
0.4
ns
ns
V
V
1
2
1
1
mA
1
1000
ns
1
300
ns
1
2.5
30
4
(Max VIL - 0.15) to
(Min VIH + 0.15)
(Min VIH + 0.15) to
(Max VIL - 0.15)
1255B—08/03/07
7
Integrated
Circuit
Systems, Inc.
ICS9FG1904B-1
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω
PARAMETER
Current Source Output
Impedance
SYMBOL
Voltage High
VHigh
Zo
CONDITIONS
MIN
VO = Vx
3000
Statistical measurement on single
ended signal using oscilloscope
math function.
Measurement on single ended
signal using absolute value.
660
1
Voltage Low
VLow
Max Voltage
Min Voltage
Vovs
Vuds
Crossing Voltage (abs)
Vcross(abs)
Crossing Voltage (var)
d-Vcross
Variation of crossing over all edges
Long Accuracy
ppm
Average period
Tperiod
Absolute min period
Tabsmin
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
tr
tf
d-tr
d-tf
see Tperiod min-max values
400MHz nominal
400MHz spread
333.33MHz nominal
333.33MHz spread
266.66MHz nominal
266.66MHz spread
200MHz nominal
200MHz spread
166.66MHz nominal
166.66MHz spread
133.33MHz nominal
133.33MHz spread
100.00MHz nominal
100.00MHz spread
400MHz nominal/spread
333.33MHz nominal/spread
266.66MHz nominal/spread
200MHz nominal/spread
166.66MHz nominal/spread
133.33MHz nominal/spread
100.00MHz nominal/spread
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
Duty Cycle
dt3
Jitter, Cycle to cycle
tJCYC-CYC
tJBYP
TYP
MAX
Ω
850
1,3
-150
150
1150
-300
550
1,3
mV
1
1
mV
1
140
mV
1
0
2.4993
2.4993
2.9991
2.9991
3.7489
3.7489
4.9985
4.9985
5.9982
5.9982
7.4978
7.4978
9.9970
9.9970
2.4143
2.9141
3.6639
4.8735
5.8732
7.3728
9.8720
175
175
0
2.5008
2.5133
3.0009
3.016
3.7511
3.77
5.0015
5.0266
6.0018
6.0320
7.5023
7.5400
10.0030
10.0533
700
700
125
125
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
1,2,7
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1
1
1
1
45
55
%
1
50
ps
1,4,5
50
ps
1,4
Bypass mode as additive jitter
Notes:
1.Guaranteed by design and characterization, not 100% tested in production.
2. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that the input frequency meets CK410 accuracy requirements
3.IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
4. Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.
5. Measured from differential cross-point to differential cross-point
6. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.
7. This device does not introduce any ppm errors to the input clock.
1255B—08/03/07
8
1
mV
250
Measurement from differential
wavefrom
PLL mode,
from differential wavefrom
UNITS NOTES
Integrated
Circuit
Systems, Inc.
ICS9FG1904B-1
Electrical Characteristics - Skew and Differential Jitter Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
Group
Parameter
Description
Input-to-Output Skew in PLL mode (1:1 only),
tSPO_PLL
CLK_IN, DIF[x:0]
nominal value @ 25°C, 3.3V
Input-to-Output Skew in Bypass mode (1:1 only),
tPD_BYP
CLK_IN, DIF[x:0]
nominal value @ 25°C, 3.3V
Input-to-Output Skew Variation in PLL mode
CLK_IN, DIF [x:0] ∆tSPO_PLL
(over specified voltage / temperature operating ranges)
Min
Max Units Notes
-500
500
ps
1,2,4,5,8
2.5
4.5
ns
1,2,3,5
|350|
ps
1,2,4,5,6,
10
|500|
ps
1,2,3,4,5,
6,10
100
ps
1,2
50
ps
1.2
150
ps
1,2,3
10
ps
1,4,7
80
ps
1,4,9
Input-to-Output Skew Variation in Bypass mode
(over specified voltage / temperature operating ranges)
CLK_IN, DIF [x:0]
∆tPD_BYP
DIF[14:0]
tSKEW_G15
DIF[18:15]
tSKEW_G4
DIF[18:0]
tSKEW_A19
DIF[18:0]
tJPH
DIF[18:0]
tSSTERROR
Output-to-Output Skew Group of 15
(Common to Bypass and PLL mode)
Output-to-Output Skew Group of 4 (Common to Bypass and PLL
mode)
Output-to-Output Skew across all 19 outputs
(Common to Bypass and PLL mode - all outputs at same gear)
Differential Phase Jitter (RMS Value)
Differential Spread Spectrum Tracking Error (peak to peak)
NOTES:
1. Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.
2. Measured from differential cross-point to differential cross-point
3. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.
4. This parameter is deterministic for a given device
5. Measured with scope averaging on to find mean value.
6. Long-term variation from nominal of input-to-output skew over temperature and voltage for a single device.
7. This parameter is measured at the outputs of two separate ICS9FG1900 devices driven by a single CK410B. The ICS9FG1900's must be set to high
bandwidth. Differential phase jitter is the accumulation of the phase jitter not shared by the outputs (eg. not including the affects of spread spectrum). Target
ranges of consideration are agents with BW of 1-22Mhz and 11-33Mhz.
8. t is the period of the input clock
9. Differential spread spectrum tracking error is the difference in spread spectrum tracking between two ICS9FG1900 devices This parameter is measured at
the outputs of two separate ICS9FG1900 devices driven by a single CK410B in Spread Spectrum mode. The ICS9FG1900's must be set to high bandwidth.
The spread spectrum characteristics are: maximum of 0.5%, 30-33KHz modulation frequency, linear profile.
10. This parameter is an absolute value. It is not a double-sided figure.
Electrical Characteristics - Phase Jitter Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, when driven by 932S421B or equivalent
PARAMETER
Symbol
Conditions
Min
Typ
t jphPCIe1
PCIe Gen 1
PCIe Gen 2
t jphPCIe2Lo
10kHz < f < 1.5MHz
Jitter, Phase
t jphPCIe2Hi
t jphFBD1_3.2G
t jphFBD1_4.0G
PCIe Gen 2
1.5MHz < f < Nyquist (50MHz)
FBD1 3.2/4G
11MHz to 33MHz
FBD1 4.8G
11MHz to 33MHz
Notes:
Guaranteed by design and characterization, not 100% tested in production.
2
See http://www.pcisig.com for complete specs
1
1255B—08/03/07
9
Max
108
Units
ps (p-p)
Notes
1,2
3
ps (RMS)
1,2
3.1
ps (RMS)
1,2
3
ps (RMS)
1,2
2.5
ps (RMS)
1,2
Integrated
Circuit
Systems, Inc.
ICS9FG1904B-1
Programming the 9FG1904B-1
The 9FG1904B-1 uses advanced power saving features to detect when only geared outputs or only 1:1 outputs are
needed. It then shuts down the unused PLL. At power up all outputs are coming from the 1:1 PLL and the Gear PLL
is shut down. This power saving feature requires a little care when configuring the gear outputs in the device.
Configuring Gear Outputs of the 9FG1904B-1
Selecting Pre-configured Gear Ratios
Byte 0 contains both the bits that enable the gear ratio outputs (Bits 7 and 6), and the bits that select the actual gear
ratio (bits (4:0)). It is tempting to enable the gearing outputs and select the gear ratio at the same time. However, this
can result in the inability to obtain the proper output frequency. Due to the power saving feature, it is necessary to perform
this operation as two steps:
1. First, enable outputs to the gear ratio PLL, which actually powers up the gear ratio PLL (Set Byte 0, bits 7 and
6)
2. Then select the desired gear ratio in a separate write to byte 0 (Set Byte 0, bits (4:0)
The actual order of the two operations is unimportant, so steps 1 and 2 could be reversed if desired.
Programming Gear Ratios that are not Pre-Configured
Most applications using the 9FG1904B-1 can obtain the desired output frequencies from the selections built into the
gear table. There are two gear tables defined for these devices. There is the original GS gear set indicated by the
DBxxxxGS yellow cover designation and the newer optimized GSO gear set indicated by DBxxxxGSO yellow cover
designation. The 9FG1904B-1 contains a gear set that is a combination of the GS and GSO gear sets. The differences
between the GS and GSO gear sets are highlighted in Figure 1 GS versus GSO versus 9FG1904B-1 Gear Ratios.
Any gear in the GS or the GSO table that is not pre-configured in the 9FG1904B-1, and virtually any other input/output
combination can be obtained by use of M/N programming. Note that care must be used or the jitter/bandwidth
characteristics of the PLL can be compromised.
The values provided later in this document have been verified to preserve the PLL performance of the device. Refer
to the section Using M/N Programming to Obtain Other Gear Ratios for additional details.
1255B—08/03/07
10
Integrated
Circuit
Systems, Inc.
ICS9FG1904B-1
GS Gear Ratios
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CLK_IN
(CPU FSB)
MHz
Geared DIF
Outputs
MHz
100.00
100.00
100.00
100.00
100.00
100.00
133.33
133.33
133.33
133.33
133.33
166.67
166.67
166.67
160/
166.67
166.67
200.00
200.00
200.00
200.00
200.00
266.67
266.667/
320
266.67
333.33
320/
333.33
333.33
400.00
400.00
400.00
400.00
400.00
133.33
166.67
200.00
266.67
333.33
400.00
166.67
200.00
266.67
333.33
400.00
133.33
200.00
266.67
320/
333.33
400.00
133.33
166.67
266.67
333.33
400.00
133.33
166.67/
200
200.00
133.33
160/
166.67
200.00
133.33
160.00
166.67
320.00
333.33
GSO Gear Ratios
Gear
Ratio
n/M
M n
3 4 1.33
3 5 1.67
1 2 2.00
3 8 2.67
3 10 3.33
1 4 4.00
4 5 1.25
2 3 1.50
1 2 1.25
2 5 1.50
1 3 3.00
5 4 0.80
5 6 1.20
5 8 1.60
1
100.00
100.00
100.00
100.00
100.00
133.33
133.33
133.33
133.33
133.33
133.33
166.67
166.67
166.67
Geared
DIF
Outputs
MHz
133.33
166.67
200.00
266.67
333.33
100.00
166.67
200.00
266.67
333.33
400.00
133.33
200.00
266.67
M
3
3
1
3
3
4
4
2
1
2
1
5
5
5
n
4
5
2
8
10
3
5
3
2
5
3
4
6
8
CLK_IN
(CPU FSB)
MHz
2
2.00
166.67
333.33
1
2
5 12
3 2
6 5
3 4
3 5
1 2
2 1
2.40
0.67
0.83
1.33
1.67
2.00
0.50
166.67
200.00
200.00
200.00
200.00
200.00
266.67
400.00
133.33
166.67
266.67
333.33
400.00
133.33
5
3
6
3
3
1
2
12
2
5
4
5
2
1
8
5
0.63
266.67
166.67
8
5
4
5
3
2
0.75
0.40
266.67
333.33
200.00
133.33
4
5
3
2
2
1
0.50
333.33
166.67
2
1
5
3
5
12
5
6
3
1
2
5
4
5
0.60
0.33
0.40
0.42
0.80
0.83
333.33
400.00
400.00
400.00
400.00
400.00
200.00
133.33
166.67
200.00
266.67
333.33
5
3
12
2
6
6
3
1
5
1
4
5
9FG1904-1 Gear Ratios
CLK_IN
Gear
(CPU FSB)
Ratio
MHz
n/M
1.33
100.00
1.67
100.00
2.00
100.00
2.67
100.00
3.33
100.00
0.75
100.00
1.25
133.33
1.50
133.33
2.00
133.33
2.50
133.33
3.00
133.33
0.80
166.67
1.20
166.67
1.60
166.67
160/
2.00
166.67
2.40
166.67
0.67
200.00
0.83
200.00
1.33
200.00
1.67
200.00
2.00
200.00
0.50
266.67
266.667/
0.63
320.00
0.75
266.67
0.40
333.33
320/
0.50
333.33
0.60
333.33
0.33
400.00
0.42
400.00
0.50
400.00
0.67
400.00
0.83
400.00
Figure 1 GS versus GSO versus 9FG1904B-1 Gear Ratios
1255B—08/03/07
11
Geared
DIF
Outputs
M
MHz
133.33
3
166.67
3
200.00
1
266.67
3
333.33
3
400.00
1
166.67
4
200.00
2
266.67
1
333.33
2
100.00
4
133.33
5
200.00
5
266.67
5
320/
1
333.33
400.00
5
133.33
3
166.67
6
266.67
3
333.33
3
400.00
1
133.33
2
166.67/
8
200.00
200.00
4
133.33
5
160/
2
166.67
200.00
5
133.33
3
160.00
5
166.67 12
320.00
5
333.33
6
n
4
5
2
8
10
4
5
3
2
5
3
4
6
8
Gear
Ratio
n/M
1.33
1.67
2.00
2.67
3.33
4.00
1.25
1.50
1.25
1.50
0.75
0.80
1.20
1.60
2
2.00
12
2
5
4
5
2
1
2.40
0.67
0.83
1.33
1.67
2.00
0.50
5
0.63
3
2
0.75
0.40
1
0.50
3
1
2
5
4
5
0.60
0.33
0.40
0.42
0.80
0.83
Integrated
Circuit
Systems, Inc.
ICS9FG1904B-1
Using M/N Programming to Obtain Other Gear Ratios
M/N programming can be used to obtain input output frequency combinations that are not preconfigured in the
9FG1904B-1. Refer to Figure 2 PLL Block Diagram.
The internal architecture of the 9FG1904B-1 is standard pseudo-ZDB architecture with internal feedback. This means
that the REF divider, the Output divider and the Feedback divider all play a role in determining the output frequency.
The output frequency is given by the equation:
Output Frequency = (Input Frequency x N x Output Div)/M
REF (M)
DIV
Input
Clock
OUTPUT
DIV
vco
FBK (N)
DIV
BUFFERS
Output
Clocks
Figure 2 PLL Block Diagram
The DBxxxxGSO input/output combinations that are not in the 9FG1904B-1 gear table are shown in Table 1 DBxxxxGSO
Gears Not Present in the 9FG1904B-1. This table also gives the values needed to program the gearing PLL to provide
the desired input/output combination.
1
0 133.33 400.00
4
12
2
3.000
2
1 400.00 200.00
12
6
4
0.500
3
1 400.00 266.67
12
8
3
0.667
Table 1 DBxxxxGSO Gears Not Present in the 9FG1904B-1
2
A
A
A
4
6
Byte
19
Byte
13
Output Div
(Hex)
Byte
18
Byte
12
VCO N Div
(Hex)
Gear
Decimal Post
Divider
Decimal N
Value
Decimal M
Value
Output
Frequency
Input
Frequency
(Fref)
Line
FS_A_410#
Gear PLL Bytes
Byte
17
Byte
11
REF M Div
(Hex)
1:1 PLL Bytes
0
4
1
Note before the M/N programming can be accomplished, Byte 10, bit 7 (the M/N_Enable bit) must be set to a ‘1’. The
values provided in the table above have been verified to meet the specified performance of the 9FG1901B-1.
Performance is not guaranteed for any other values that have not been pre-approved by IDT. Contact your local IDT
representative for other values not mentioned here.
Setting the 1:1 PLL Operating Point
After configuring the Gearing outputs, it is also necessary to set the 1:1 PLL operating point by writing the input
frequency value to Byte 9 bits (2:0). The input frequency is usually the CPU HCLK frequency.
1255B—08/03/07
12
Integrated
Circuit
Systems, Inc.
ICS9FG1904B-1
9FG1904-1 SMBus Address Mapping
when using CK410/CK410B, 9FG1200, and
9DB401/801
PLL B YPAS S M ODE
S MB _A 2_PLLB YP# = 0
SMB_A(2:0) = 000
SMB Adr: D0
9FG1904-1
(DB1900GS)
SMB_A(2:0) = 001
SMB Adr: D2
9FG1904-1
(DB1900GS)
SMB_A(2:0) = 010
SMB Adr: D4
9FG1904-1
(DB1900GS)
SMB_A(2:0) = 011
SMB Adr: D6
9FG1904-1
(DB1900GS)
SMB_A(2:0) = 100
SMB Adr: D8
9FG1904-1
(DB1900GS)
P LL ZD B M ODE
SM B_A2_PLLBYP# = 1
SMB_A(2:0) = 101
SMB Adr: DA
9FG1904-1
(DB1900GS)
SMB_A(2:0) = 110
SMB Adr: DC
9FG1904-1
(DB1900GS)
SMB_A(2:0) = 111
SMB Adr: DE
9FG1904-1
(DB1900GS)
OR
OR
OR
OR
OR
OR
OR
OR
SMB_A(2:0) = 000
SMB Adr: D0
9FG1200-1
(DB1200GS)
SMB_A(2:0) = 001
SMB Adr: D2
9FG1200-1
(DB1200GS)
OR
SMB Adr: D2
954101
932S401
(CK410/410B)
OR
SMB Adr: DC
9DB401/801
(DB400/800)
SMB_A(2:0) = 010
SMB Adr: D4
9FG1200-1
(DB1200GS)
SMB_A(2:0) = 011
SMB Adr: D6
`
9FG1200-1
(DB1200GS)
SMB_A(2:0) = 100
SMB Adr: D8
9FG1200-1
(DB1200GS)
SMB_A(2:0) = 101
SMB Adr: DA
9FG1200-1
(DB1200GS)
SMB_A(2:0) = 110
SMB Adr: DC
9FG1200-1
(DB1200GS)
SMB_A(2:0) = 111
SMB Adr: DE
9FG1200-1
(DB1200GS)
1255B—08/03/07
13
Integrated
Circuit
Systems, Inc.
ICS9FG1904B-1
General SMBus serial interface information for the ICS9FG1904B-1
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address *D0 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address *D0(H)
WR
WRite
Controller (host) will send start bit.
Controller (host) sends the write address *D0 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address *D1 (H)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Read Operation
Controller (Host)
T
starT bit
Slave Address *D0(H)
WR
WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address *D1(H)
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
Byte N + X - 1
ACK
P
stoP bit
* The SMBus Address of this device is programmable.
See the preceding page for details on how to set the
SMBus address.
Byte N + X - 1
N
P
1255B—08/03/07
14
Not acknowledge
stoP bit
Integrated
Circuit
Systems, Inc.
ICS9FG1904B-1
SMBusTable: Gear Ratio Select Register
Pin #
Name
Control Function
Byte 0
Group of 15 gear ratio enable
Bit 7 DIF(14:0)
Group of 4 gear ratio enable
Bit 6 DIF(18:15)
Reserved
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
Gear Ratio FS4 (Inverse of FS_A_410 input!)
Gear Ratio FS3
Gear Ratio FS2
Gear Ratio FS1
Gear Ratio FS0
SMBusTable: Output Control Register
Pin #
Name
Byte 1
DIF_7
Bit 7
DIF_6
Bit 6
DIF_5
Bit 5
DIF_4
Bit 4
DIF_3
Bit 3
DIF_2
Bit 2
DIF_1
Bit 1
DIF_0
Bit 0
0
Type
RW Gear Ratio
RW Gear Ratio
RW
RW
RW
RW
RW
RW
Control Function
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
1
1:1
1:1
Type
RW
RW
RW
RW
RW
RW
RW
RW
Latch
See ICS9FG1904-1
Programmable Gear
Ratios Table
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
SMBusTable: Output and PLL BW Control Register
Byte 2
0
1
Pin #
Name
Control Function
Type
RW
High BW
Low BW
see note
PLL_BW# adjust
Bit 7
RW
Bypass
PLL
see note
BYPASS# test mode / PLL
Bit 6
DIF_13
Output Control
RW
Hi-Z
Enable
Bit 5
DIF_12
Output Control
RW
Hi-Z
Enable
Bit 4
DIF_11
Output Control
RW
Hi-Z
Enable
Bit 3
DIF_10
Output Control
RW
Hi-Z
Enable
Bit 2
DIF_9
Output Control
RW
Hi-Z
Enable
Bit 1
DIF_8
Output Control
RW
Hi-Z
Enable
Bit 0
Note: Bit 7 is wired OR to the HIGH_BW# input, any 0 selects High BW
Note: Bit 6 is wired OR to the SMB_A2_PLLBYP# input, any 0 selects Fanout Bypass mode
SMBusTable: Output Enable Readback Register
Byte 3
Pin #
Name
Control Function
Readback
OE9#
Input
Bit 7
Readback - OE8# Input
Bit 6
Readback - OE7# Input
Bit 5
Readback - OE6# Input
Bit 4
Readback - OE5# Input
Bit 3
Readback - OE_01234# Input
Bit 2
Readback - HIGH_BW# In
8
Bit 1
Readback - SMB_A2_PLLBYP# In
72
Bit 0
1255B—08/03/07
15
Type
R
R
R
R
R
R
R
R
PWD
1
1
1
0
1
Readback
Readback
Readback
Readback
Readback
Readback
Readback
Readback
1
0
1
1
PWD
1
1
1
1
1
1
1
1
PWD
1
1
1
1
1
1
1
1
PWD
X
X
X
X
X
X
X
X
Integrated
Circuit
Systems, Inc.
ICS9FG1904B-1
SMBusTable: Output Enable Readback Register
Byte 4
Pin #
Name
Control Function
69
Readback - OE17_18# Input
Bit 7
60
Readback - OE15_16# Input
Bit 6
Reserved
Bit 5
54
Readback - OE14# Input
Bit 4
51
Readback - OE13# Input
Bit 3
48
Readback - OE12# Input
Bit 2
43
Readback - OE11# Input
Bit 1
40
Readback - OE10# Input
Bit 0
Type
R
R
0
1
PWD
X
X
X
X
X
X
X
X
Readback
Readback
Readback
Readback
Readback
Readback
Readback
R
R
R
R
R
SMBusTable: Vendor & Revision ID Register
Pin #
Name
Control Function
Byte 5
RID3
Bit 7
RID2
Bit 6
REVISION ID
RID1
Bit 5
RID0
Bit 4
VID3
Bit 3
VID2
Bit 2
VENDOR ID
VID1
Bit 1
VID0
Bit 0
Type
R
R
R
R
R
R
R
R
0
-
1
-
PWD
0
0
0
1
0
0
0
1
SMBusTable: DEVICE ID
Pin #
Byte 6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
1
0
0
1
0
1
0
0
Type
RW
RW
RW
Writing to this register
RW
configures how many
RW
bytes will be read back.
RW
RW
RW
0
-
1
-
PWD
0
0
0
0
0
1
1
1
Name
Control Function
Device ID 7 (MSB)
Device ID 6
Device ID 5
Device ID 4
Device ID 3
Device ID 2
Device ID 1
Device ID 0
SMBusTable: Byte Count Register
Byte 7
Pin #
Name
BC7
Bit 7
BC6
Bit 6
BC5
Bit 5
BC4
Bit 4
BC3
Bit 3
BC2
Bit 2
BC1
Bit 1
BC0
Bit 0
Control Function
1255B—08/03/07
16
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Integrated
Circuit
Systems, Inc.
ICS9FG1904B-1
SMBusTable: Control Pin Readback Register
Name
Control Function
Pin #
Byte 8
5
Readback - FS_A_410
Bit 7
RESERVED
Bit 6
RESERVED
Bit 5
DIF_18
Output Control
Bit 4
DIF_17
Output Control
Bit 3
DIF_16
Output Control
Bit 2
DIF_15
Output Control
Bit 1
DIF_14
Output Control
Bit 0
SMBusTable: 1:1 PLL Operating Set Point Register
Pin #
Name
Control Function
Byte 9
RESERVED
Bit 7
RESERVED
Bit 6
RESERVED
Bit 5
RESERVED
Bit 4
RESERVED
Bit 3
Frequency Select C
Bit 2
Frequency Select B
Bit 1
Bit 0
-
FS_A_410
Type
R
0
RW
RW
RW
RW
RW
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Enable
Enable
Enable
Enable
Enable
Type
0
1
RW
RW
RW
SMBus Table: M/N Programming & Watchdog Safe Register
Pin #
Name
Control Function
Byte 10
Gear and 1:1 PLL M/N
M/N_EN
Bit 7
Programming Enable
RESERVED
Bit 6
RESERVED
Bit 5
RESERVED
Bit 4
RESERVED
Bit 3
RESERVED
Bit 2
RESERVED
Bit 1
RESERVED
Bit 0
SMBus Table: Gear PLL Frequency Control Register
Byte 11
Pin #
Name
Control Function
RESERVED
Bit 7
RESERVED
Bit 6
Gear PLL M Div5
Bit 5
Gear PLL M Div4
Bit 4
Gear PLL M Div3
Bit 3
M Divider
Gear PLL M Div2
Bit 2
Gear PLL M Div1
Bit 1
Gear PLL M Div0
Bit 0
1255B—08/03/07
17
1
Readback
See ICS9FG1904 1:1
PLL Programming Table
PWD
X
X
X
1
1
1
1
1
PWD
0
0
0
0
0
x
1
Latch
Type
0
1
PWD
RW
Disable
Enable
0
X
X
X
X
X
X
X
Type
RW
RW
RW
RW
RW
RW
0
1
PWD
X
X
X
X
See M/N Programming Section
X
of the Data Sheet
X
X
X
Integrated
Circuit
Systems, Inc.
ICS9FG1904B-1
SMBus Table: Gear PLL Frequency Control Register
Byte 12
Pin #
Name
Control Function
Gear PLL N Div7
Bit 7
Gear PLL N Div6
Bit 6
Gear PLL N Div5
Bit 5
Gear PLL N Div4
Bit 4
N Divider
Gear PLL N Div3
Bit 3
Gear PLL N Div2
Bit 2
Gear PLL N Div1
Bit 1
Gear PLL N Div0
Bit 0
SMBusTable: Reserved Register
Byte 13
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Gear PLL Out
Bit 3
Gear PLL Out
Bit 2
Gear PLL Out
Bit 1
Gear PLL Out
Bit 0
Div
Div
Div
Div
3
2
1
0
Control Function
RESERVED
RESERVED
RESERVED
RESERVED
Gear PLL Output Divider
Gear PLL Output Divider
Gear PLL Output Divider
Gear PLL Output Divider
0
1
PWD
Type
RW
X
RW
X
RW
X
RW See M/N Programming Section X
of the Data Sheet
RW
X
RW
X
RW
X
RW
X
Type
RW
RW
RW
RW
0
1
PWD
0
0
0
0
x
See Output Divider Ratios x
Table
x
x
SMBusTable: Reserved Register
Byte 14
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Type
0
1
PWD
0
0
0
0
0
0
0
0
SMBusTable: Reserved Register
Byte 15
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Type
0
1
PWD
0
0
0
0
0
0
0
0
1255B—08/03/07
18
Integrated
Circuit
Systems, Inc.
ICS9FG1904B-1
SMBusTable: Reserved Register
Byte 16
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Type
0
1
PWD
0
0
0
0
0
0
0
0
SMBus Table: 1:1 PLL
Pin #
Byte 17
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Frequency Control Register
Name
Control Function
Type
0
1
PWD
X
RESERVED
X
RESERVED
1:1 PLL M Div5
RW
X
1:1 PLL M Div4
RW
X
M
Divider
Programming
1:1 PLL M Div3
RW See M/N Programming Section X
of the Data Sheet
bits
1:1 PLL M Div2
RW
X
1:1 PLL M Div1
RW
X
1:1 PLL M Div0
RW
X
SMBus Table: 1:1 PLL
Byte 18
Pin #
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Frequency Control Register
0
1
PWD
Name
Control Function
Type
1:1 PLL N Div7
RW
X
1:1 PLL N Div6
RW
X
1:1 PLL N Div5
RW
X
See
M/N
Programming
Section
N
Divider
Programming
1:1 PLL N Div4
RW
X
of the Data Sheet
b(7:0)
1:1 PLL N Div3
RW
X
1:1 PLL N Div2
RW
X
1:1 PLL N Div1
RW
X
1:1 PLL N Div0
RW
X
SMBusTable: Reserved Register
Pin #
Name
Byte 19
Bit 7
Bit 6
Bit 5
Bit 4
1:1 PLL Out
Bit 3
1:1 PLL Out
Bit 2
1:1 PLL Out
Bit 1
1:1 PLL Out
Bit 0
Div
Div
Div
Div
3
2
1
0
Control Function
RESERVED
RESERVED
RESERVED
RESERVED
1:1 PLL Output Divider
1:1 PLL Output Divider
1:1 PLL Output Divider
1:1 PLL Output Divider
1255B—08/03/07
19
Type
RW
RW
RW
RW
0
1
PWD
0
0
0
0
x
See Output Divider Ratios x
Table
x
x
Integrated
Circuit
Systems, Inc.
SMBusTable: Reserved Register
Byte 20
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ICS9FG1904B-1
Control Function
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
SMBusTable: Test Byte Register
Byte 21
Test
Test Function
`
ICS ONLY TEST
Bit 7
ICS ONLY TEST
Bit 6
ICS ONLY TEST
Bit 5
ICS ONLY TEST
Bit 4
ICS ONLY TEST
Bit 3
ICS ONLY TEST
Bit 2
ICS ONLY TEST
Bit 1
ICS ONLY TEST
Bit 0
Note: Do NOT write to Bit 21. Erratic device operation will result!
1255B—08/03/07
20
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Test Result
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PWD
0
0
0
0
0
0
0
0
PWD
0
0
0
0
0
0
0
0
Integrated
Circuit
Systems, Inc.
ICS9FG1904B-1
(Ref. )
Seating Plane
(N D - 1)x e
(Ref. )
A1
Index Area
ND & NE
Even
A3
N
L
N
Anvil
Singulation
1
2
E2
OR
E
(Ref. )
b
(Ref.)
A
D
(N E - 1)x e
E2
2
Sawn
Singulation
Top View
e (Typ.)
2 If N D & N
E
are Even
1
e
D2
2
ND & NE
Odd
Thermal
Base
D2
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
C
0.08
C
THERMALLY ENHANCED, VERY THIN, FINE PITCH
QUAD FLAT / NO LEAD PLASTIC PACKAGE
DIMENSIONS
SYMBOL
A
A1
A3
b
e
DIMENSIONS
MIN.
MAX.
0.8
1.0
0
0.05
0.25 Reference
0.18
0.3
0.50 BASIC
SYMBOL
N
ND
NE
D x E BASIC
D2 MIN. / MAX.
E2 MIN. / MAX.
L MIN. / MAX.
ICS 72L
TOLERANCE
72
18
18
10.00 x 10.00
5.75 / 6.15
5.75 / 6.15
0.30/ 0.50
Ordering Information
ICS 9FG1904BK-1LFT
Example:
ICS XXXX B K - V LF T
Designation for tape and reel packaging
Lead Free, RoHS Compliant (Optional)
Variation Number
Package Type
K = MLF
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 to 7 digit numbers)
1255B—08/03/07
21
Integrated
Circuit
Systems, Inc.
ICS9FG1904B-1
Revision History
Rev.
A
B
Issue Date Description
1. Added Output Divider Table.
2. Added Phase Jitter Table to electrical characteristics.
05/04/07
3. Added M/N programming information.
4. Changed part number to reference 9FG1904B-1.
08/03/07 Release to Final.
1255B—08/03/07
22
Page #
Various
-