ICSSSTVA16859B Integrated Circuit Systems, Inc. DDR 13-Bit to 26-Bit Registered Buffer Q13A Q12A Q11A Q10A Q9A VDDQ GND Q8A Q7A Q6A Q5A Q4A Q3A Q2A GND Q1A Q13B VDDQ Q12B Q11B Q10B Q9B Q8B Q7B Q6B GND VDDQ Q5B Q4B Q3B Q2B Q1B Product Features: • Differential clock signals • Meets SSTL_2 signal data • Supports SSTL_2 class I specifications on outputs • Low-voltage operation - VDD = 2.3V to 2.7V • Available in 64 pin TSSOP and 56 pin MLF packages • Exceeds SSTVN16859 performance Truth Table1 Inputs Q Outputs RESET# CLK CLK# D Q L X or Floating X or Floating X or Floating L H ↑ ↓ H H H ↑ ↓ L L H L or H L or H X Q0(2) 2. Q8A VDDQ Q9A Q10A Q11A Q12A Q13A VDDQ GND D13 D12 VDD VDDQ D11 43 56 Output level before the indicated steady state input conditions were established. Block Diagram CLK CLK# D1 VREF R Q1A CLK D1 Q1B Q7A 1 Q6A Q5A Q4A Q3A Q2A Q1A Q13B VDDQ Q12B Q11B Q10B Q9B Q8B 14 42 D10 1050A—01/07/05 D9 D8 D7 RESET# GND CLK# CLK VDDQ VDD VREF D6 D5 29 D4 ICSSSTVA16859B 15 28 Q7B Q6B VDDQ Q5B Q4B Q3B Q2B Q1B VDDQ D1 D2 VDD VDDQ D3 To 12 Other Channels VDDQ GND D13 D12 VDD VDDQ GND D11 D10 D9 GND D8 D7 RESET# GND CLK# CLK VDDQ VDD VREF D6 GND D5 D4 D3 GND VDDQ VDD D2 D1 GND VDDQ 64-Pin TSSOP H = "High" Signal Level L = "Low" Signal Level ↑ = Transition "Low"-to-"High" ↓ = Transition "High"-to-"Low" X = Don't Care RESET# 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 6.10 mm. Body, 0.50 mm. pitch Notes: 1. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ICSSSTVA16859B Pin Configurations Recommended Applications: • DDR Memory Modules: - DDRI (PC1600, PC2100) - DDR333 (PC2700) - DDRI-400 (PC3200) • Provides complete DDR DIMM solution with ICS93V857 or ICS95V857 • SSTL_2 compatible data registers 56-Pin VFQFN (MLF2) ICSSSTVA16859B General Description The 13-bit-to-26-bit ICSSSTVA16859B is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/O levels, except for the LVCMOS RESET# input. Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#). The positive edge of CLK is used to trigger the data flow and CLK# is used to maintain sufficient noise margins where as RESET#, an LVCMOS asynchronous signal, is intended for use at the time of power-up only. ICSSSTVA16859B supports lowpower standby operation. A logic level “Low” at RESET# assures that all internal registers and outputs (Q) are reset to the logic “Low” state, and all input receivers, data (D) and clock (CLK/CLK#) are switched off. Please note that RESET# must always be supported with LVCMOS levels at a valid logic state because VREF may not be stable during power-up. To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESET# must be held at a logic “Low” level during power up. In the DDR DIMM application, RESET# is specified to be completely asynchronous with respect to CLK and CLK#. Therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power standby state, the register will be cleared and the outputs will be driven to a logic “Low” level quickly relative to the time to disable the differential input receivers. This ensures there are no glitches on the output. However, when coming out of low-power standby state, the register will become active quickly relative to the time to enable the differential input receivers. When the data inputs are at a logic level “Low” and the clock is stable during the “Low”-to-”High” transition of RESET# until the input receivers are fully enabled, the design ensures that the outputs will remain at a logic “Low” level. Pin Configuration (64-Pin TSSOP) PIN NUMBER PIN NAME TYPE 1-5, 8-14, 16, 17, 19-25, 28-32 Q (13:1) OUTPUT DESCRIPTION 7, 15, 26, 34, 39, 43, 50, 54, 58, 63 GND PWR Ground 6, 18, 27, 33, 38, 47, 59, 64 VDDQ PWR Output supply voltage, 2.5V nominal 35, 36, 40-42, 44, 52, 53, 5557, 61, 62 D (13:1) INPUT Data input Data output 48 CLK INPUT Positive master clock input 49 CLK# INPUT Negative master clock input Core supply voltage, 2.5V nominal 37, 46, 60 VDD PWR 51 RESET# INPUT Reset (active low) 45 VREF INPUT Input reference voltage, 2.5V nominal Pin Configuration (56-Pin MLF2) PIN NUMBER PIN NAME TYPE 1-8, 10-16, 18-22, 50-54, 56 Q (13:1) OUTPUT DESCRIPTION Data output 37, 48 GND PWR 9, 17, 23, 27, 34, 44, 49, 55 VDDQ PWR 24, 25, 28-31, 39-43, 46, 47 D (13:1) INPUT Data input 35 CLK INPUT Positive master clock input 36 CLK# INPUT Negative master clock input 1050A—01/07/05 Ground Output supply voltage, 2.5V nominal 26, 33, 45 VDD PWR 38 RESET# INPUT Reset (active low) Core supply voltage, 2.5V nominal 32 VREF INPUT Input reference voltage, 2.5V nominal - Center PAD PWR Ground (MLF2 package only) ICSSSTVA16859B Absolute Maximum Ratings Storage Temperature . . . . . . . . . . . . . . . . . . . . Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Voltage1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Clamp Current . . . . . . . . . . . . . . . . . . . . Output Clamp Current . . . . . . . . . . . . . . . . . . . Continuous Output Current . . . . . . . . . . . . . . . VDD, VDDQ or GND Current/Pin . . . . . . . . . . . –65°C to +150°C -0.5 to 3.6V -0.5 to VDD +0.5 -0.5 to VDDQ +0.5 ±50 mA ±50 mA ±50 mA ±100 mA Package Thermal Impedance 3 55°C/W ............... Notes: 1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. This current will flow only when the output is in the high state level V0 >VDDQ. 3. The package thermal impedance is calculated in accordance with JESD 51. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Recommended Operating Conditions - DDRI/DDR333 (PC1600, PC2100, PC2700) PARAMETER V DD V DDQ VREF VTT VI VIH (DC) VIH (AC) VIL (DC) VIL (DC) VIH VIL VICR VID VIX IOH IOL TA 1 DESCRIPTION Supply Voltage I/O Supply Voltage Reference Voltage Termination Voltage Input Voltage DC Input High Voltage AC Input High Voltage Data Inputs DC Input Low Voltage AC Input Low Voltage Input High Voltage Level RESET# Input Low Voltage Level Common mode Input Range CLK, CLK# Differential Input Voltage Cross Point Voltage of Differential Clock Pair High-Level Output Current Low-Level Output Current Operating Free-Air Temperature Guaranteed by design, not 100% tested in production. 1050A—01/07/05 MIN 2.3 2.3 1.15 VREF - 0.04 0 VREF + 0.15 VREF + 0.31 TYP 2.5 2.5 1.25 V REF MAX 2.7 2.7 1.35 V REF + 0.04 V DDQ UNITS VREF - 0.15 VREF - 0.31 V 1.7 0.97 0.36 0.7 1.53 (V DDQ/2) - 0.2 (VDDQ/2) + 0.2 0 -16 16 70 mA °C ICSSSTVA16859B Recommended Operating Conditions - DDRI-400 (PC3200) PARAMETER V DD V DDQ VREF VTT VI VIH (DC) VIH (AC) VIL (DC) VIL (DC) VIH VIL VICR VID VIX IOH IOL TA 1 DESCRIPTION Supply Voltage I/O Supply Voltage Reference Voltage Termination Voltage Input Voltage DC Input High Voltage AC Input High Voltage Data Inputs DC Input Low Voltage AC Input Low Voltage Input High Voltage Level RESET# Input Low Voltage Level Common mode Input Range CLK, CLK# Differential Input Voltage Cross Point Voltage of Differential Clock Pair High-Level Output Current Low-Level Output Current Operating Free-Air Temperature Guaranteed by design, not 100% tested in production. 1050A—01/07/05 MIN 2.5 2.5 1.25 VREF - 0.04 0 VREF + 0.15 VREF + 0.31 TYP 2.6 2.6 1.3 V REF MAX 2.7 2.7 1.35 V REF + 0.04 V DDQ UNITS VREF - 0.15 VREF - 0.31 V 1.7 0.97 0.36 0.7 1.53 (V DDQ/2) - 0.2 (VDDQ/2) + 0.2 0 -16 16 70 mA °C ICSSSTVA16859B DC Electrical Characteristics - DDRI/DDR333 (PC1600, PC2100, PC2700) TA = 0 - 70°C; VDD = 2.5 +/-0.2V, VDDQ=2.5 +/-0.2V; (unless otherwise stated) SYMBOL VIK VOL IDD All Inputs Standby (Static) Operating (Static) Dynamic operating (clock only) IDDD Dynamic Operating (per each data input) rOH rOL rO(D) Ci Output High Output Low [rOH - rOL] each separate bit Data Inputs CLK and CLK# IOH = -100µA 2.3V-2.7V IOH = -8mA IOL = 100µA IOL = 8mA VI = VDD or GND RESET# = GND VI = VIH(AC) or VIL(AC), RESET# = VDD VI RESET# = VDD, = VIH(AC) or VIL(AC), CLK and CLK# switching 50% duty cycle. 2.3V 2.3V-2.7V 2.3V 2.7V IO = 0 MIN IOH = -16mA IOL = 16mA TYP MAX -1.2 VDDQ 0.2 1.95 UNITS V 0.2 0.35 ±5 0.01 µA µA TBD mA TBD µ/clock MHz TBD µA/ clock MHz/data 2.7V RESET# = VDD, VI = VIH(AC) or VIL (AC), CLK and CLK# switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle 2.3V-2.7V 2.3V-2.7V IO = 20mA, TA = 25° C 2.5V VI = VREF ±350mV VICR = 1.25V, VI(PP) = 360mV 2.5V Notes: 1 - Guaranteed by design, not 100% tested in production. 1050A—01/07/05 VDDQ 2.3V II = -18mA VOH II CONDITIONS PARAMETERS 7 7 2.5 2.5 13.5 13 20 20 Ω Ω 4 Ω 3.5 3.5 pF ICSSSTVA16859B DC Electrical Characteristics - DDRI-400 (PC3200) TA = 0 - 70°C; VDD = 2.5 +/-0.2V, VDDQ=2.5 +/-0.2V; (unless otherwise stated) SYMBOL VIK VOL IDD All Inputs Standby (Static) Operating (Static) Dynamic operating (clock only) IDDD Dynamic Operating (per each data input) rOH rOL rO(D) Ci Output High Output Low [rOH - rOL] each separate bit Data Inputs CLK and CLK# IOH = -100µA 2.5V-2.7V IOH = -8mA IOL = 100µA IOL = 8mA VI = VDD or GND RESET# = GND VI = VIH(AC) or VIL(AC), RESET# = VDD VI RESET# = VDD, = VIH(AC) or VIL(AC), CLK and CLK# switching 50% duty cycle. 2.7V 2.5V-2.7V 2.5V 2.7V IO = 0 MIN IOH = -16mA IOL = 16mA TYP MAX -1.2 VDDQ 0.2 1.95 UNITS V 0.2 0.35 ±5 0.01 µA µA TBD mA TBD µ/clock MHz TBD µA/ clock MHz/data 2.7V VI RESET# = VDD, = VIH(AC) or VIL (AC), CLK and CLK# switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle 2.5V-2.7V 2.5V-2.7V IO = 20mA, TA = 25° C 2.6V VI = VREF ±350mV VICR = 1.25V, VI(PP) = 360mV 2.6V Notes: 1 - Guaranteed by design, not 100% tested in production. 1050A—01/07/05 VDDQ 2.5V II = -18mA VOH II CONDITIONS PARAMETERS 7 7 2.5 2.5 13.5 13 20 20 Ω Ω 4 Ω 3.5 3.5 pF ICSSSTVA16859B Timing Requirements1 (over recommended operating free-air temperature range, unless otherwise noted) VDDQ = 2.5V ± 0.2V PARAMETERS SYMBOL MIN MAX Clock frequency 270 fclock Output slew rate 1 4 tSL 0.4 Setup time, fast slew rate 2 & 4 Data before CLK↑ , CLK#↓ tS 0.6 Setup time, slow slew rate 3 & 4 2&4 0.4 Hold time, fast slew rate Th Data after CLK↑ , CLK#↓ 0.5 Hold time, slow slew rate 3 & 4 1 - Guaranteed by design, not 100% tested in production. Notes: 2 - For data signal input slew rate of ≥ 1V/ns. 3 - For data signal input slew rate of ≥ 0.5V/ns and < 1V/ns. 4 - CLK, CLK# signals input slew rate of ≥ 1V/ns. UNITS Switching Characteristics - DDRI/DDR333 (PC1600, PC2100, PC2700) (over recommended operating free-air temperature range, unless otherwise noted) (see Figure 1) V DD = 2.5V ±0.2V From To SYMBOL UNITS (Input) (Output) MIN TYP MAX 210 MHz fmax CLK, CLK# (TSSOP) Q 1.6 2.1 2.6 ns tPD CLK, CLK# (VFQFN[MLF2]) Q 1.6 2.1 2.6 ns RESET# Q 3.5 ns tphl Switching Characteristics - DDRI-400 (PC3200) (over recommended operating free-air temperature range, unless otherwise noted) (see Figure 1) VDD = 2.6V ±0.1V From To SYMBOL UNITS (Input) (Output) MIN TYP MAX f max 210 MHz Q 1.1 1.65 ns t PD (VFQFN[MLF2]) Q 1.9 ns t PDSS CLK, CLK# (TSSOP) Q 1.1 1.6 1.85 ns t PD RESET# Q 3.5 ns t phl 1050A—01/07/05 MHz V/ns ns ns ns ns ICSSSTVA16859B VDD 1kΩ From Output Under Test Test point CL = 30 pF (see Note 1) 1kΩ Load Circuit LVCMOS RESET# Input VDDQ VDDQ/2 VDDQ/2 tinact VI(pp) 0V tact IDD (see note 2) 90% IDDH 10% Timing Input tPHL IDDL Voltage and Current Waveforms Inputs Active and Inactive Times VICR VICR tPHL VTT VTT VOH VOL Output Voltage Waveforms - Propagation Delay Times tw VIH VREF Input VREF VIL Voltage Waveforms - Pulse Duration VI(pp) Timing Input VIH VDD/2 VIL VICR tPHL tS Input LVCMOS RESET# Input VREF VOH Output th VTT VOL VIH VREF VIL Voltage Waveforms - Propagation Delay Times Voltage Waveforms - Setup and Hold Times Figure 1 - Parameter Measurement Information (VDDQ = 2.5V ±0.2V) Notes: 1. CL incluces probe and jig capacitance. 2. IDD tested with clock and data inputs held at VDDQ or GND, and IO = 0 mA. 3. All input pulses are supplied by generators having the following characteristics: PRR @10 MHz, Zo=50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. VTT = VREF = VDDQ/2 6. VIH = VREF + 310mV (AC voltage levels) for differential inputs. VIH = VDDQ for LVCMOS input. 7. VIL = VREF - 310mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. 8. tPLH and tPHL are the same as tpd 1050A—01/07/05 ICSSSTVA16859B c N L E1 INDEX AREA E 1 2 a D A A2 A1 -Ce SEATING PLANE b aaa C In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 8.10 BASIC 0.319 BASIC E E1 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N 0° 8° 0° 8° α aaa -0.10 -.004 VARIATIONS N 64 D mm. MIN MAX 16.90 17.10 Ref erence Doc.: JEDEC Publication 95, M O-153 10-0039 6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil) (240 mil) Ordering Information ICSSSTVA16859BG(LF)-T Example: ICS XXXX y G (LF) - T Designation for tape and reel packaging Lead Free (optional) Package Type G = TSSOP Revision Designator Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 1050A—01/07/05 D (inch) MIN .665 MAX .673 ICSSSTVA16859B Symbol Common Dime ns ions A - 0.85 1.00 A1 0.00 0.01 0.05 A2 - 0.65 0.80 A3 56 pin MLF2 0.20 BSC D 8.00 BSC D1 7.75 BSC E 8.00 BSC E1 7.75 BSC Θ 12 P 0.24 0.42 0.60 R 0 . 13 0.17 0.23 Pitch Varation D e 0.50 BSC N 56 Nd 14 Ne Ordering Information ICSSSTVA16859BK(LF)-T Example: 0.30 0.40 0.50 b 0 . 18 0.23 0.30 Q 0.00 0.20 0.45 D2 4.35 4.50 4.65 E2 5.05 5.20 5.35 ICS XXXX y K ( LF) - T Designation for tape and reel packaging Lead Free (optional) Package Type K = MLF Revision Designator Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 1050A—01/07/05 14 L WWW.ALLDATASHEET.COM Copyright © Each Manufacturing Company. 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