SONY ICX274

ICX274AQF
Diagonal 8.923mm (Type 1/1.8) Progressive Scan CCD Image Sensor with Square Pixel for Color Cameras
Description
The ICX274AQF is a diagonal 8.923mm (Type 1/1.8)
interline CCD solid-state image sensor with a square
pixel array and 2.01M effective pixels. Progressive
scan allows all pixels' signals to be output
independently within approximately 1/15 second,
and output is also possible using various addition
and pulse elimination methods. This chip features an
electronic shutter with variable charge-storage time
which makes it possible to realize full-frame still
images without a mechanical shutter. High resolution
and high color reproductivity are achieved through
the use of R, G, B primary color mosaic filters as the
color filters. Further, high sensitivity and low dark
current are achieved through the adoption of Super
HAD CCD technology.
This chip is suitable for applications such as
electronic still cameras, PC input cameras, etc.
Features
• High horizontal and vertical resolution
• Supports the following modes
Progressive scan mode (with/without mechanical shutter)
2/8-line readout mode
2/4-line readout mode
2-line addition mode
Center scan modes (1), (2) and (3)
AF modes (1) and (2)
• Square pixel
• Horizontal drive frequency: 28.6364MHz (typ.), 36.0MHz (max.)
• Reset gate bias are not adjusted
• R, G, B primary color mosaic filters on chip
• High sensitivity, low dark current
• Continuous variable-speed shutter function
• Excellent anti-blooming characteristics
• 20-pin high-precision plastic package
20 pin SOP (Plastic)
Pin 1
2
V
10
12
Pin 11
H
48
Optical black position
(Top View)
Device Structure
• Interline CCD image sensor
• Image size:
Diagonal 8.923mm (Type 1/1.8)
• Total number of pixels:
1688 (H) × 1248 (V) approx. 2.11M pixels
• Number of effective pixels: 1628 (H) × 1236 (V) approx. 2.01M pixels
• Number of active pixels:
1620 (H) × 1220 (V) approx. 1.98M pixels
• Recommended number of
recording pixels:
1600 (H) × 1200 (V) approx. 1.92M pixels
• Chip size:
8.50mm (H) × 6.80mm (V)
• Unit cell size:
4.40µm (H) × 4.40µm (V)
• Optical black:
Horizontal (H) direction: Front 12 pixels, rear 48 pixels
Vertical (V) direction:
Front 10 pixels, rear 2 pixels
• Number of dummy bits:
Horizontal 28
Vertical 1
• Substrate material:
Silicon
∗ Wfine CCD is trademark of Sony corporation.
Represents a CCD adopting progressive scan, primary color filter and square pixel.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E02262
ICX274AQF
GND
Vφ1
Vφ2C
Vφ2B
Vφ2A
Vφ3C
Vφ3B
Vφ3A
Vφ4
10
9
8
7
6
5
4
3
2
1
Vertical register
VOUT
Block Diagram and Pin Configuration
(Top View)
G
B
G
B
R
G
R
G
G
B
G
B
R
G
R
G
G
B
G
B
R
G
R
G
G
B
G
B
R
G
R
G
Note)
Horizontal register
17
φSUB
CSUB
18
19
: Photo sensor
20
Hφ2A
16
Hφ1A
15
VL
14
GND
φRG
13
Hφ1B
12
Hφ2B
11
VDD
Note)
Pin Description
Pin No.
Symbol
Description
Pin No.
Symbol
Description
1
Vφ4
Vertical register transfer clock
11
VDD
Supply voltage
2
Vφ3A
Vertical register transfer clock
12
φRG
Reset gate clock
3
Vφ3B
Vertical register transfer clock
13
Hφ2B
Horizontal register transfer clock
4
Vφ3C
Vertical register transfer clock
14
Hφ1B
Horizontal register transfer clock
5
Vφ2A
Vertical register transfer clock
15
GND
GND
6
Vφ2B
Vertical register transfer clock
16
φSUB
7
Vφ2C
Vertical register transfer clock
17
CSUB
Substrate clock
Substrate bias∗1
8
Vφ1
Vertical register transfer clock
18
VL
Protective transistor bias
9
GND
GND
19
Hφ1A
Horizontal register transfer clock
10
VOUT
Signal output
20
Hφ2A
Horizontal register transfer clock
∗1 DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance of
0.1µF.
–2–
ICX274AQF
Absolute Maximum Ratings
Item
Ratings
Unit
VDD, VOUT, φRG – φSUB
–40 to +12
V
Vφ2α, Vφ3α – φSUB (α = A to C)
–50 to +15
V
Vφ1, Vφ4, VL – φSUB
–50 to +0.3
V
Hφ1β, Hφ2β, GND – φSUB (β = A, B)
–40 to +0.3
V
CSUB – φSUB
–25 to
V
VDD, VOUT, φRG, CSUB – GND
–0.3 to +22
V
Vφ1, Vφ2α, Vφ3α, Vφ4 – GND (α = A to C)
–10 to +18
V
Hφ1β, Hφ2β – GND (β = A, B)
–10 to +6.5
V
Vφ2α, Vφ3α – VL (α = A to C)
–0.3 to +28
V
Vφ1, Vφ4, Hφ1β, Hφ2β, GND – VL (β = A, B)
–0.3 to +15
V
to +15
V
Hφ1β – Hφ2β (β = A, B)
–6.5 to +6.5
V
Hφ1β, Hφ2β – Vφ4 (β = A, B)
–10 to +16
V
Storage temperature
–30 to +80
°C
Guaranteed temperature of performance
–10 to +60
°C
Operating temperature
–10 to +75
°C
Against φSUB
Against GND
Against VL
Voltage difference between vertical clock input pins
Between input
clock pins
∗2 +24V (Max.) is guaranteed when clock width < 10µs, clock duty factor < 0.1%.
+16V (Max.) is guaranteed during power-on or power-off.
–3–
Remarks
∗2
ICX274AQF
Bias Conditions
Item
Symbol
Supply voltage
VDD
Protective transistor bias
VL
∗1
Substrate voltage No line addition
adjustment range 2-line addition∗2
Min.
Typ.
Max.
14.55
15.0
∗3
15.45
VSUB
Unit Remarks
V
Internally generated value
VSUB2
8.8
Substrate voltage adjustment accuracy
∆VSUB
Indicated
voltage – 0.2
Reset gate clock
φRG
Indicated
voltage
∗5
∗4
14.4
V
Indicated
voltage + 0.2
V
V
∗1 Progressive scan mode, 2/8-line readout mode, 2/4-line readout mode, center scan modes (1) and (3),
and AF modes (1) and (2)
∗2 2-line addition mode and center scan mode (2)
∗3 VL setting is the VVL voltage of the vertical clock waveform, or the same voltage as the VL power supply
for the V driver should be used.
4
∗ Substrate voltage (VSUB2) setting value indication
The substrate voltage (VSUB) for modes without line addition is generated internally.
The substrate voltage setting value for use with vertical 2-line addition is indicated by a code on the
bottom surface of the image sensor. Adjust the substrate voltage to the indicated voltage.
VSUB2 code – 1-digit indication
↑
VSUB2 code
The code and the actual value correspond as follows.
VSUB2 code
1
2
3
4
6
7
8
Actual value
8.8
9.0
9.2
9.4
9.6
9.8
VSUB2 code
J
K
L
m
N
P
9
A
C
d
E
f
G
h
10.0 10.2 10.4 10.6 10.8 11.0 11.2 11.4 11.6
R
S
U
V
W
X
Y
Z
Actual value 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2 13.4 13.6 13.8 14.0 14.2 14.4
[Example] "h" indicates a VSUB2 setting of 11.6V.
∗5 Do not apply a DC bias to the reset gate clock pin, because a DC bias is generated within the CCD.
DC characteristics
Item
Supply current
Symbol
Min.
Typ.
Max.
Unit
IDD
7.0
10.0
13.0
mA
–4–
Remarks
ICX274AQF
Clock Voltage Conditions
Item
Readout clock
voltage
Vertical transfer
clock voltage
Horizontal transfer
clock voltage
Reset gate clock
voltage
Substrate clock
voltage
Min.
Typ.
Max.
Unit
Waveform
diagram
VVT
14.55
15.0
15.45
V
1
VVH1, VVH2
–0.05
0
0.05
V
2
VVH3, VVH4
–0.2
0
0.05
V
2
VVL1, VVL2,
VVL3, VVL4
–8.0
–7.5
–7.0
V
2
VVL = (VVL3 + VVL4)/2
VφV
6.8
7.5
8.05
V
2
VφV = VVHn – VVLn (n = 1 to 4)
Symbol
Remarks
VVH = (VVH1 + VVH2)/2
VVH3 – VVH
–0.25
0.1
V
2
VVH4 – VVH
–0.25
0.1
V
2
VVHH
0.5
V
2
High-level coupling
VVHL
0.5
V
2
High-level coupling
VVLH
0.5
V
2
Low-level coupling
VVLL
0.5
V
2
Low-level coupling
VφH
4.75
5.0
5.25
V
3
VHL
–0.05
0
0.05
V
3
VCR
0.8
2.5
V
3
VφRG
3.0
3.3
5.25
V
4
VRGLH – VRGLL
0.4
V
4
Low-level coupling
VRGL – VRGLm
0.5
V
4
Low-level coupling
23.5
V
5
VφSUB
21.5
22.5
–5–
Cross-point voltage
ICX274AQF
Clock Equivalent Circuit Constants
Item
Symbol
Min.
Typ.
Max. Unit Remarks
CφV1
3300
pF
CφV2A, CφV2B
1200
pF
CφV2C
2700
pF
CφV3A, CφV3B
1000
pF
CφV3C
1800
pF
CφV4
6800
pF
CφV12 (A, B)
120
pF
CφV12C
220
pF
CφV13 (A, B)
150
pF
CφV13C
270
pF
CφV14
2700
pF
CφV2 (A, B), 3 (A, B)
470
pF
CφV2 (A, B), 3C
680
pF
CφV2 (A, B), 4
680
pF
CφV2C, 3 (A, B)
1000
pF
CφV2C, 3C
820
pF
CφV2C, 4
1800
pF
CφV3 (A, B), 4
820
pF
CφV3C, 4
1500
pF
Capacitance between horizontal transfer clock
and GND
CφH1
100
pF
CφH2
100
pF
Capacitance between horizontal transfer clocks
CφHH
47
pF
Capacitance between reset gate clock and GND
CφRG
2
pF
Capacitance between substrate clock and GND
CφSUB
820
pF
R1, R4
30
Ω
R2 (A, B, C), 3 (A, B, C)
62
Ω
Vertical transfer clock ground resistor
RGND
15
Ω
Horizontal transfer clock series resistor
RφH
7
Ω
Horizontal transfer clock ground resistor
RφH2
20
kΩ
Reset gate clock and series resistor
RφRG
4.7
Ω
Capacitance between vertical transfer clock and
GND
Capacitance between vertical transfer clocks
Vertical transfer clock series resistor
Note 1) Expressions using parentheses such as CφV2 (A,B), 3C indicate items which include all combinations of
the pins within the parentheses.
For example, CφV2 (A, B), 3C indicates [CφV2A3C, CφV2B3C].
–6–
ICX274AQF
Vφ1
RφH
RφH
Hφ1A
Hφ2A
R1
CφV1
RφH
RφH
Hφ1B
Hφ2B
CφHH
CφV14
CφV2α4 (α = A to C)
CφV12α (α = A to C)
CφH2
CφH1
Vφ4
R4
Vφ2α (α = A to C)
R2α (α = A to C)
RGND
CφV4
RφH2
CφV2α (α = A to C)
Horizontal transfer clock equivalent circuit
CφV2α3α (α = A to C)
CφV3α4 (α = A to C)
CφV13α (α = A to C)
CφV3α (α = A to C)
R3α (α = A to C)
RφRG
RGφ
Vφ3α (α = A to C)
Note 2) Cφ2α2β and Cφ3α3β (α = A to C, β = A to C other than α) are
sufficiently small relative to other capacitance between
other vertical clocks in the equivalent circuit, so these
are omitted from the equivalent circuit diagram.
Vertical transfer clock equivalent circuit
CφRG
Reset gate clock equivalent circuit
–7–
ICX274AQF
Drive Clock Waveform Conditions
(1) Readout clock waveform
100%
90%
φM
VVT
φM
2
10%
0%
tr
twh
0V
tf
(2) Vertical transfer clock waveform
Vφ1
Vφ3A, Vφ3B, Vφ3C
VVH1
VVHH
VVH
VVHL
VVHL
VVH3
VVHL
VVL1
VVHH
VVHH
VVHH
VVH
VVHL
VVL3
VVLH
VVLH
VVLL
VVLL
VVL
VVL
Vφ2A, Vφ2B , Vφ2C
VVHH
Vφ4
VVHH
VVH
VVH
VVHH
VVHH
VVHL
VVHL
VVH2 VVHL
VVH4
VVLH
VVL2VVLH
VVLL
VVLL
VVL
VVH = (VVH1 + VVH2)/2
VVL = (VVL3 + VVL4)/2
VφV = VVHn – VVLn (n = 1 to 4)
VVHL
VVL4
–8–
VVL
ICX274AQF
(3) Horizontal transfer clock waveform
tr
tf
twh
Hφ2β
90%
VCR
VφH
twl
VφH
2
10%
Hφ1β
VHL
two
Cross-point voltage for the Hφ1β rising side of the horizontal transfer clocks Hφ1β and Hφ2β waveforms is VCR.
The overlap period for twh and twl of horizontal transfer clocks Hφ1β and Hφ2β is two. (β = A, B)
(4) Reset gate clock waveform
tr
twh
tf
VRGH
RG waveform
twl
VφRG
Point A
VRGLH
VRGL
VRGLL
VRGLm
VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from
Point A in the above diagram until the rising edge of RG.
In addition, VRGL is the average value of VRGLH and VRGLL.
VRGL = (VRGLH + VRGLL)/2
Assuming VRGH is the minimum value during the interval twh, then:
VφRG = VRGH – VRGL
Negative overshoot level during the falling edge of RG is VRGLm.
(5) Substrate clock waveform
100%
90%
φM
VφSUB
10%
VSUB
0%
(Internally generated bias)
tr
twh
–9–
φM
2
tf
ICX274AQF
Clock Switching Characteristics (Horizontal drive frequency: 28.6364MHz)
Item
Symbol
Readout clock
VT
Vertical transfer
clock
Vφ1, Vφ4,
Vφ2α, Vφ3α
(α = A to C)
Horizontal
transfer clock
Item
Horizontal
transfer clock
twl
tr
tf
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
3.3 3.5
0.5
15
∗2
7.5
5
7.5
Hφ2β (β = A, B) 10 12.5
10 12.5
5
7.5
5
7.5
φSUB
Symbol
Hφ1A, Hφ1B,
Hφ2A, Hφ2B
24
2
2.1
two
Min. Typ. Max.
8
10
ns
ns
3
During drain
0.5 µs
charge
0.5
Unit
During
readout
∗1
5
7
Remarks
400 ns
10 12.5
4
Unit
µs
0.5
Hφ1β (β = A, B) 10 12.5
Reset gate clock φRG
Substrate clock
twh
Remarks
ns
Clock Switching Characteristics (Horizontal drive frequency: 36MHz)
Item
Symbol
Readout clock
VT
Vertical transfer
clock
Vφ1, Vφ4,
Vφ2α, Vφ3α
(α = A to C)
Horizontal
transfer clock
Item
Horizontal
transfer clock
twl
tr
tf
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
4.0 4.2
0.5
0.5
15
400 ns
9
8
9
5
6
5
6
Hφ2β (β = A, B) 8
9
8
9
5
6
5
6
8
2
4
φSUB
Symbol
Hφ1A, Hφ1B,
Hφ2A, Hφ2B
5.5
1.67
two
Min. Typ. Max.
8
9
3
0.25
Unit
Unit
µs
Hφ1β (β = A, B) 8
Reset gate clock φRG
Substrate clock
twh
ns
Remarks
During
readout
∗1
∗2
ns
During drain
0.25 µs
charge
Remarks
ns
∗1 When two vertical transfer clock drivers CXD3400N are used.
∗2 tf ≥ tr – 2ns, and the cross-point voltage (VCR) for the Hφ1β (β = A, B) rising side of the Hφ1β and Hφ2β
waveforms must be VφH/2 [V] or more.
– 10 –
ICX274AQF
Spectral Sensitivity Characteristics (excludes lens characteristics and light source characteristics)
1.0
B
G
R
Relative Response
0.8
0.6
0.4
0.2
0
400
450
500
550
Wave Length [nm]
– 11 –
600
650
700
ICX274AQF
Image Sensor Characteristics
Symbol
Min.
Typ.
Max.
Unit
Measurement
method
Sg
335
420
545
mV
1
R
Rr
0.35
0.5
0.65
1
B
Rb
0.45
0.6
0.75
1
Vsat
400
Vsat2∗1
400
Item
G Sensitivity
Sensitivity
comparison
(Ta = 25°C)
Saturation signal
Smear
Video signal shading
Sm
SH
mV
–100
–92
–94
–86
–88
–80
20
dB
Remarks
1/30s accumulation
No line addition∗2
2-line addition∗3
2
Ta = 60°C
3
Progressive scan mode∗4
2/4-line readout mode∗5
2/8-line readout mode∗6
%
4
%
5
25
Zone 0 and I
Zone 0 to II’
∆Srg
Uniformity between
video signal channels ∆Sbg
8
Dark signal
Vdt
8
mV
6
Ta = 60°C, 14.985 frame/s
Dark signal shading
∆Vdt
2
mV
7
Ta = 60°C, 14.985 frame/s, ∗7
Line crawl G
Lcg
3.8
%
8
Line crawl R
Lcr
3.8
%
8
Line crawl B
Lcb
3.8
%
8
Lag
Lag
0.5
%
9
8
∗1 Vsat2 is the saturation signal level in 2-line addition mode, and is 200mV per pixel.
∗2 Progressive scan mode, 2/8-line readout mode, 2/4-line readout mode, and center scan modes (1) and (3).
∗3 2-line addition mode and center scan mode (2).
∗4 Same for 2-line addition mode and center scan modes (2) and (3).
∗5 Same for center scan mode (1).
∗6 Same for AF modes (1) and (2).
∗7 Excludes vertical dark signal shading caused by vertical register high-speed transfer.
– 12 –
ICX274AQF
Zone Definition of Video Signal Shading
1628 (H)
4
4
8
V
10
H
8
H
8
Zone 0, I
1236 (V)
8
Zone II, II’
Ignored region
Effective pixel region
V
10
Measurement System
CCD signal output [∗A]
CCD
C.D.S
AMP
S/H
Gr/Gb channel signal output [∗B]
S/H
R/B channel signal output [∗C]
Note) Adjust the amplifier gain so that the gain between [∗A] and [∗B], and between [∗A] and [∗C] equals 1.
Image Sensor Characteristics Measurement Method
Color coding of this image sensor & Readout
Gb
B
Gb
B
R
Gr
R
Gr
Gb
B
Gb
B
R
Gr
R
Gr
The primary color filters of this image sensor are arranged in the layout
shown in the figure on the left (Bayer arrangement).
Gr and Gb denote the G signals on the same line as the R signal and the
B signal, respectively.
Horizontal register
Color Coding Diagram
– 13 –
ICX274AQF
Readout modes
The diagrams below and on the following pages show the output methods for the following nine readout
modes.
Progressive scan mode
2/8-line readout mode
2/4-line readout mode
16 (V2C/V3C)
G
B
16 (V2C/V3C)
G
B
16 (V2C/V3C)
G
B
15 (V2C/V3C)
R
G
15 (V2C/V3C)
R
G
15 (V2C/V3C)
R
G
14 (V2A/V3A)
G
B
14 (V2A/V3A)
G
B
14 (V2A/V3A)
G
B
13 (V2B/V3B)
R
G
13 (V2B/V3B)
R
G
13 (V2B/V3B)
R
G
12 (V2C/V3C)
G
B
12 (V2C/V3C)
G
B
12 (V2C/V3C)
G
B
11 (V2C/V3C)
R
G
11 (V2C/V3C)
R
G
11 (V2C/V3C)
R
G
10 (V2B/V3B)
G
B
10 (V2B/V3B)
G
B
10 (V2B/V3B)
G
B
R
G
9 (V2A/V3A)
R
G
G
B
8 (V2C/V3C)
G
B
9 (V2A/V3A)
R
G
9 (V2A/V3A)
8 (V2C/V3C)
G
B
8 (V2C/V3C)
7 (V2C/V3C)
R
G
7 (V2C/V3C)
R
G
7 (V2C/V3C)
R
G
6 (V2A/V3A)
G
B
6 (V2A/V3A)
G
B
6 (V2A/V3A)
G
B
5 (V2B/V3B)
R
G
5 (V2B/V3B)
R
G
5 (V2B/V3B)
R
G
4 (V2C/V3C)
G
B
4 (V2C/V3C)
G
B
4 (V2C/V3C)
G
B
3 (V2C/V3C)
R
G
3 (V2C/V3C)
R
G
3 (V2C/V3C)
R
G
2 (V2B/V3B)
G
B
2 (V2B/V3B)
G
B
2 (V2B/V3B)
G
B
1 (V2A/V3A)
R
G
1 (V2A/V3A)
R
G
1 (V2A/V3A)
R
G
VOUT
VOUT
VOUT
Note) Blacked out portions in the diagram indicate pixels which are not read out.
Output starts from line 1 in 2/8-line decimation mode.
1. Progressive scan mode
In this mode, all pixel signals are output in non-interlace format in 1/14.985s.
All pixel signals within the same exposure period are read out simultaneously, making this mode suitable
for high resolution image capturing.
2. 2/8-line readout mode
All effective area signals are output in approximately 1/30s by reading out the signals for only two out of
eight lines (1st and 6th lines, 9th and 14th lines).
This readout mode emphasizes processing speed over vertical resolution, making it suitable for AE/AF and
other control and for checking images on LCD viewfinders.
3. 2/4-line readout mode
All effective area signals are output in approximately 1/20s by reading out the signals for only two out of
four lines (3rd and 4th lines, 7th and 8th lines, and so on).
– 14 –
ICX274AQF
2-line addition mode
Center scan mode (1)
Center scan mode (2)
16 (V2C/V3C)
G
B
16 (V2C/V3C)
G
B
16 (V2C/V3C)
G
B
15 (V2C/V3C)
R
G
15 (V2C/V3C)
R
G
15 (V2C/V3C)
R
G
14 (V2A/V3A)
G
B
14 (V2A/V3A)
G
B
14 (V2A/V3A)
G
B
13 (V2B/V3B)
R
G
13 (V2B/V3B)
R
G
13 (V2B/V3B)
R
G
12 (V2C/V3C)
G
B
12 (V2C/V3C)
G
B
12 (V2C/V3C)
G
B
11 (V2C/V3C)
R
G
11 (V2C/V3C)
R
G
11 (V2C/V3C)
R
G
10 (V2B/V3B)
G
B
10 (V2B/V3B)
G
B
10 (V2B/V3B)
G
B
9 (V2A/V3A)
R
G
9 (V2A/V3A)
R
G
9 (V2A/V3A)
R
G
8 (V2C/V3C)
G
B
8 (V2C/V3C)
G
B
8 (V2C/V3C)
G
B
7 (V2C/V3C)
R
G
7 (V2C/V3C)
R
G
7 (V2C/V3C)
R
G
6 (V2A/V3A)
G
B
6 (V2A/V3A)
G
B
6 (V2A/V3A)
G
B
5 (V2B/V3B)
R
G
5 (V2B/V3B)
R
G
5 (V2B/V3B)
R
G
4 (V2C/V3C)
G
B
4 (V2C/V3C)
G
B
4 (V2C/V3C)
G
B
3 (V2C/V3C)
R
G
3 (V2C/V3C)
R
G
3 (V2C/V3C)
R
G
2 (V2B/V3B)
G
B
2 (V2B/V3B)
G
B
2 (V2B/V3B)
G
B
1 (V2A/V3A)
R
G
1 (V2A/V3A)
R
G
1 (V2A/V3A)
R
G
VOUT
VOUT
VOUT
Note) Blacked out portions in the diagram indicate pixels which are not read out.
After reading out the pixels indicated by
and transferring two lines, the pixels indicated by
are read out and two pixels of the same color are added by the vertical transfer block.
4. 2-line addition mode
In this mode, the signals for only two out of four lines (3rd and 4th lines, 7th and 8th lines, and so on) are
read out, the vertical register is shifted by 2 bits, and then the signals of the remaining two out of the four
lines (1st and 2nd lines, 5th and 6th lines, and so on) are read out and added within the vertical register. All
effective area signals are output in approximately 1/20s.
5. Center scan mode (1)
In this mode, the signals for only two out of four lines (3rd and 4th lines, 7th and 8th lines, and so on) are
read out. The undesired portions are swept by vertical register high-speed transfer, and the vertical
1136-pixel region in the center of the picture is output by the above readout method. The number of
output lines is 568 lines at 36MHz, and 434 lines at 28.6364MHz. The frame rate is increased
(approximately 30 frames/s) by setting the number of output lines to that of VGA mode, making this
mode suitable for VGA moving pictures. (However, the angle of view decreases.)
6. Center scan mode (2)
In this mode, the signals for only two out of four lines (3rd and 4th lines, 7th and 8th lines, and so on) are
read out, the vertical register is shifted by 2 bits, and then the signals of the remaining two out of the four
lines (1st and 2nd lines, 5th and 6th lines, and so on) are read out and added within the vertical register.
The undesired portions are swept by vertical register high-speed transfer, and the vertical 1136-pixel region
in the center of the picture is output by the above readout method. The number of output lines is 568 lines
at 36MHz, and 434 lines at 28.6364MHz. The frame rate is increased (approximately 30 frames/s) by
setting the number of output lines to that of VGA mode, making this mode suitable for VGA moving pictures.
(However, the angle of view decreases.)
– 15 –
ICX274AQF
Center scan mode (3)
16 (V2C/V3C)
G
AF mode (1)
B
16 (V2C/V3C)
G
AF mode (2)
B
16 (V2C/V3C)
G
B
R
G
G
B
15 (V2C/V3C)
R
G
15 (V2C/V3C)
R
G
15 (V2C/V3C)
14 (V2A/V3A)
G
B
14 (V2A/V3A)
G
B
14 (V2A/V3A)
13 (V2B/V3B)
R
G
13 (V2B/V3B)
R
G
13 (V2B/V3B)
R
G
12 (V2C/V3C)
G
B
12 (V2C/V3C)
G
B
12 (V2C/V3C)
G
B
11 (V2C/V3C)
R
G
11 (V2C/V3C)
R
G
11 (V2C/V3C)
R
G
10 (V2B/V3B)
G
B
10 (V2B/V3B)
G
B
10 (V2B/V3B)
G
B
9 (V2A/V3A)
R
G
9 (V2A/V3A)
R
G
9 (V2A/V3A)
R
G
G
B
8 (V2C/V3C)
G
B
R
G
7 (V2C/V3C)
R
G
G
B
G
8 (V2C/V3C)
G
B
8 (V2C/V3C)
7 (V2C/V3C)
R
G
7 (V2C/V3C)
6 (V2A/V3A)
G
B
6 (V2A/V3A)
G
B
6 (V2A/V3A)
5 (V2B/V3B)
R
G
5 (V2B/V3B)
R
G
5 (V2B/V3B)
R
4 (V2C/V3C)
G
B
4 (V2C/V3C)
G
B
4 (V2C/V3C)
G
B
3 (V2C/V3C)
R
G
3 (V2C/V3C)
R
G
3 (V2C/V3C)
R
G
2 (V2B/V3B)
G
B
2 (V2B/V3B)
G
B
2 (V2B/V3B)
G
B
1 (V2A/V3A)
R
G
1 (V2A/V3A)
R
G
1 (V2A/V3A)
R
G
VOUT
VOUT
VOUT
Note) Blacked out portions in the diagram indicate pixels which are not read out.
7. Center scan mode (3)
This is the center scan mode using the progressive scan method.
The undesired portions are swept by vertical register high-speed transfer, and the picture center is cut out.
The number of output lines is 580 lines at 36MHz, and 444 lines at 28.6364MHz.
8. AF mode (1)
In this mode, the undesired portions are swept by vertical register high-speed transfer, and the vertical
940-pixel region in the center of the picture is output in approximately 1/60s by reading out the signals for
only two out of eight lines (1st and 6th lines, 9th and 14th lines). The number of output lines is 235 lines at
36MHz, and 170 lines at 28.6364MHz. This mode aims for even faster AF control than 2/8-line readout
mode.
9. AF mode (2)
In this mode, the undesired portions are swept by vertical register high-speed transfer, and the vertical
300-pixel region in the center of the picture is output in approximately 1/120s by reading out the signals for
only two out of eight lines (1st and 6th lines, 9th and 14th lines). The number of output lines is 75 lines at
36MHz, and 43 lines at 28.6364MHz. This mode aims for even faster AF control than 2/8-line readout
mode.
– 16 –
ICX274AQF
Center scan and AF modes
Undesired portions (Swept by vertical register high-speed transfer)
Picture center cut-out portion
Description of Center Scan and AF Mode Operation
The center scan and AF modes realize high frame rates by sweeping the top and bottom of the picture with
high-speed transfer and cutting out the center of the picture.
The various readout modes during center scan and AF operation are described below.
• AF modes
AF mode (1), (2): The output method is the same as readout in 2/8-line readout mode.
• Center scan modes
Center scan mode (1): The output method is the same as 2/4-line readout mode.
Center scan mode (2): The output method consists of 2-line addition readout whereby the signals for only
two out of four lines (3rd and 4th lines, 7th and 8th lines, and so on) are read out,
the vertical register is shifted by 2 bits, and then the signals of the remaining two
out of the four lines (1st and 2nd lines, 5th and 6th lines, and so on) are read out
and added within the vertical register.
Center scan mode (3): The output method is the same as progressive scan mode.
The readout method, frame rate, number of output lines and other information for each readout mode are
shown in the table below.
Mode
Readout method
Addition
method
Number of output
Frame rate (frame/s) effective pixel data
lines
28.6MHz
36MHz
28.6MHz
36MHz
Progressive scan mode
Progressive scan
None
9.99
14.985
1220
1220
2/8-line readout mode
2/8-line readout
None
29.97
29.97
305
305
2/4-line readout mode
2/4-line readout
None
19.98
19.98
610
610
2-line addition mode
2/4-line readout
Vertical 2-line
19.98
19.98
1220
1220
Center scan mode (1)
2/4-line readout
None
29.97
29.97
434
568
Center scan mode (2)
2-line addition readout Vertical 2-line
29.97
29.97
434
568
Center scan mode (3)
Progressive scan
None
29.97
29.97
444
580
AF mode (1)
2/8-line readout
None
59.94
59.94
170
235
AF mode (2)
2/8-line readout
None
119.88
119.88
43
75
– 17 –
ICX274AQF
Measurement conditions
(1) In the following measurements, the device drive conditions are at the typical values of the bias and clock
voltage conditions, and the progressive scan readout mode is used.
(2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical
black level (OB) is used as the reference for the signal output, which is taken as the value of the Gr/Gb
signal output or the R/B signal output of the measurement system.
Definition of standard imaging conditions
(1) Standard imaging condition I:
Use a pattern box (luminance: 706cd/m2, color temperature of 3200K halogen source) as a subject.
(Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR
cut filter and image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined
as the standard sensitivity testing luminous intensity.
(2) Standard imaging condition II:
Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles.
Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted
to the value indicated in each testing item by the lens diaphragm.
1. Sensitivity
Set to the standard imaging condition I. After setting the electronic shutter mode with a shutter speed of
1/100s, measure the signal voltages (VGr, VGb) at the center of each Gr and Gb channel screen, and
substitute the values into the following formulas.
VG = (VGr + VGb)/2
Sg = VG × 100 [mV]
30
2. Saturation signal
Set to the standard imaging condition II. After adjusting the luminous intensity to 20 times the intensity with
the average value of the G channel signal output, 150mV, measure the minimum values of the G, R and B
signal outputs.
3. Smear
Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, first adjust the average value
of the Gr signal output to 150mV. Measure the average values of the Gr signal output, Gb signal output, R
signal output and B signal output (Gra, Gba, Ra, Ba), and then adjust the luminous intensity to 500 times
the intensity with the average value of the Gr signal output, 150mV. After the readout clock is stopped and
the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum
value (Vsm [mV]) independent of the Gr, Gb, R and B signal outputs, and substitute the values into the
following formula.
Smear in modes other than progressive scan mode is calculated from the storage time and signal
addition method. As a result, 2-line addition mode and center scan modes (2) and (3) are the same as
progressive scan mode, 2/4-line readout mode and center scan mode (1) are two times progressive scan
mode, and 2/8-line readout mode and AF modes (1) and (2) are four times progressive scan mode.
(
Sm = 20 × log Vsm ÷ Gra + Gba + Ra + Ba × 1 × 1
4
500
10
– 18 –
) [dB] (1/10V method conversion value)
ICX274AQF
4. Video signal shading
Set to the standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjusting the luminous
intensity so that the average value of the G channel signal output is 150mV. Then measure the maximum
value (Gmax [mV]) and minimum value (Gmin [mV]) of the G signal output and substitute the values into
the following formula.
SH = (Gmax – Gmin)/150 × 100 [%]
5. Uniformity between video signal channels
After measuring 4, measure the maximum (Rmax [mV]) and minimum (Rmin [mV]) values of the R signal
and the maximum (Bmax [mV]) and minimum (Bmin [mV]) values of the B signal, and substitute the values
into the following formulas.
∆Srg = (Rmax – Rmin)/150 × 100 [%]
∆Sbg = (Bmax – Bmin)/150 × 100 [%]
6. Dark signal
Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature of 60°C
and the device in the light-obstructed state, using the horizontal idle transfer level as a reference.
7. Dark signal shading
After measuring 6, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark
signal output and substitute the values into the following formula.
∆Vdt = Vdmax – Vdmin [mV]
8. Line crawl
Set to the standard imaging condition II. Adjusting the luminous intensity so that the value of the Gr signal
output is 150mV, and then insert R, G and B filters and measure the difference between G signal lines
(∆Glr, ∆Glg, ∆Glb [mV]) as well as the value of the G signal output (Gar, Gag, Gab). Substitute the values
into the following formula.
Lci = ∆Gli × 100 [%] (i = r, g, b)
Gai
9. Lag
Adjust the Y signal output generated by the strobe light to 150mV. After setting the strobe light so that it
strobes with the following timing, measure the residual signal amount (Vlag). Substitute the value into the
following formula.
Lag = (Vlag/150) × 100 [%]
VD
Light
Strobe light timing
Y signal output 150mV
Output
– 19 –
Vlag (lag)
0.1
CXD3400N
18
17
16
3
4
5
6
7
8
9
10
XV3
XSG3B
XSG3A
XV2
XSG2B
XSG2A
XV4
XV1
0.1
1/35V
0.1
Note) Substrate bias control
Switch the substrate bias adjustment input voltage to
DCIN before adjusting the substrate bias in 2-line
addition mode and center scan mode (2).
φRG
Hφ2B
Hφ1B
Hφ2A
Hφ1A
11
12
13
14
15
19
2
XSUB
20
11
1
12
9
13
14
15
16
10
8
7
6
XV2
XSG2C
CXD3400N
17
5
4
XSG3C
18
0.1
0.1
1
2
3
4
Substrate bias
φSUB pin voltage
5
6
7
8
ICX274
(BOTTOM VIEW)
9 10
3.3/16V
0.1
2200p
20 19 18 17 16 15 14 13 12 11
Substrate bias adjustment input voltage
(VSUB in the circuit diagram above)
0.1
0.1
Vφ4
Hφ2A
19
Vφ3A
Hφ1A
3
Vφ3B
VL
2
Vφ3C
CSUB
100k
Vφ2A
φSUB
20
Vφ2C
1
Vφ2B
GND
– 20 –
Hφ1B
XV3
0.1
Vφ1
Hφ2B
3.3V
GND
φRG
15V
VOUT
VDD
Drive Circuit
0.01
VSUB
CCD
OUT
Modes other than the above
VSUB (Internally generated value)
2-line addition mode
VSUB2 Center scan mode (2)
GND
DCIN
1M
3.3/20V
4.7k
2SC4250
–7.5V
ICX274AQF
– 21 –
CCD
OUT
V4
V3
V2
V1
"a"
1235
1236
1235
1236
Note) The 1252H horizontal period at 36MHz is 480clk; the 1493H horizontal period at 28MHz is 1860clk.
28.6MHz
HD
1249
1250
1251
1252
36MHz
1492
1493
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
VD
"a"
28.6MHz
Progressive Scan Mode
1249
1250
1251
1252
36MHz
1492
1493
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
Drive Timing Chart (Vertical Sync)
ICX274AQF
– 22 –
SUB
V4
V3A/V3B/V3C
V2A/V2B/V2C
V1
SHD
SHP
RG
H2A/H2B
H1A/H1B
CLK
1920
1 4
1
1
1
1
1
1
1
52 1
Drive Timing Chart (Horizontal Sync)
18
1
36
1
54
1
Progressive Scan Mode
54
1
90
1
54
1
90
1
135
1
60
1
9
78
114
96
132
204 1
28 1
12
ICX274AQF
296
V4
V3A/V3B/V3C
V2A/V2B/V2C
V1
H1A/H1B
"a" enlarged
18 18 18 18 18 18 18 18 60
Drive Timing Chart (Vertical Sync)
Progressive Scan Mode
1100
1250
18 18 18 18 18
ICX274AQF
– 23 –
– 24 –
CCD
OUT
Mechanical
shutter
TRG
SUB
V4
V3A/V3B/V3C
V2A/V2B/V2C
V1
HD
1
2
3
4
5
6
7
8
9
10
11
"a"
72
70
CLOSE
Note) The 1564 and 1565H horizontal periods at 36MHz are 1021clk; the 1742H horizontal period at 28MHz is 1530clk.
"b"
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
VD
1564
1565
36MHz
Progressive Scan Mode (With Mechanical Shutter)
1742
1
28.6MHz
Drive Timing Chart (Vertical Sync)
OPEN
ICX274AQF
1235
1236
1321
– 25 –
V4
V3A/V3B
V3C
V2A/V2B
V2C
V1
H1A/H1B
"b" enlarged
Progressive Scan Mode (With Mechanical Shutter)
134400 bits
#1
#2
#3
#1865
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
Drive Timing Chart (Vertical Sync)
18 18 18 18 18 18 18 18 60
ICX274AQF
1
– 26 –
CCD
OUT
V4
V3B/V3C
V3A
V2B/V2C
V2A
V1
406
407
"a"
36MHz
311
312
1225
1230
1233
Note) The 511H horizontal period at 36MHz is 1680clk; the 406 and 407H horizontal periods at 28MHz are 1470clk.
28.6MHz
510
511
1
2
3
4
5
6
7
8
9
10
11
12
13
14
3
8
1
6
9
14
17
22
25
30
33
38
41
46
HD
311
312
1225
1230
1233
VD
"a"
36MHz
2/8-line Readout Mode
406
407
28.6MHz
510
511
1
2
3
4
5
6
7
8
9
10
11
12
13
14
3
8
1
6
9
14
17
22
25
30
33
38
41
46
Drive Timing Chart (Vertical Sync)
ICX274AQF
– 27 –
SUB
V4
V3B/V3C
V3A
V2B/V2C
V2A
V1
SHD
SHP
RG
H2A/H2B
H1A/H1B
CLK
2352
1 4
1
1
1
1
1
1
1
1
1
52 1
36
18
1
1
54
54
1
1
54
Drive Timing Chart (Horizontal Sync)
90
90
1
1
1
54
54
90
1
1
1
54
54
1
1
90
54
1
1
90
90
1
1
54
90
90
1
1
1
54
54
90
1
1
2/8-line Readout Mode
1
54
54
1
1
90
54
1
1
90
90
1
1
54
90
90
1
1
1
54
54
90
1
1
1
54
54
1
1
90
54
1
1
90
90
1
1
54
90
90
1
1
1
54
54
567 1
1
54 1
54 1
36 1
36 1
1 18
90
1
1
72
1
60
1 9
60
60
60
60
60
60
636 1
28 1
12
ICX274AQF
728
– 28 –
V4
V3B/V3C
V3A
V2B/V2C
V2A
V1
H1A/H1B
"a" enlarged
1100
18 18 18 18 18 18 18 18 18 18
18 18 18 18 18 18 18 18 18
1250
2/8-line Readout Mode
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 42
Drive Timing Chart (Vertical Sync)
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 60
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
ICX274AQF
– 29 –
CCD
OUT
V4
V3A/V3B
V3C
V2A/V2B
V2C
V1
"a"
1231
1232
1235
1236
625
Note) The 871H horizontal period at 36MHz is 900clk; the 693H horizontal period at 28MHz is 810clk.
36MHz
HD
693
28.6MHz
871
1
2
3
4
5
6
7
8
9
10
5
6
9
10
3
4
7
8
VD
"a"
36MHz
2/4-line Readout Mode
693
28.6MHz
871
1
2
3
4
5
6
7
8
9
10
5
6
9
10
3
4
7
8
Drive Timing Chart (Vertical Sync)
ICX274AQF
652
1231
1232
1235
1236
– 30 –
SUB
V4
V3A/V3B/V3C
V2A/V2B/V2C
V1
SHD
SHP
RG
H2A/H2B
H1A/H1B
CLK
2070
1 4
1
1
1
1
1
1
1
52 1
18
1
Drive Timing Chart (Horizontal Sync)
36
1
54
1
54
1
90
1
54
1
90
2/4-line Readout Mode
1
54
1
90
1
54
1
90
1
54
1
54
1
54
1
90
282
1
1
1
60
12
84
120
102
138
354 1
28 1
12
ICX274AQF
446
– 31 –
V4
V3A/V3B
V3C
V2A/V2B
V2C
V1
H1A/H1B
"a" enlarged
600
54
750
2/4-line Readout Mode
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 66
Drive Timing Chart (Vertical Sync)
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
54
150
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
ICX274AQF
CCD
OUT
V4
V3A/V3B
V3C
V2A/V2B
V2C
V1
693
"a"
36MHz
625
1229 1231
1230 1232
1233 1235
1234 1236
1
2
Note) The 871H horizontal period at 36MHz is 900clk; the 693H horizontal period at 28MHz is 810clk.
28.6MHz
871
1
2
3
4
5
6
7
8
9
10
5
6
9
10
3
4
7
8
3
4
7
8
1
2
5
6
HD
"a"
36MHz
VD
693
28.6MHz
871
1
2
3
4
5
6
7
8
9
10
5
6
9
10
3
4
7
8
2-line Addition Mode
625
1231
1232
1235
1236
1229
1230
1233
1234
1
2
– 32 –
3
4
7
8
1
2
5
6
Drive Timing Chart (Vertical Sync)
ICX274AQF
– 33 –
SUB
V4
V3A/V3B/V3C
V2A/V2B/V2C
V1
SHD
SHP
RG
H2A/H2B
H1A/H1B
CLK
2070
1 4
1
1
1
1
1
1
1
52 1
18
1
Drive Timing Chart (Horizontal Sync)
36
1
54
1
54
1
90
1
54
1
2-line Addition Mode
90
1
54
1
90
1
54
1
90
1
54
1
54
1
54
1
90
282
1
1
1
60
12
84
120
102
138
354 1
28 1
12
ICX274AQF
446
– 34 –
V4
V3A/V3B
V3C
V2A/V2B
V2C
V1
H1A/H1B
"a" enlarged
600
2-line Addition Mode
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 66
Drive Timing Chart (Vertical Sync)
54
750
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
54
150
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
ICX274AQF
– 35 –
CCD
OUT
V4
V3A/V3B
V3C
V2A/V2B
V2C
V1
HD
VD
Center Scan Mode (1)/(28.6MHz)
"a" "b"
458
459
460
461
462
1
2
3
4
5
6
7
8
9
10
Note) The 462H horizontal period is 1230clk.
"d"
450
451
452
453
1052
1055
"d"
450
451
452
453
1048
1051
1052
1055
188
191
192
195
17
15
Drive Timing Chart (Vertical Sync)
459
460
461
462
1
2
3
4
5
6
7
8
9
10
"a" "b"
ICX274AQF
188
191
192
17
15
– 36 –
CCD
OUT
V4
V3A/V3B
V3C
V2A/V2B
V2C
V1
HD
"d"
"a" "b"
Note) The 581H horizontal period is 601clk.
1183
1184
1187
1188
576
577
578
579
580
581
1
2
3
4
5
6
7
8
9
10
55
56
59
60
VD
Center Scan Mode (1)/(36MHz)
1183
1184
1187
1188
"d"
"a" "b"
576
577
578
579
580
581
1
2
3
4
5
6
7
8
9
10
55
56
59
60
Drive Timing Chart (Vertical Sync)
ICX274AQF
– 37 –
V4
V3A/V3B
V3C
V2A/V2B
V2C
V1
H1A/H1B
"a" enlarged
600
54
750
Center Scan Mode (1)
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 66
Drive Timing Chart (Vertical Sync)
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
ICX274AQF
– 38 –
V4
V3A/V3B
V3C
V2A/V2B
V2C
V1
H1A/H1B
"b" enlarged
#5
#6
Center Scan Mode (1)/(28.6MHz)
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
Drive Timing Chart (Vertical Sync)
#187
27936 bits
28980 bits = 14H
ICX274AQF
– 39 –
V4
V3A/V3B
V3C
V2A/V2B
V2C
V1
H1A/H1B
"b" enlarged
#5
#6
Center Scan Mode (1)/(36MHz)
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
Drive Timing Chart (Vertical Sync)
#52
8784 bits
10350 bits = 5H
ICX274AQF
– 40 –
CCD
OUT
V4
V3A/V3B
V3C
V2A/V2B
V2C
V1
HD
VD
"a"
"b"
Note) The 462H horizontal period is 1230clk.
"d"
Center Scan Mode (2)/(28.6MHz)
188
191
192
195
186
189
190
193
18
"d"
1048
1051
1052
1055
1046
1049
1050
1053
Drive Timing Chart (Vertical Sync)
1050 1052
1053 1055
452
453
454
455
456
457
458
459
460
461
462
1
2
3
4
5
6
7
8
9
10
15
188
191
192
186
189
190
"a" "b"
452
453
454
455
456
457
458
459
460
461
462
1
2
3
4
5
6
7
8
9
10
15
18
ICX274AQF
CCD
OUT
V4
V3A/V3B
V3C
V2A/V2B
"d"
"a" "b"
Note) The 581H horizontal period is 601clk.
1183
1184
1187
1188
1181
1182
1185
1186
V2C
"a" "b"
55
56
59
60
53
54
57
58
V1
"d"
1183
1184
1187
1188
1181
1182
1185
1186
HD
576
577
578
579
580
581
1
2
3
4
5
6
7
8
9
10
55
56
59
60
– 41 –
53
54
57
58
VD
Center Scan Mode (2)/(36MHz)
576
577
578
579
580
581
1
2
3
4
5
6
7
8
9
10
Drive Timing Chart (Vertical Sync)
ICX274AQF
– 42 –
V4
V3A/V3B
V3C
V2A/V2B
V2C
V1
H1A/H1B
"a" enlarged
600
Center Scan Mode (2)
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 66
Drive Timing Chart (Vertical Sync)
750
54 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
54
150
18 18 18 18 18 18 18 18
ICX274AQF
– 43 –
V4
V3A/V3B
V3C
V2A/V2B
V2C
V1
H1A/H1B
"b" enlarged
# (3 + 5)
# (4 + 6)
Center Scan Mode (2)/(28.6MHz)
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
Drive Timing Chart (Vertical Sync)
# (185 + 187)
27936 bits
28980 bits = 14H
ICX274AQF
– 44 –
V4
V3A/V3B
V3C
V2A/V2B
V2C
V1
H1A/H1B
"b" enlarged
# (3 + 5)
# (4 + 6)
Center Scan Mode (2)/(36MHz)
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
Drive Timing Chart (Vertical Sync)
# (50 + 52)
8784 bits
10350 bits = 5H
ICX274AQF
– 45 –
SUB
V4
V3A/V3B/V3C
V2A/V2B/V2C
V1
SHD
SHP
RG
H2A/H2B
H1A/H1B
CLK
2070
1 4
1
1
1
1
1
1
1
52 1
18
1
Drive Timing Chart (Horizontal Sync)
36
1
54
1
54
1
90
1
54
1
90
1
54
1
Center Scan Modes (1) and (2)
90
1
54
1
90
1
54
1
90
1
54
1
90
282
1
1
1
60
12
84
120
102
138
354 1
28 1
12
ICX274AQF
446
– 46 –
V4
V3A/V3B
V3C
V2A/V2B
V2C
V1
H1A/H1B
"d" enlarged
Center Scan Modes (1) and (2)/(28.6MHz)
16560 bits
#1
#2
#3
#222
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
Drive Timing Chart (Vertical Sync)
ICX274AQF
1
– 47 –
V4
V3A/V3B
V3C
V2A/V2B
V2C
V1
H1A/H1B
"d" enlarged
Center Scan Modes (1) and (2)/(36MHz)
6210 bits
#1
#2
#3
#63
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
Drive Timing Chart (Vertical Sync)
ICX274AQF
1
– 48 –
CCD
OUT
V4
V3
V2
V1
HD
"a"
"b"
496
497
498
1
2
3
4
5
6
Note) The 498H horizontal period is 1260clk.
"d"
478
479
839
840
VD
32
33
34
35
397
398
"d"
478
479
839
840
Center Scan Mode (3)/(28.6MHz)
496
497
498
1
2
3
4
5
6
"a" "b"
32
33
34
35
397
398
Drive Timing Chart (Vertical Sync)
ICX274AQF
– 49 –
CCD
OUT
V4
V3
V2
V1
HD
"d"
609
610
"a"
"b"
624
625
626
1
2
3
4
5
6
Note) The 626H horizontal period is 1200clk.
907
908
VD
27
28
29
30
31
329
330
"d"
609
610
907
908
Center Scan Mode (3)/(36MHz)
624
625
626
1
2
3
4
5
6
"a" "b"
27
28
29
30
329
330
Drive Timing Chart (Vertical Sync)
ICX274AQF
– 50 –
SUB
V4
V3A/V3B/V3C
V2A/V2B/V2C
V1
SHD
SHP
RG
H2A/H2B
H1A/H1B
CLK
1920
1 4
1
1
1
1
1
1
1
52 1
Drive Timing Chart (Horizontal Sync)
18
1
36
1
54
1
Center Scan Mode (3)
54
1
90
1
54
1
90
1
135
1
60
1
9
78
114
96
132
204 1
28 1
12
ICX274AQF
296
V4
V3A/V3B/V3C
V2A/V2B/V2C
V1
H1A/H1B
"a" enlarged
18 18 18 18 18 18 18 18 60
Drive Timing Chart (Vertical Sync)
Center Scan Mode (3)
1100
1250
18 18 18 18 18
ICX274AQF
– 51 –
– 52 –
V4
V3A/V3B
V3C
V2A/V2B
V2C
V1
H1A/H1B
"b" enlarged
Center Scan Mode (3)/(28.6MHz)
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
Drive Timing Chart (Vertical Sync)
58608 bits
59520 bits = 31H
ICX274AQF
– 53 –
V4
V3A/V3B
V3C
V2A/V2B
V2C
V1
H1A/H1B
"b" enlarged
Center Scan Mode (3)/(36MHz)
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
Drive Timing Chart (Vertical Sync)
48816 bits
49920 bits = 26H
ICX274AQF
– 54 –
V4
V3A/V3B
V3C
V2A/V2B
V2C
V1
H1A/H1B
"d" enlarged
Center Scan Mode (3)/(28.6MHz)
34560 bits
#1
#2
#3
#398
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
Drive Timing Chart (Vertical Sync)
ICX274AQF
1
– 55 –
V4
V3A/V3B
V3C
V2A/V2B
V2C
V1
H1A/H1B
"d" enlarged
Center Scan Mode (3)/(36MHz)
28800 bits
#1
#2
#3
#330
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
Drive Timing Chart (Vertical Sync)
ICX274AQF
1
– 56 –
CCD
OUT
V4
V3B/V3C
V3A
V2B/V2C
V2A
V1
HD
"a"
"b"
201
202
203
204
1
2
3
4
5
6
7
8
Note) The 203 and 204H horizontal periods are 1323clk.
"d"
190
191
953
958
VD
19
20
21
22
286
289
"d"
190
191
953
958
AF Mode (1)/(28.6MHz)
201
202
203
204
1
2
3
4
5
6
7
8
9
"a" "b"
19
20
21
22
286
289
Drive Timing Chart (Vertical Sync)
ICX274AQF
– 57 –
CCD
OUT
V4
V3B/V3C
V3A
V2B/V2C
V2A
V1
HD
VD
AF Mode (1)/(36MHz)
"a"
"b"
Note) The 256H horizontal period is 840clk.
"d"
248
249
1086
1089
254
255
256
1
2
3
4
5
6
7
8
9
10
11
12
13
14
153
158
"d"
248
249
1086
1089
"a" "b"
254
255
256
1
2
3
4
5
6
7
8
9
10
11
12
13
14
153
158
Drive Timing Chart (Vertical Sync)
ICX274AQF
– 58 –
V4
V3A/V3B
V3C
V2A/V2B
V2C
V1
H1A/H1B
"b" enlarged
AF Mode (1)/(28.6MHz)
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
Drive Timing Chart (Vertical Sync)
41904 bits
42336 bits = 18H
ICX274AQF
– 59 –
V4
V3A/V3B
V3C
V2A/V2B
V2C
V1
H1A/H1B
"b" enlarged
AF Mode (1)/(36MHz)
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
Drive Timing Chart (Vertical Sync)
22896 bits
23520 bits = 10H
ICX274AQF
– 60 –
V4
V3A/V3B
V3C
V2A/V2B
V2C
V1
H1A/H1B
"d" enlarged
AF Mode (1)/(28.6MHz)
25872 bits
#1
#2
#3
#339
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
Drive Timing Chart (Vertical Sync)
ICX274AQF
1
– 61 –
V4
V3A/V3B
V3C
V2A/V2B
V2C
V1
H1A/H1B
"d" enlarged
AF Mode (1)/(36MHz)
14112 bits
#1
#2
#3
#180
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
Drive Timing Chart (Vertical Sync)
ICX274AQF
1
– 62 –
CCD
OUT
V4
V3B/V3C
V3A
V2B/V2C
V2A
V1
HD
"a"
"b"
100
101
102
1
2
3
4
5
6
7
8
9
Note) The 102H horizontal period is 1323clk.
"d"
80
81
702
705
VD
35
36
37
38
537
542
"d"
80
81
702
705
AF Mode (2)/(28.6MHz)
100
101
102
1
2
3
4
5
6
7
8
9
"a" "b"
35
36
37
38
537
542
Drive Timing Chart (Vertical Sync)
ICX274AQF
– 63 –
CCD
OUT
V4
V3B/V3C
V3A
V2B/V2C
V2A
V1
HD
"a" "b"
126
127
128
1
2
3
4
5
6
7
8
9
Note) The 128H horizontal period is 1596clk.
"d"
108
109
766
769
VD
31
32
33
34
473
478
"d"
108
109
766
769
AF Mode (2)/(36MHz)
126
127
128
1
2
3
4
5
6
7
8
9
"a" "b"
31
32
33
34
473
478
Drive Timing Chart (Vertical Sync)
ICX274AQF
– 64 –
V4
V3A/V3B
V3C
V2A/V2B
V2C
V1
H1A/H1B
"b" enlarged
AF Mode (2)/(28.6MHz)
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
Drive Timing Chart (Vertical Sync)
78192 bits
79968 bits = 34H
ICX274AQF
– 65 –
V4
V3A/V3B
V3C
V2A/V2B
V2C
V1
H1A/H1B
"b" enlarged
AF Mode (2)/(36MHz)
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
Drive Timing Chart (Vertical Sync)
68976 bits
70560 bits = 30H
ICX274AQF
– 66 –
V4
V3A/V3B
V3C
V2A/V2B
V2C
V1
H1A/H1B
"d" enlarged
AF Mode (2)/(28.6MHz)
47040 bits
#1
#2
#3
#640
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
Drive Timing Chart (Vertical Sync)
ICX274AQF
1
– 67 –
V4
V3A/V3B
V3C
V2A/V2B
V2C
V1
H1A/H1B
"d" enlarged
AF Mode (2)/(36MHz)
42336 bits
#1
#2
#3
#564
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
Drive Timing Chart (Vertical Sync)
ICX274AQF
1
– 68 –
SUB
V4
V3B/V3C
V3A
V2B/V2C
V2A
V1
SHD
SHP
RG
H2A/H2B
H1A/H1B
CLK
2352
1 4
1
1
1
1
1
1
1
1
1
52 1
36
18
1
1
54
54
1
1
54
Drive Timing Chart (Horizontal Sync)
90
90
1
1
1
54
54
90
1
1
1
54
54
1
1
90
54
1
1
90
90
1
1
54
90
90
1
1
1
54
54
90
1
1
AF Modes (1) and (2)
1
54
54
1
1
90
54
1
1
90
90
1
1
54
90
90
1
1
1
54
54
90
1
1
1
54
54
1
1
90
54
1
1
90
90
1
1
54
90
90
1
1
1
54
54
72
567 1
1
54 1
54 1
36 1
36 1
1 18
90
1
1
1
60
1 9
60
60
60
60
60
60
636 1
28 1
12
ICX274AQF
728
– 69 –
V4
V3B/V3C
V3A
V2B/V2C
V2A
V1
H1A/H1B
"a" enlarged
1100
18 18 18 18 18 18 18 18 18 18 18 18 18 18
18 18 18 18 18 18 18 18 18 18 18 18 18
1250
AF Modes (1) and (2)
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 42
Drive Timing Chart (Vertical Sync)
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 60
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
ICX274AQF
ICX274AQF
Notes of Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non-chargeable gloves, clothes or material.
Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensors.
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.
2) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W
soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.
c) To dismount an image sensor, do not use a solder suction equipment. When using an electric
desoldering tool, use a thermal controller of the zero-cross On/Off type and connect it to ground.
3) Dust and dirt protection
Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and
dirt. Clean glass plates with the following operations as required, and use them.
a) Perform all assembly operations in a clean room (class 1000 or less).
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should
dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized
air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if grease stained. Be careful not to scratch the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
e) When a protective tape is applied before shipping, just before use remove the tape applied for
electrostatic protection. Do not reuse the tape.
4) Installing (attaching)
a) Remain within the following limits when applying a static load to the package. Do not apply any load
more than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to
limited portions. (This may cause cracks in the package.)
Cover glass
50N
50N
1.2Nm
Plastic package
Compressive strength
Torsional strength
b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the
package may fracture, etc., depending on the flatness of the bottom of the package. Therefore, for
installation, use either an elastic load, such as a spring plate, or an adhesive.
– 70 –
ICX274AQF
c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated
voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area,
and indicated values should be transferred to other locations as a precaution.
d) The notch of the package is used for directional index, and that can not be used for reference of fixing.
In addition, the cover glass and seal resin may overlap with the notch of the package.
e) If the leads are bent repeatedly and metal, etc., clash or rub against the package, the dust may be
generated by the fragments of resin.
f) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyanoacrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives.
(reference)
5) Others
a) Do not expose to strong light (sun rays) for long periods, as color filters will be discolored. When high
luminous objects are imaged with the exposure level controlled by the electronic iris, the luminance of
the image-plane may become excessive and discoloring of the color filter will possibly be accelerated. In
such a case, it is advisable that taking-lens with the automatic-iris and closing of the shutter during the
power-off mode should be properly arranged. For continuous using under cruel condition exceeding the
normal using condition, consult our company.
b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.
c) Brown stains may be seen on the bottom or side of the package. But this does not affect the CCD
characteristics.
d) This package has 2 kinds of internal structure. However, their package outline, optical size, and strength
are the same.
Structure A
Structure B
Package
Chip
Metal plate
(lead frame)
Cross section of
lead frame
The cross section of lead frame can be seen on the side of the package for structure A.
– 71 –
B
– 72 –
2.5
0.5
2.5
9.0
~
~
1.27
12.7
DRAWING NUMBER
AS-B7-03(E)
0.95g
42 ALLOY
LEAD MATERIAL
PACKAGE MASS
GOLD PLATING
LEAD TREATMENT
0.3
10.0
M
11
A
~
2.5
10
0.3
13.8 ± 0.1
H
Plastic
1
V
20
PACKAGE MATERIAL
PACKAGE STRUCTURE
0.8
6.0
1.0 ± 0.1
6.9
B'
12.0 ± 0.1
0.5
2.4
10.9
0.8
D
0˚ to
0.25
(0.6)
10˚
C
0.15
1.7
10
11
1.7
1.7
1
20
1.7
9. The notches on the bottom of the package are used only for directional index, they must
not be used for reference of fixing.
8. The thickness of the cover glass is 0.5mm, and the refractive index is 1.5.
7. The tilt of the effective image area relative to the bottom “C” is less than 50µm.
The tilt of the effective image area relative to the top “D” of the cover glass is less than 50µm.
6. The height from the bottom “C” to the effective image area is 1.41 ± 0.10mm.
The height from the top of the cover glass “D” to the effective image area is 1.49 ± 0.15mm.
5. The rotation angle of the effective image area relative to H and V is ±0.7˚.
4. The center of the effective image area relative to “B” and “B'” is (H, V) = (6.9, 6.0) ± 0.075mm.
3. The bottom “C” of the package, and the top of the cover glass “D” are the height reference.
2. The two points “B” of the package are the horizontal reference.
The point “B'” of the package is the vertical reference.
1. “A” is the center of the effective image area.
20 pin SOP
2.9 ± 0.15
Unit: mm
14.0 ± 0.15
Package Outline
ICX274AQF
Sony Corporation