ICX252AQ Diagonal 8.933mm (Type 1/1.8) Frame Readout CCD Image Sensor with Square Pixel for Color Cameras Description The ICX252AQ is a diagonal 8.933mm (Type 1/1.8) interline CCD solid-state image sensor with a square pixel array and 3.24M effective pixels. Frame readout allows all pixels' signals to be output independently within approximately 1/4.28 second. Also, number of vertical pixels decimation allows output of 30 frames per second in high frame rate readout mode. R, G, B primary color mosaic filters are used as the color filters, and at the same time high sensitivity and low dark current are achieved through the adoption of Super HAD CCD technology. This chip is suitable for applications such as electronic still cameras, etc. Features • Supports frame readout • High horizontal and vertical resolution • Supports high frame rate readout mode: 30 frames/s, AF1 mode: 60 frames/s, 50 frames/s, AF2 mode: 120 frames/s, 100 frames/s • Square pixel • Horizontal drive frequency: 18MHz • No voltage adjustments (reset gate and substrate bias are not adjusted.) • R, G, B primary color mosaic filters on chip • High sensitivity, low dark current • Continuous variable-speed shutter • Excellent anti-blooming characteristics • Exit pupil distance recommended range –20 to –100mm • 20-pin high-precision plastic package Device Structure • Interline CCD image sensor • Total number of pixels: • Number of effective pixels: • Number of active pixels: • Number of recommended record pixels: • Chip size: • Unit cell size: • Optical black: • Number of dummy bits: • Substrate material: 20 pin DIP (Plastic) AAAAA AAAAA AAAAA AAAAA AAAAA Pin 1 2 V 4 Pin 11 H 8 48 Optical black position (Top View) 2140 (H) × 1560 (V) approx. 3.34M pixels 2088 (H) × 1550 (V) approx. 3.24M pixels 2080 (H) × 1542 (V) approx. 3.21M pixels diagonal 8.933mm 2048 (H) × 1536 (V) approx. 3.15M pixels diagonal 8.832mm aspect ratio 4:3 8.10mm (H) × 6.64mm (V) 3.45µm (H) × 3.45µm (V) Horizontal (H) direction: Front 4 pixels, rear 48 pixels Vertical (V) direction: Front 8 pixels, rear 2 pixels Horizontal 28 Vertical 1 (even fields only) Silicon ∗Super HAD CCD is a registered trademark of Sony Corporation. Super HAD CCD is a CCD that drastically improves sensitivity by introducing newly developed semiconductor technology by Sony Corporation into Sony's high-performance HAD (Hole-Accumulation Diode) sensor Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E00109-PS ICX252AQ GND TEST TEST Vφ1B Vφ1A Vφ2 Vφ3B Vφ3A Vφ4 10 9 8 7 6 5 4 3 2 1 Vertical register VOUT Block Diagram and Pin Configuration (Top View) Gb B Gb B R Gr R Gr Gb B Gb B R Gr R Gr Gb B Gb B R Gr R Gr Note) Horizontal register 14 15 16 17 φRG Hφ2 Hφ1 GND φSUB CSUB 18 19 : Photo sensor 20 Hφ2 13 Hφ1 12 VL 11 VDD Note) Pin Description Pin No. Symbol Description Pin No. Symbol Description 1 Vφ4 Vertical register transfer clock 11 VDD Supply voltage 2 Vφ3A Vertical register transfer clock 12 φRG Reset gate clock 3 Vφ3B Vertical register transfer clock 13 Hφ2 Horizontal register transfer clock 4 Vφ2 Vertical register transfer clock 14 Hφ1 Horizontal register transfer clock 5 Vφ1A Vertical register transfer clock 15 GND GND 6 Vφ1B 16 φSUB 7 TEST Vertical register transfer clock Test pin∗1 17 CSUB Substrate clock Substrate bias∗2 8 TEST Test pin∗1 18 VL Protective transistor bias 9 GND GND 19 Hφ1 Horizontal register transfer clock 10 VOUT Signal output 20 Hφ2 Horizontal register transfer clock ∗1 Leave this pin open. ∗2 DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance of 0.1µF. –2– ICX252AQ Absolute Maximum Ratings Item Ratings Unit Remarks VDD, VOUT, φRG – φSUB –40 to +12 V Vφ1A, Vφ1B, Vφ3A, Vφ3B – φSUB –50 to +15 V Vφ2, Vφ4, VL – φSUB –50 to +0.3 V Hφ1, Hφ2, GND – φSUB –40 to +0.3 V CSUB – φSUB –25 to V VDD, VOUT, φRG, CSUB – GND –0.3 to +22 V Vφ1A, Vφ1B, Vφ2, Vφ3A, Vφ3B, Vφ4 – GND –10 to +18 V Hφ1, Hφ2 – GND –10 to +6.5 V Vφ1A, Vφ1B, Vφ3A, Vφ3B – VL –0.3 to +28 V Vφ2, Vφ4, Hφ1, Hφ2, GND – VL –0.3 to +15 V to +15 V Hφ1 – Hφ2 –6.5 to +6.5 V Hφ1, Hφ2 – Vφ4 –10 to +16 V Storage temperature –30 to +80 °C Guaranteed temperature of performance –10 to +60 °C Operating temperature –10 to +75 °C Against φSUB Against φSUB Against VL Voltage difference between vertical clock input pins Between input clock pins ∗1 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%. +16V (Max.) is guaranteed for turning on or off power supply. –3– ∗1 ICX252AQ Bias Conditions Item Symbol Min. Typ. Max. Unit 14.55 15.0 ∗1 15.45 V Supply voltage VDD Protective transistor bias VL Substrate clock φSUB ∗2 Reset gate clock φRG ∗2 Remarks ∗1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same voltage as the VL power supply for the V driver should be used. ∗2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated within the CCD. DC Characteristics Item Supply current Symbol Min. Typ. Max. Unit IDD 2.0 4.5 7.0 mA Remarks Clock Voltage Conditions Item Readout clock voltage Vertical transfer clock voltage Horizontal transfer clock voltage Reset gate clock voltage Min. Typ. Max. Unit Waveform diagram VVT 14.55 15.0 15.45 V 1 VVH1, VVH2 –0.05 0 0.05 V 2 VVH3, VVH4 –0.2 0 0.05 V 2 VVL1, VVL2, VVL3, VVL4 –8.0 –7.5 –7.0 V 2 VVL = (VVL3 + VVL4)/2 VφV 6.8 7.5 8.05 V 2 VφV = VVHn – VVLn (n = 1 to 4) Symbol Remarks VVH = (VVH1 + VVH2)/2 VVH3 – VVH –0.25 0.1 V 2 VVH4 – VVH –0.25 0.1 V 2 VVHH 0.6 V 2 High-level coupling VVHL 0.9 V 2 High-level coupling VVLH 0.9 V 2 Low-level coupling VVLL 0.5 V 2 Low-level coupling VφH 4.75 5.0 5.25 V 3 VHL –0.05 0 0.05 V 3 VCR 0.8 2.5 V 3 VφRG 3.0 3.3 5.25 V 4 VRGLH – VRGLL 0.4 V 4 Low-level coupling VRGL – VRGLm 0.5 V 4 Low-level coupling 23.5 V 5 Substrate clock voltage VφSUB 21.5 22.5 –4– Cross-point voltage ICX252AQ Clock Equivalent Circuit Constant Symbol Item Min. Typ. Max. Unit CφV1A, CφV3A 1500 pF CφV1B, CφV3B 5600 pF CφV2, CφV4 2700 pF CφV1A2, CφV3A4 390 pF CφV1B2, CφV3B4 470 pF CφV23A, CφV41A 120 pF CφV23B, CφV41B 180 pF CφV1A3A 39 pF CφV1B3B 220 pF CφV1A3B, CφV1B3A 62 pF CφV24 75 pF CφV1A1B, CφV3A3B 68 pF Capacitance between horizontal transfer CφH1, CφH2 clock and GND 36.5 pF Capacitance between horizontal transfer CφHH clocks 88.5 pF Capacitance between vertical transfer clock and GND Capacitance between vertical transfer clocks Capacitance between reset gate clock and GND CφRG 8 pF Capacitance between substrate clock and GND CφSUB 1000 pF Vertical transfer clock series resistor R1A, R1B, R2, R3A, R3B, R4 62 Ω Vertical transfer clock ground resistor RGND 18 Ω Horizontal transfer clock series resistor RφH 15 Ω Remarks Vφ2 R2 CφV1A3A CφV23B CφV23A Vφ3A R3A CφV24 CφV1A2 Vφ1A R1A RφH RφH Hφ1 CφV1B2 CφV1A CφV1A1B CφV1B3A CφV1B CφV41A Vφ1B CφV2 CφV3A RφH CφHH RφH Hφ1 CφV3A3B CφV1A3B CφV3B R1B CφV4 CφV41B Hφ2 Hφ2 CφH1 CφH2 CφV3A4 R3B Vφ3B CφV3B4 RGND CφV1B3B R4 Vφ4 Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit –5– ICX252AQ Drive Clock Waveform Conditions (1) Readout clock waveform 100% 90% II II φM φM 2 VVT 10% 0% tr twh 0V tf (2) Vertical transfer clock waveform Vφ1A, Vφ1B Vφ3A, Vφ3B VVHH VVH1 VVHH VVH VVHL VVHL VVH3 VVHL VVL1 VVH VVHH VVHH VVHL VVL3 VVLH VVLH VVLL VVLL VVL VVL Vφ2 Vφ4 VVHH VVHH VVH VVH VVHH VVHH VVHL VVH2 VVHL VVHL VVH4 VVL2 VVHL VVLH VVLH VVLL VVLL VVL VVL4 VVH = (VVH1 + VVH2)/2 VVL = (VVL3 + VVL4)/2 VφV = VVHn – VVLn (n = 1 to 4) –6– VVL ICX252AQ (3) Horizontal transfer clock waveform tr twh tf Hφ2 90% VCR VφH twl VφH 2 10% VHL Hφ1 two Cross-point voltage for the Hφ1 rising side of the horizontal transfer clocks Hφ1 and Hφ2 waveforms is VCR. The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two. (4) Reset gate clock waveform tr twh tf VRGH RG waveform twl VφRG Point A VRGLH VRGLL VRGLm VRGL VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL. VRGL = (VRGLH + VRGLL)/2 Assuming VRGH is the minimum value during the interval twh, then: VφRG = VRGH – VRGL Negative overshoot level during the falling edge of RG is VRGLm. (5) Substrate clock waveform 100% 90% φM φM 2 VφSUB VSUB 10% 0% tr twh (A bias generated within the CCD) –7– tf ICX252AQ Clock Switching Characteristics (Horizontal drive frequency: 18MHz) Item twh Symbol tr tf Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. 0.5 2.63 2.83 Readout clock VT Vertical transfer clock Vφ1A, Vφ1B, Vφ2, Vφ3A, Vφ3B, Vφ4 Horizontal transfer clock twl 0.5 15 µs 250 ns Hφ1 14 19.5 14 19.5 8.5 14 8.5 14 Hφ2 14 19.5 14 19.5 8.5 14 8.5 14 During Hφ1 parallel-serial Hφ2 conversion 6.67 0.01 0.01 5.56 0.01 0.01 37 4 5 During imaging Reset gate clock φRG Substrate clock φSUB 7 10 0.5 1.7 3.06 two Item Symbol Horizontal transfer clock Hφ1, Hφ2 Min. Typ. Max. 12 19.5 Unit Unit Remarks During readout When using CXD3400N ns tf ≥ tr – 2ns µs ns 0.5 µs During drain charge Remarks ns Spectral Sensitivity Characteristics (excludes lens characteristics and light source characteristics) 1.0 G B R Relative Response 0.8 0.6 0.4 0.2 0 400 450 500 550 Wave Length [nm] –8– 600 650 700 ICX252AQ Image Sensor Characteristics (Horizontal drive frequency: 18MHz) Item Symbol Unit Measurement method mV 1 Min. Typ. Sg 220 270 R Rr 0.3 0.45 0.6 1 B Rb 0.35 0.50 0.65 1 Saturation signal Vsat 450 Smear Sm G sensitivity Sensitivity comparison Video signal shading –89.1 –79.6 Max. (Ta = 25°C) –81.2 –71.6 20 SHg 25 mV 2 dB 3 % 4 Remarks 1/30s accumulation Ta = 60°C,∗1 Frame readout mode,∗2 High frame rate readout mode Zone 0 and I Zone 0 to II' Dark signal Vdt 12 mV 5 Ta = 60°C, 4.28 frame/s Dark signal shading ∆Vdt 6 mV 6 Ta = 60°C, 4.28 frame/s,∗3 Line crawl G Lcg 3.8 % 7 Line crawl R Lcr 3.8 % 7 Line crawl B Lcb 3.8 % 7 Lag Lag 0.5 % 8 ∗1 The saturation signal level is 450mV or more by performing pull-down CSUB pin at 1.3kΩ resistor. For high frame rate readout mode, it is 800mV. ∗2 After closing the mechanical shutter, the smear can be reduced to below the detection limit by performing vertical register sweep operation. ∗3 Excludes vertical dark signal shading caused by vertical register high-speed transfer. Zone Definition of Video Signal Shading 2088 (H) 4 4 4 V 10 H 8 H 8 Zone 0, I Zone II, II' V 10 1550 (V) 4 Ignored region Effective pixel region Measurement System CCD signal output [∗A] CCD C.D.S AMP S/H Gr/Gb channel signal output [∗B] S/H R/B channel signal output [∗C] Note) Adjust the amplifier gain so that the gain between [∗A] and [∗B], and between [∗A] and [∗C] equals 1. –9– ICX252AQ Image Sensor Characteristics Measurement Method Measurement conditions 1) In the following measurements, the device drive conditions are at the typical values of the bias and clock voltage conditions, and the frame readout mode is used. 2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black level (OB) is used as the reference for the signal output, which is taken as the value of the Gr/Gb channel signal output or the R/B channel signal output of the measurement system. Color coding of this image sensor & Readout B2 B1 Gb B Gb B R Gr R Gr Gb B Gb B R Gr R Gr A2 A1 The primary color filters of this image sensor are arranged in the layout shown in the figure on the left (Bayer arrangement). Gr and Gb denote the G signals on the same line as the R signal and the B signal, respectively. For frame readout, the A1 and A2 lines are output as signals in the A field, and the B1 and B2 lines in the B field. Horizontal register Color Coding Diagram – 10 – ICX252AQ Readout modes 1. Readout modes list The following readout modes are possible by driving the image sensor at the timing specifications noted in this Data Sheet. Mode name Frame rate Frame readout mode High frame rate readout mode AF1 mode AF2 mode Number of output effective lines NTSC mode 4.28 frame/s 1550 (Odd 775, Even 775) PAL mode 4.16 frame/s 1550 (Odd 775, Even 775) NTSC mode 30 frame/s 258 PAL mode 25 frame/s 258 NTSC mode 60 frame/s See Page.12 PAL mode 50 frame/s See Page.12 NTSC mode 120 frame/s See Page.12 PAL mode 100 frame/s See Page.12 2. Frame readout mode, high frame rate readout mode Frame readout mode High frame rate readout mode 2nd field 1st field 13 VOUT R Gr 13 R Gr 13 R Gr Gb B 12 Gb B 12 Gb B 12 11 R Gr 11 R Gr 11 R Gr 10 Gb B 10 Gb B 10 Gb B 9 R Gr Gr 9 R Gr Gb B 9 R 8 Gb B 8 Gb B 8 7 R Gr 7 R Gr 7 R Gr 6 Gb B 6 Gb B 6 Gb B 5 R Gr Gr 5 R Gr Gb B 5 R 4 Gb B 4 Gb B 4 3 R Gr 3 R Gr 3 R Gr 2 Gb B 2 Gb B 2 Gb B 1 R Gr Gr 1 R Gr VOUT 1 R VOUT Note) Blacked out portions in the diagram indicate pixels which are not read out. 1. Frame readout mode In this mode, all pixel signals are divided into two fields and output. All pixel signals are read out independently, making this mode suitable for high resolution image capturing. 2. High frame rate readout mode Output is performed at 30 frames per second by reading out 4 pixels for every 12 vertical pixels and adding 2 pixels in the horizontal CCD. The number of output lines is 258 lines. This readout mode emphasizes processing speed over vertical resolution. – 11 – ICX252AQ 3. AF1 mode, AF2 mode The AF modes increase the frame rate by cutting out a portion of the picture through high-speed elimination of the top and bottom of the picture in high frame rate readout mode. AF1 allows 1/60s and 1/50s output, and AF2 allows 1/120s and 1/100s output, so these modes are effective for raising the auto focus (AF) speed. In addition, the cut-out can begin from an optional line by controlling the number of frame shift lines that sweep the top of the picture. The relation between the number of frame shift lines, the output start position and number of output lines is shown in the table below. Top frame shift region (Number of shift lines = 0 to 255) AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA Number of effective lines in high frame rate readout mode 258 Cut-out region Bottom high-speed sweep region AF1 mode Frame rate Output start position on timing chart Number of frame shift lines Output lines∗1 AF2 mode NTSC PAL NTSC PAL 1/60s 1/50s 1/120s 1/100s 26H 26H 30H 30H i + 3 to i + 38 i + 3 to i + 47 i = 0 to 255 i + 3 to i + 108 i + 3 to i + 134 ∗1 Output line is Up to 258 lines. The i + 1 and i + 2 line signals may be disrupted by elimination of the picture top, so these lines should not be used. For example, if the picture top is eliminated with i = 100 in AF1 mode (NTSC), lines 103 to 208 in high frame rate readout mode are output from 26H of the timing chart. If the picture top is eliminated with i = 160 in AF1 mode (NTSC), lines 163 to 258 in high frame rate readout mode are output from 26H of the timing chart. – 12 – ICX252AQ Definition of standard imaging conditions 1) Standard imaging condition I: Use a pattern box (luminance: 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity. 2) Standard imaging condition II: Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. 3) Standard imaging condition III: Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens (exit pupil distance –33mm) with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. 1. G sensitivity, sensitivity comparison Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of 1/100s, measure the signal outputs (VGr, VGb, VR and VB) at the center of each Gr, Gb, R and B channel screen, and substitute the values into the following formulas. VG = (VGr + VGb)/2 Sg = VG × 100/30 [mV] Rr = VR/VG Rb = VB/VG 2. Saturation signal Set to standard imaging condition II. After adjusting the luminous intensity to 20 times the intensity with the average value of the Gr signal output, 150mV, measure the minimum values of the Gr, Gb, R and B signal outputs. 3. Smear Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, first adjust the average value of the Gr signal output to 150mV. Measure the average values of the Gr signal output, Gb signal output, R signal output and B signal output (Gra, Gba, Ra, Ba), and then adjust the luminous intensity to 500 times the intensity with the average value of the Gr signal output, 150mV. After the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value (VSm [mV]) independent of the Gr, Gb, R and B signal outputs, and substitute the values into the following formula. ( Sm = 20 × log Vsm ÷ Gra + Gba + Ra + Ba 1 1 × × 4 10 500 ) [dB] (1/10V method conversion value) 4. Video signal shading Set to standard imaging condition III. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so that the average value of the Gr signal output is 150mV. Then measure the maximum (Grmax [mV]) and minimum (Grmin [mV]) values of the Gr signal output and substitute the values into the following formula. SHg = (Grmax – Grmin)/150 × 100 [%] – 13 – ICX252AQ 5. Dark signal Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60°C and the device in the light-obstructed state, using the horizontal idle transfer level as a reference. 6. Dark signal shading After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark signal output and substitute the values into the following formula. ∆Vdt = Vdmax – Vdmin [mV] 7. Line crawl Set to standard imaging condition II. Adjusting the luminous intensity so that the average value of the Gr signal output is 150mV, and then insert R, G and B filters and measure the difference between G signal lines (∆Glr, ∆Glg, ∆Glb [mV]) as well as the average value of the G signal output (Gar, Gag, Gab). Substitute the values into the following formula. Lci = ∆Gli × 100 [%] (i = r, g, b) Gai 8. Lag Adjust the Gr signal output value generated by strobe light to 150mV. After setting the strobe light so that it strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following formula. Lag = (Vlag/150) × 100 [%] VD V1A/V1B Strobe light timing Gr signal output 150mV Output – 14 – Vlag (leg) ICX252AQ –7.5V Drive Circuit 15V 3.3V 100k 0.1 1/35V 1 20 XSUB 2 19 XV3 3 18 XSG3B 4 17 XSG3A 5 XV1 6 15 XSG1B 7 14 XSG1A 8 13 XV4 9 12 XV2 10 11 0.1 16 CXD3400N 0.1 47 3 4 5 6 7 8 9 10 Vφ4 Vφ3B Vφ2 Vφ1A Vφ1B TEST TEST VOUT GND 2 Vφ3A 2SK1875 1 CCD OUT 1.8k ICX252 (BOTTOM VIEW) VDD Hφ2 φRG GND 3.3/20V Hφ1 φSUB CSUB VL VSUB Cont. Hφ1 Hφ2 VR1 (1.3k) 0.01 20 19 18 17 16 15 14 13 12 11 Hφ2 Hφ1 φRG 0.1 0.1 1M Substrate bias control signal VSUB Cont. Substrate bias φSUB pin voltage Mechanical shutter mode tf ≈ 10ms tr ≈ 2ms GND Internally generated value VSUB 0.1 3.3/16V 2200p Notes) Substrate bias control 1. The saturation signal level decreases when exposure is performed using the mechanical shutter, so control the substrate bias. 2. A saturation signal level equivalent to that for continuous exposure can be assured by connecting a 1.3kΩ grounding resistor to the CCD CSUB pin. Drive timing precautions 1. Blooming occurs in modes (high frame rate readout, etc.) that do not use the mechanical shutter, so do not ground the connected 1.3kΩ resistor. 2. tf is slow, so the internally generated voltage VSUB may not drop to a sufficiently low level if the substrate bias control signal is not set to high level 40ms before entering the exposure period and the 1.3kΩ resistor connected to the CSUB pin is not grounded. 3. The blooming signal generated during exposure in mechanical shutter mode is swept by providing one field or more of idle transfer through vertical register high-speed sweep transfer from the time the mechanical shutter closes until sensor readout is performed. However, note that the VL potential and the φSUB pin DC voltage sag at this time. – 15 – – 16 – CCD OUT VSUB Cont. Mechanical shutter TRG SUB V4 V3B V3A V2 V1B V1A VD Act. B OPEN B C Exposure operation Note) The B output signal contains a blooming component and should therefore not be used. C output signal (ODD) CLOSE C output signal (EVEN) Frame readout mode E Output after frame readout D output signal E output signal OPEN D High frame rate readout mode High Frame Rate Readout Mode → Frame Readout Mode/Electronic Shutter Normal Operation A output signal A output signal B output signal B output signal A High frame rate readout mode Drive Timing Chart (Vertical Sequence) ICX252AQ – 17 – CCD OUT VSUB Cont. Mechanical shutter TRG SUB V4 V3A/B V2 30 31 30 31 27 27 9 10 9 10 1 1 NTSC PAL CLOSE Note) 2288fH, However, 919H and 1828H in NTSC mode are 1716 clk, and 944H, 945H, 1889H and 1890H in PAL mode are 1208 clk. OPEN 35 35 “b” 810 810 “c” 919 920 945 946 “a” 928 929 953 954 “c” 946 972 1 3 5 7 1 3 5 7 9 11 V1A/B 948 974 HD 950 976 VD All pixel output period 954 980 2 4 6 8 2 4 6 8 10 12 1729 1755 Exposure period 1548 1550 1838 1 1890 1 NTSC/PAL Frame Readout Mode NTSC: 4.28 frame/s, PAL: 4.17 frame/s 1547 1549 Drive Timing Chart (Vertical Sync) OPEN ICX252AQ – 18 – V4 V3A/B V2 V1A/B H1 “b” Enlarged V4 V3A/B V2 V1A/B NTSC: #948 PAL : #974 172 181 241 211 1130 1100 172 52 52 2288 1 2288 1 1190 1160 1250 1280 1310 1 1 H1 NTSC: #30 PAL : #30 2288 2288 “a” Enlarged 52 52 NTSC/PAL Frame Readout Mode NTSC: #949 PAL : #975 NTSC: #31 PAL : #31 172 172 Drive Timing Chart (Readout) ICX252AQ – 19 – V4 V3A/B V2 V1A/B HD “c” Enlarged 1 52 #1 #2 #3 #4 19 10 19 10 19 10 19 10 19 10 19 10 19 10 19 10 Drive Timing Chart (High-speed Sweep Operation) 61776 clk = 27 lines NTSC/PAL Frame Readout Mode #1038 19 10 19 10 52 ICX252AQ – 20 – SUB H2 H1 V4 V3A/B V2 V1A/B SHD SHP RG CLK 18 1 38 1 47 1 40 1 76 1 68 1 49 1 67 1 1 1 1 1 1 18 1 52 48 1 34 15 44 24 62 172 120 1 4 1 5 1 2288 Ignored pixel 4 bits 200 28 Ignored pixel 4 bits NTSC/PAL Frame Readout Mode 209 Drive Timing Chart (Horizontal Sync) ICX252AQ CCD OUT V4 V3B V3A V2 V1B V1A PAL "d" NTSC "d" 255 255 HD 260 260 NTSC/PAL High Frame Rate Readout Mode NTSC: 30 frame/s, PAL: 25 frame/s 263 1 315 1 Note) 2288fH, However, 263H in NTSC mode is 1144 clk, and 315H in PAL mode is 1568 clk. 1527 1534 1539 1546 9 10 9 10 1525 1532 1537 1544 1549 15 15 6 3 10 15 22 27 30 255 255 4 1 8 13 20 25 28 260 260 1527 1534 1539 1546 263 1 315 1 1525 1532 1537 1544 1549 9 10 9 10 6 3 10 15 22 27 30 – 21 – 4 1 8 13 20 25 28 15 15 VD Drive Timing Chart (Vertical Sync) ICX252AQ – 22 – V4 V3B V3A V2 V1B V1A NTSC 1144 PAL 1568 H1 “d” Enlarged #1 1010 1130 1190 1220 1270 1100 1160 1070 1040 1430 1400 1370 1340 1310 1280 1250 NTSC/PAL High Frame Rate Readout Mode 172 52 1 Drive Timing Chart (Readout) NTSC 2288 PAL 2288 #2 ICX252AQ 172 52 1 – 23 – SUB H2 H1 V4 V3A/B V2 V1A/B SHD SHP RG CLK 1 1 1 1 1 15 9 1 1 14 1 13 23 23 1 1 1 13 23 1 1 13 1 23 13 1 1 23 1 13 23 1 1 13 23 1 1 13 1 23 58 13 1 1 1 23 1 13 23 1 1 13 23 1 1 172 120 39 16 25 21 30 4 52 48 1 5 1 2288 Ignored pixel 4 bits 200 28 Ignored pixel 4 bits 1 NTSC/PAL High Frame Rate Readout Mode, AF1 Mode, AF2 Mode 209 Drive Timing Chart (Horizontal Sync) ICX252AQ CCD OUT V4 V3B V3A V2 V1B 158 132 1 1 "e" "d" Frame shift period 13H AF mode output signal Note) 2288fH, However, 182H in NTSC mode is 572 clk, and 158H in PAL mode is 784 clk. High-speed sweep period 7H (138 lines) "f" 9 10 9 10 "f" "d" 6 V1A PAL 23 23 4 NTSC 26 26 HD 158 132 1 1 6 – 24 – 4 VD "e" 9 10 9 10 NTSC/PAL AF1 Mode NTSC: 60 frame/s, PAL: 50 frame/s 15 15 Drive Timing Chart (Vertical Sync) ICX252AQ CCD OUT V4 V3B V3A V2 V1B Frame shift period 13H AF mode output line "f" "d" "e" 66 1 79 1 Note) 2288fH, However, 66H in NTSC mode is 1430 clk, and 79H in PAL mode is 1356 clk. 6 4 V1A "e" 9 10 9 10 PAL "d" 27 27 NTSC "f" 30 30 High-speed sweep period 7H (208 lines) 66 1 79 1 HD 9 10 9 10 6 – 25 – 4 VD NTSC/PAL AF2 Mode NTSC: 120 frame/s, PAL: 100 frame/s 27 27 Drive Timing Chart (Vertical Sync) ICX252AQ – 26 – V4 V3A/B V2 V1A/B HD “e” Enlarged 1 #1 13 23 13 23 13 23 13 23 13 23 13 23 13 23 13 23 13 23 66 13 23 13 23 13 23 57 61 52 #2 13H Drive Timing Chart (High-speed Frame Shift Operation) NTSC/PAL AF1 Mode, AF2 Mode i = 0 to 255 52 ICX252AQ – 27 – V4 V3A/B V2 V1A/B HD “ f ” Enlarged 1 #1 13 23 13 23 13 23 13 23 13 23 13 23 13 23 13 23 13 23 66 13 23 13 23 13 23 57 61 52 NTSC/PAL AF1 Mode, AF2 Mode #2 AF1 mode: 7H, AF2 mode: 11H Drive Timing Chart (High-speed Sweep Operation) AF1 mode: #138 AF2 mode: #208 52 ICX252AQ ICX252AQ Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensors. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, use a thermal controller of the zero-cross On/Off type and connect it to ground. 3) Dust and dirt protection Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. Clean glass plates with the following operations as required, and use them. a) Perform all assembly operations in a clean room (class 1000 or less). b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. e) When a protective tape is applied before shipping, just before use remove the tape applied for electrostatic protection. Do not reuse the tape. 4) Installing (attaching) a) Remain within the following limits when applying a static load to the package. Do not apply any load more than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited portions. (This may cause cracks in the package.) AAAA AAAA AAAA AAAA Cover glass 50N 50N Plastic package Compressive strength AAAA AAAA 1.2Nm Torsional strength b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the bottom of the package. Therefore, for installation, use either an elastic load, such as a spring plate, or an adhesive. – 28 – ICX252AQ c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area, and indicated values should be transferred to other locations as a precaution. d) The notch of the package is used for directional index, and that can not be used for reference of fixing. In addition, the cover glass and seal resin may overlap with the notch of the package. e) If the leads are bent repeatedly and metal, etc., clash or rub against the package, the dust may be generated by the fragments of resin. f) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyanoacrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference) 5) Others a) Do not expose to strong light (sun rays) for long periods, as color filters will be discolored. When high luminous objects are imaged with the exposure level controlled by the electronic iris, the luminance of the image-plane may become excessive and discoloring of the color filter will possibly be accelerated. In such a case, it is advisable that taking-lens with the automatic-iris and closing of the shutter during the poweroff mode should be properly arranged. For continuous using under cruel condition exceeding the normal using condition, consult our company. b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. c) Brown stains may be seen on the bottom or side of the package. But this does not affect the CCD characteristics. – 29 – B 2.5 0.5 2.5 9.0 ~ ~ DRAWING NUMBER PACKAGE MASS LEAD MATERIAL LEAD TREATMENT PACKAGE MATERIAL 12.7 0.3 M 10.0 13.8 ± 0.1 H 6.9 AS-B6-01(E) 0.95g 42 ALLOY GOLD PLATING Plastic 1 V 20 1.27 PACKAGE STRUCTURE 0.8 6.0 ~ 2.5 10 11 A 0.3 D 20pin DIP 10.9 0.8 Unit: mm B' 12.0 ± 0.1 0.5 2.4 – 30 – 2.9 ± 0.15 3.5 ± 0.3 C 0° to 9° 1.7 10 11 1.7 1.7 12.2 1 20 1.7 9. The notches on the bottom of the package are used only for directional index, they must not be used for reference of fixing. 8. The thickness of the cover glass is 0.5mm, and the refractive index is 1.5. 7. The tilt of the effective image area relative to the bottom “C” is less than 50µm. The tilt of the effective image area relative to the top “D” of the cover glass is less than 50µm. 6. The height from the bottom “C” to the effective image area is 1.41 ± 0.10mm. The height from the top of the cover glass “D” to the effective image area is 1.49 ± 0.15mm. 5. The rotation angle of the effective image area relative to H and V is ± 1°. 4. The center of the effective image area relative to “B” and “B'” is (H, V) = (6.9, 6.0) ± 0.15mm. 3. The bottom “C” of the package, and the top of the cover glass “D” are the height reference. 2. The two points “B” of the package are the horizontal reference. The point “B'” of the package is the vertical reference. 1. “A” is the center of the effective image area. 0.25 Package Outline ICX252AQ