IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • • • • The IDT54/74FCT273T/AT/CT are octal D flip-flops built using an advanced dual metal CMOS technology. The IDT54/ 74FCT273T/AT/CT have eight edge-triggered D-type flipflops with individual D inputs and O outputs. The common buffered Clock (CP) and Master Reset ( ) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s O output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. • • • • • Std., A, and C speed grades Low input and output leakage ≤1µA (max.) CMOS power levels True TTL input and output compatibility – VOH = 3.3V (typ.) – VOL = 0.3V (typ.) High drive outputs (-15mA IOH, 48mA IOL) Meets or exceeds JEDEC standard 18 specifications Product available in Radiation Tolerant and Radiation Enhanced versions Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) Available in DIP, SOIC, QSOP, CERPACK and LCC packages MR MR FUNCTIONAL BLOCK DIAGRAM D0 D1 D2 D3 D4 D5 D6 D7 CP D Q D CP Q D CP RD Q D CP RD Q D CP RD Q D CP RD Q D CP RD Q D CP RD Q CP RD RD MR O0 O1 O2 O3 O4 O5 O6 O7 2568 drw 03 2 3 19 O7 18 D7 17 D6 D1 4 O6 O5 O1 5 O2 6 14 D5 7 13 D4 D2 D3 O4 CP O1 5 O2 6 P20-1 D20-1 SO20-2 SO20-8 & E20-1 16 15 D2 7 D3 8 O3 GND 9 12 10 11 3 2 1 20 19 18 D7 17 D6 16 O6 15 O5 14 D5 L20-2 8 9 10 11 12 13 2568 drw 01 DIP/SOIC/QSOP/CERPACK TOP VIEW CP O4 D4 4 VCC O0 20 D0 D0 D1 INDEX 1 O3 GND MR O0 MR VCC O7 PIN CONFIGURATIONS 2568 drw 02 LCC TOP VIEW The IDT logo is a registered trademark of Integrated Device Technology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES 1995 Integrated Device Technology, Inc. 6.10 APRIL 1995 DSC-4209/3 1 IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND COMMERCIAL TEMPERATURE RANGES FUNCTION TABLE(1) PIN DESCRIPTION Pin Names DN Description Data Inputs MR Master Reset (Active LOW) CP Clock Pulse Input (Active Rising Edge) ON Data Outputs 2568 tbl 01 ABSOLUTE MAXIMUM RATINGS(1) Military –0.5 to +7.0 Unit V –0.5 to VCC +0.5 V –55 to +125 °C –65 to +135 °C –65 to +150 °C 0.5 W I OUT –60 to +120 mA –60 to +120 MR DN Outputs ON Reset (Clear) L X X L Load "1" H ↑ h H Load "0" H ↑ I L NOTE: 2568 tbl 02 1. H = HIGH voltage level steady state h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition L = LOW voltage level steady state I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition X = Don’t Care ↑ = LOW-to-HIGH Clock Transition CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol Rating Commercial VTERM(2) Terminal Voltage –0.5 to +7.0 with Respect to GND VTERM(3) Terminal Voltage –0.5 to with Respect to VCC +0.5 GND TA Operating 0 to +70 Temperature TBIAS Temperature –55 to +125 Under Bias TSTG Storage –55 to +125 Temperature PT Power Dissipation 0.5 DC Output Current Operating Mode Inputs CP Symbol Parameter(1) CIN Input Capacitance COUT Output Capacitance Conditions VIN = 0V Typ. 6 VOUT = 0V 8 Max. Unit 10 pF 12 NOTE: 1. This parameter is measured at characterization but not tested. pF 2568 lnk 04 2568 lnk 03 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed VCC by +0.5V unless otherwise noted. 2. Input and VCC terminals only. 3. Outputs and I/O terminals only. 6.10 2 IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10% Parameter Input HIGH Level Test Conditions(1) Guaranteed Logic HIGH Level VIL Input LOW Level II H Input HIGH Current (4) II L Input LOW Current (4) Symbol VIH Current (4) Min. 2.0 Typ.(2) — Max. — Guaranteed Logic LOW Level — — 0.8 V VCC = Max. VI = 2.7V — — ±1 µA VCC = Max. VI = 0.5V — — ±1 µA — — ±1 µA II Input HIGH VIK Clamp Diode Voltage VCC = Min., IN = –18mA IOS Short Circuit Current VCC = Max.(3) , VO = GND VOH Output HIGH Voltage VCC = Min. VIN = VIH or VIL VOL Output LOW Voltage VH Input Hysteresis ICC Quiescent Power Supply Current VCC = Max., VI = VCC (Max.) IOH = –6mA MIL. IOH = –8mA COM'L. IOH = –12mA MIL. IOH = –15mA COM'L. IOL = 32mA MIL. IOL = 48mA COM'L. VCC = Min. VIN = VIH or VIL — VCC = Max. VIN = GND or VCC — –0.7 –1.2 V –60 –120 –225 mA 2.4 3.3 — V 2.0 3.0 — V — 0.3 0.5 V — 200 — mV — 0.01 1 mA NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. 4. The test parameter for this parameter is ±5µA at TA = -55°C. 6.10 Unit V 2568 tbl 05 3 IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND COMMERCIAL TEMPERATURE RANGES POWER SUPPLY CHARACTERISTICS Symbol ∆ICC ICCD IC Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Total Power Supply Current (6) Test Conditions(1) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open MR = VCC One Input Toggling 50% Duty Cycle VCC = Max. Outputs Open fCP= 10MHz 50% Duty Cycle MR = VCC One Bit Toggling at fi = 5MHz 50% Duty Cycle VCC = Max. Outputs Open fCP= 10MHz 50% Duty Cycle MR = VCC Eight Bits Toggling at fi = 2.5MHz 50% Duty Cycle Min. Typ.(2) Max. Unit — 0.5 2.0 mA VIN = VCC VIN = GND — 0.15 0.25 mA/ MHz VIN = VCC VIN = GND — 1.5 3.5 mA VIN = 3.4V VIN = GND — 2.0 5.5 VIN = VCC VIN = GND — 3.8 7.3 5) VIN = 3.4V VIN = GND — 6.0 16.3 (5) NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi) ICC = Quiescent Current ∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz. 6.10 2568 tbl 06 4 IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND COMMERCIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS OVER OPERATING RANGE IDT54/74FCT273T Com'l. Symbol Parameter tPLH Propagation Delay CP to ON tPHL tPHL tSU tH tW tW tREM Propagation Delay MR to ON Set-up Time HIGH or LOW DN to CP Hold Time HIGH or LOW DN to CP CP Pulse Width HIGH or LOW MR Pulse Width LOW Recovery Time MR to CP Condition(1) CL = 50pF (2) Min. Mil. (2) Max. Min. IDT54/74FCT273AT Com'l. (2) Max. Min. Mil. (2) IDT54/74FCT273CT Com'l. (2) Max. Min. Max. Min. Mil. Max. Min. (2) Max. Unit 2.0 13.0 2.0 15.0 2.0 7.2 2.0 8.3 2.0 5.8 2.0 6.5 ns 2.0 13.0 2.0 15.0 2.0 7.2 2.0 8.3 2.0 6.1 2.0 6.8 ns 3.0 — 3.5 — 2.0 — 2.0 — 2.0 — 2.0 — ns 2.0 — 2.0 — 1.5 — 1.5 — 1.5 — 1.5 — ns 7.0 — 7.0 — 6.0 — 6.0 — 6.0 — 6.0 — ns 7.0 — 7.0 — 6.0 — 6.0 — 6.0 — 6.0 — ns 4.0 — 5.0 — 2.0 — 2.5 — 2.0 — 2.5 — ns RL = 500Ω NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 2568 tbl 07 6.10 5 IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND COMMERCIAL TEMPERATURE RANGES TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS SWITCH POSITION V CC 7.0V 500Ω Pulse Generator Switch Open Drain Disable Low Closed Enable Low V OUT VIN Test Open All Other Tests D.U.T. 50pF RT 2568 lnk 08 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 500Ω CL 2568 drw 04 SET-UP, HOLD AND RELEASE TIMES DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tH tSU tREM tSU PULSE WIDTH 3V 1.5V 0V 3V 1.5V 0V LOW-HIGH-LOW PULSE 1.5V tW 3V 1.5V 0V HIGH-LOW-HIGH PULSE 1.5V 2568 drw 06 3V 1.5V 0V tH 2568 drw 05 PROPAGATION DELAY ENABLE AND DISABLE TIMES ENABLE SAME PHASE INPUT TRANSITION tPLH tPHL OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL 3V 1.5V 0V VOH 1.5V VOL DISABLE 3V CONTROL INPUT 1.5V OUTPUT NORMALLY LOW 3V 1.5V 0V SWITCH CLOSED 3.5V 1.5V tPZH OUTPUT NORMALLY HIGH 2568 drw 07 SWITCH OPEN 0V tPLZ tPZL 3.5V 0.3V VOL tPHZ 0.3V VOH 1.5V 0V 0V 2568 drw 08 NOTES: 1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns 6.10 6 IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDTXX Temp. Range FCT X Family XXXX X X Device Type Package Process Blank B Commercial MIL-STD-883, Class B P D SO L E Q Plastic DIP CERDIP Small Outline IC Leadless Chip Carrier CERPACK Quarter-size Small Outline Package 273T 273AT 273CT Octal D Flip-Flop w/Clear Blank High Drive 54 74 –55°C to +125°C 0°C to +70°C 2568 drw 09 6.10 7