IDT6167SA IDT6167LA CMOS STATIC RAM 16K (16K x 1-BIT) Integrated Device Technology, Inc. FEATURES: • High-speed (equal access and cycle time) — Military: 15/20/25/35/45/55/70/85/100ns (max.) — Commercial: 15/20/25/35ns (max.) • Low power consumption • Battery backup operation — 2V data retention voltage (IDT6167LA only) • Available in 20-pin CERDIP and Plastic DIP, and 20-pin SOJ • Produced with advanced CMOS high-performance technology • CMOS process virtually eliminates alpha particle softerror rates • Separate data input and output • Military product compliant to MIL-STD-883, Class B DESCRIPTION: The lDT6167 is a 16,384-bit high-speed static RAM organized as 16K x 1. The part is fabricated using IDT’s highperformance, high reliability CMOS technology. Access times as fast as 15ns are available. The circuit also offers a reduced power standby mode. When CS goes HIGH, the circuit will automatically go to, and remain in, a standby mode as long as CS remains HIGH. This capability provides significant system-level power and cooling savings. The lowpower (LA) version also offers a battery backup data retention capability where the circuit typically consumes only 1µW operating off a 2V battery. All inputs and the output of the IDT6167 are TTL-compatible and operate from a single 5V supply, thus simplifying system designs. The IDT6167 is packaged in a space-saving 20-pin, 300 mil Plastic DIP or CERDIP, Plastic 20-pin SOJ, providing high board-level packing densities. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. FUNCTIONAL BLOCK DIAGRAM A0 VCC GND 16,384-BIT MEMORY ARRAY ADDRESS DECODE A13 DIN CS WE I/O CONTROL DOUT CONTROL LOGIC 2981 drw 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES 1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. 5.2 MARCH 1996 2981/5 1 IDT6167SA/LA CMOS STATIC RAM 16K (16K x 1-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATIONS Symbol A0 1 20 VCC A1 2 19 A13 A2 3 18 A12 A3 4 D20-1, 17 A11 A4 5 & 16 A10 A5 6 S020-1 15 A9 A6 7 14 A8 DOUT 8 13 WE A7 9 12 DIN 10 11 CS GND P20-1, Mil. Unit –0.5 to +7.0 –0.5 to +7.0 V Terminal Voltage with Respect to GND TA Operating Temperature 0 to +70 –55 to +125 °C TBIAS Temperature Under Bias –55 to +125 –65 to +135 °C TSTG Storage Temperature –55 to +125 –65 to +150 °C PT Power Dissipation 1.0 1.0 W IOUT DC Output Current 50 50 mA NOTE: 2981 tbl 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DIP/SOJ TOP VIEW PIN DESCRIPTIONS Address Inputs CS WE Com’l. VTERM 2981 drw 02 A0–A13 Rating Chip Select Write Enable VCC Power DIN DATAIN DOUT DATAOUT GND Ground CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol Parameter(1) Conditions Max. Unit 2981 tbl 01 CIN Input Capacitance COUT Output Capacitance Mode CS WE Output Power Standby H X High-Z Standby Read L H DATAOUT Active Write L L High-Z Active NOTE: 1. H = VIH, L = VIL, X = Don't Care. VOUT = 0V 7 pF RECOMMENDED DC OPERATING CONDITIONS RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Commercial pF 2981 tbl 02 Symbol Military 7 NOTE: 2981 tbl 04 1. This parameter is determined by device characterization, but is not production tested. TRUTH TABLE (1) Grade VIN = 0V Parameter Min. Typ. VCC Supply Voltage 4.5 5.0 5.5 V GND Supply Voltage 0 0 0 V VIH Input High Voltage — 6.0 V — 0.8 V VIL Temperature GND VCC –55°C to +125°C 0V 5V ± 10% 0°C to +70°C 0V 5V ± 10% Input Low Voltage 2.2 –0.5 (1) Max. Unit NOTE: 2981 tbl 05 1. VIL (min.) = –3.0V for pulse width less than 20ns, once per cycle. 2981 tbl 06 5.2 2 IDT6167SA/LA CMOS STATIC RAM 16K (16K x 1-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS(1) (VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC – 0.2V) 6167SA/LA15 Symbol ICC1 ICC2 ISB ISB1 Parameter Power Com’l. 6167SA/LA20 6167SA/LA25 Mil. Com’l. Mil. Com’l. Mil. Unit mA Operating Power Supply Current CS ≤ VIL, Outputs Open, VCC = Max., f = 0(3) SA 90 90 90 90 90 90 LA 55 60 55 60 55 60 Dynamic Operating Current CS ≤ VIL, Outputs Open, VCC = Max., f = fMAX(3) SA 120 130 100 110 100 100 LA 100 110 80 85 70 75 Standby Power Supply Current (TTL Level) CS ≥ VIH, Outputs Open, VCC = Max., f = fMAX(3) SA 50 50 35 35 35 35 LA 35 35 30 30 25 25 Full Standby Power Supply Current (CMOS Level) CS ≥ VHC, VCC = Max. VIN ≥ VHC or VIN ≤ VLC, f = 0(3) SA 5 10 5 10 5 10 LA 0.9 2 0.05 2 0.05 0.9 mA mA mA DC ELECTRICAL CHARACTERISTICS(1) (CONTINUED) (VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC – 0.2V) 6167SA/LA35 6167SA/LA45(2) 6167SA/LA55(2) 6167SA/LA70(2) Symbol Parameter Power Com’l. Com’l. Mil. Com’l. Mil. Com’l. Mil. Unit 90 — 90 — 90 — 90 mA ICC1 Operating Power Supply Current CS ≤ VIL, Outputs Open, VCC = Max., f = 0(3) SA LA 55 60 — 60 — 60 — 60 ICC2 Dynamic Operating Current CS ≤ VIL, Outputs Open, VCC = Max., f = fMAX(3) SA 100 100 — 100 — 100 — 100 LA 65 70 — 65 — 60 — 60 ISB Standby Power Supply Current (TTL Level) CS ≥ VIH, Outputs Open, VCC = Max., f = fMAX(3) SA 35 35 — 35 — 35 — 35 LA 20 20 — 20 — 20 — 15 Full Standby Power Supply Current (CMOS Level) CS ≥ VHC, VCC = Max. VIN ≥ VHC or VIN ≤ VLC, f = 0(3) SA 5 10 — 10 — 10 — 10 LA 0.05 0.9 — 0.9 — 0.9 — 0.9 ISB1 90 Mil. NOTES: 1. All values are maximum guaranteed values. 2. –55°C to +125°C temperature range only. Also available; 85ns and 100ns Military devices. 3. fMAX = 1/tRC, only address inputs cycling at fMAX. f = 0 means no Address inputs change. 5.2 mA mA mA 2981 tbl 07 3 IDT6167SA/LA CMOS STATIC RAM 16K (16K x 1-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS VCC = 5.0V ± 10% IDT6167SA Symbol |ILI| Parameter Test Condition Input Leakage Current |ILO| Output Leakage Current Min. IDT6167LA Max. Min. Max. VCC = Max., MIL — 10 — 5 VIN = GND to VCC COM’L — 5 — 2 VCC = Max., CS = VIH, MIL — 10 — 5 VOUT = GND to VCC COM’L — 5 — 2 VOL Output Low Voltage IOL = 8mA, VCC = Min. — 0.4 — 0.4 VOH Output High Voltage IOH = –4mA, VCC = Min. 2.4 — 2.4 — Unit µA µA V V 2981 tbl 08 DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES (LA Version Only) VLC = 0.2V, VHC = VCC – 0.2V Typ. (1) VCC @ Symbol Parameter VDR VCC for Data Retention ICCDR Data Retention Current Test Condition — Chip Deselect to Data Retention Time tR(3) Operation Recovery Time |ILI| 3.0V 2.0V 3.0V Unit 2.0 — — — — V — 0.5 1.0 200 300 µA COM’L. — 0.5 1.0 20 30 0 — — — — ns tRC(2) — — — — ns — — — 2 2 µA VIN ≥ VHC or ≤ VLC Input Leakage Current 2.0v MIL. CS ≥ VHC tCDR (3) Min. Max. VCC @ — NOTES: 1. TA = +25°C. 2. tRC = Read Cycle Time. 3. This parameter is guaranteed by device characterization, but is not production tested. 2981 tbl 09 LOW VCC DATA RETENTION WAVEFORM DATA RETENTION MODE VCC 4.5V VDR ≥ 2V 4.5V tCDR CS tR VDR VIH VIH 2981 drw 03 5.2 4 IDT6167SA/LA CMOS STATIC RAM 16K (16K x 1-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise/Fall Times 5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V AC Test Load See Figures 1 and 2 2981 tbl 10 5V 5V 480Ω 480Ω DATAOUT DATAOUT 255Ω 255Ω 30pF* 5pF* 2981 drw 04 2981 drw 05 Figure 2. AC Test Load (for tCLZ, tCHZ, tWHZ and tOW) Figure 1. AC Test Load *Includes scope and jig. AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges) 6167SA15 6167LA15 Symbol Parameter Min. Max. 6167SA20/25 6167SA35/45(1) 6167SA55(1)/70(1) 6167LA20/25 6167LA35/45(1) 6167LA55(1)/70(1) Min. Max. Min. Max. Min. Max. Unit Read Cycle tRC Read Cycle Time 15 — 20/25 — 35/45 — 55/70 — ns tAA Address Access Time — 15 — 20/25 — 35/45 — 55/70 ns tACS Chip Select Access Time — 15 — 20/25 — 35/45 — 55/70 ns (2) Chip Deselect to Output in Low-Z 3 — 5/5 — 5/5 — 5/5 — ns (2) tCLZ tCHZ Chip Select to Output in High-Z — 10 — 10/10 — 15/30 — 40/40 ns tOH Output Hold from Address Change 3 — 5/5 — 5/5 — 5/5 — ns tPU(2) Chip Select to Power-Up Time 0 — 0/0 — 0/0 — 0/0 — ns Chip Deselect to Power-Down Time — 15 — 20/25 — 35/45 — 55/70 ns tPD (2) Write Cycle tWC Write Cycle Time 15 — 20/20 — 30/45 — 55/70 — ns tCW Chip Select to End-of-Write 15 — 15/20 — 30/40 — 45/55 — ns tAW Address Valid to End-of-Write 15 — 15/20 — 30/40 — 45/55 — ns tAS Address Set-up Time 0 — 0/0 — 0/0 — 0/0 — ns tWP Write Pulse Width 13 — 15/20 — 30/30 — 35/40 — ns tWR Write Recovery Time 0 — 0/0 — 0/0 — 0/0 — ns tDW Data Valid to End-of-Write 10 — 12/15 — 17/20 — 25/30 — ns tDH Data Hold Time 0 — 0/0 — 0/0 — 0/0 — ns tWHZ(2) Write Enable to Output in High-Z — 7 — 8/8 — 15/30 — 40/40 ns tOW(2) Output Active from End-of-Write 0 — 0/0 — 0/0 — 0/0 — NOTES: 1. –55°C to +125°C temperature range only. Also available: 85ns and 100ns Military devices. 2. This parameter is guaranteed with AC Load (Figure 2) by device characterization, but is not production tested. 5.2 ns 2981 tbl 11 5 IDT6167SA/LA CMOS STATIC RAM 16K (16K x 1-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF READ CYCLE NO. 1(1, 2) tRC ADDRESS tAA tOH PREVIOUS DATAOUT VALID DATAOUT DATAOUT VALID 2981 drw 06 TIMING WAVEFORM OF READ CYCLE NO. 2(1, 3) tRC CS tACS tCLZ DATAOUT tCHZ (4) (4) HIGH IMPEDANCE DATAOUT VALID tPU HIGH IMPEDANCE tPD ICC VCC SUPPLY CURRENT ISB 2981 drw 07 NOTES: 1. WE is HIGH for Read cycle. 2. Device is continuously selected, CS is LOW. 3. Address valid prior to or coincedent with CS transition LOW. 4. Transition is measured ±200mV from steady state. 5.2 6 IDT6167SA/LA CMOS STATIC RAM 16K (16K x 1-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF WRITE CYCLE NO. 1, (WE CONTROLLED TIMING)(1, 2, 4) tWC ADDRESS tAW CS tAS tCHZ (3) tWR tWP (5) WE tWHZ DATAOUT PREVIOUS DATAOUT VALID (5) tOW (5) (6) DATAOUT VALID (6) tDW DATAIN tDH DATAIN VALID 2981 drw 08 TIMING WAVEFORM OF WRITE CYCLE NO. 2, (CS CONTROLLED TIMING)(1, 2, 4) tWC ADDRESS tAW CS tAS tWR (3) tCW WE tDW DATAIN tDH DATAIN VALID 2981 drw 09 NOTES: 1. WE or CS must be inactive during all address transitions. 2. A write occurs during the overlap of a LOW CS and a LOW WE. 3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle. 4. If the CS low transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state. 5. Transition is measured ±200mV from steady state. 6. During this period, the I/O pins are in the output state and the input signals must not be applied. 5.2 7 IDT6167SA/LA CMOS STATIC RAM 16K (16K x 1-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDT 6167 XX XXX XX X Device Type Power Speed Package Process/ Temperature Range 5.2 Blank Commercial (0°C to +70°C) B Military (–55°C to +125°C) Compliant to MIL-STD-883, Class B P D Y 300MIL Plastic DIP (P20–1) 300MIL CERDIP (D20–1) 300MIL SOJ (SO20–1) 15 20 25 35 45 55 70 85 100 Military Only Military Only Military Only Military Only Military Only SA LA Standard Power Low Power Speed in nanoseconds 2981 drw 10 8