HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM IDT70V24S/L Integrated Device Technology, Inc. FEATURES: • True Dual-Ported memory cells which allow simultaneous access of the same memory location • High-speed access — Commercial: 25/35/55ns (max.) • Low-power operation — IDT70V24S Active: 230mW (typ.) Standby: 3.3mW (typ.) — IDT70V24L Active: 230mW (typ.) Standby: .66mW (typ.) • Separate upper-byte and lower-byte control for multiplexed bus compatibility • IDT70V24 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device • M/S = H for BUSY output flag on Master M/S = L for BUSY input on Slave • Busy and Interrupt Flags • Devices are capable of withstanding greater than 2001V electrostatic charge. • On-chip port arbitration logic • Full on-chip hardware support of semaphore signaling between ports • Fully asynchronous operation from either port • LVTTL-compatible, single 3.3V (±0.3V) power supply • Available in 84-pin PGA, 84-pin PLCC, and 100-pin TQFP DESCRIPTION: The IDT70V24 is a high-speed 4K x 16 Dual-Port Static RAM. The IDT70V24 is designed to be used as a stand-alone 64K-bit Dual-Port RAM or as a combination MASTER/SLAVE FUNCTIONAL BLOCK DIAGRAM R/ WL R/ WR LBL CEL OEL LBR CE R OE R UBR UBL I/O8L-I/O 15L I/O Control I/O8R-I/O 15R I/O Control I/O0L-I/O 7L I/O0R-I/O 7R BUSYL(1,2) BUSYR(1,2) A11L A0L NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull. Address Decoder MEMORY ARRAY 12 CEL OEL R/ WL Address Decoder A11R A0R 12 ARBITRATION INTERRUPT SEMAPHORE LOGIC SEML INTL(2) CER OER R/ WR M/ S SEM R INTR(2) 2911 drw 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE ©1996 Integrated Device Technology, Inc. OCTOBER 1996 For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391. 6.38 DSC-2911/3 1 IDT70V24S/L HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 350mW of power. The IDT70V24 is packaged in a ceramic 84-pin PGA, an 84-Pin PLCC, and a 100-pin Thin Quad Plastic Flatpack. Dual-Port RAM for 32-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit or wider memory system applications results in full-speed, errorfree operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in 17 GND 18 69 68 19 I/O15L 20 VCC 21 GND 22 I/O0R 23 I/O1R 24 62 I/O2R 25 61 VCC 26 60 I/O3R 27 59 I/O4R 28 58 I/O5R 29 57 I/O6R 30 56 I/O7R 31 55 I/O8R 54 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 67 66 INTL 65 BUSYL 64 GND 63 M/S BUSYR INTR A0R A1R A2R A3R A4R A5R A6R 2911drw 02 N/C N/C N/C N/C I/O10L I/O11L I/O12L I/O13L GND I/O14L I/O15L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R N/C N/C N/C N/C NOTES: 1. All Vcc pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. This text does not indicate the actual part marking. OEL Index 1 10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 2 74 3 73 4 72 5 71 6 70 7 69 8 9 10 IDT70V24 PN100-1 11 12 13 100-PIN TQFP TOP VIEW(3) 14 15 16 17 18 68 67 66 65 64 63 62 61 60 59 58 57 56 55 21 54 22 53 23 52 24 51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 19 20 OER A7R A8R A9R A10R N/C A11R UBR LBR CER SEMR GND W R/ R OER I/O15R I/O14R GND I/O12R I/O13R I/O11R 84-PIN PLCC/ FLATPACK TOP VIEW (3) I/O10R I/O9R I/O14L I/O9L I/O8L I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L IDT70V24 J84-1 F84-2 N/C A11L A10L A9L A8L A7L A6L 70 I/O13L 6.38 N/C A11R A10R A9R A8R A7R A6R A5R 16 CEL 71 I/O12L UBL LBL 72 15 UBR LBR 14 I/O11L W I/O10L A7L A6L A5L A4L A3L A2L A1L A0L SEML 73 CER 13 SEMR I/O9L VCC R/ L 3 2 1 84 83 82 81 80 79 78 77 76 75 74 W 11 10 9 8 7 6 5 4 12 R/ R GND I/O8L I/O7R I/O8R I/O9R I/O10R I/O11R I/O12R I/O13R I/O14R GND I/O15R A9L A8L A11L A10L N/C UBL LBL CEL W R/ L SEML OEL VCC I/O0L GND I/O1L I/O3L I/O2L I/O4L I/O6L INDEX I/O5L I/O7L PIN CONFIGURATIONS (1,2) N/C N/C N/C N/C A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R N/C N/C N/C N/C 2911 drw 03 2 IDT70V24S/L HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATIONS (CONT'D) (1,2) 63 11 61 I/O7L 64 66 10 I/O10L CEL 52 45 A11L 44 N/C A9L 33 IDT70V24 G84-3 GND 32 84-PIN PGA TOP VIEW (3) 28 VCC 7 I/O7R 1 3 I/O8R A GND 2 I/O9R I/O10R 4 I/O11R B 11 I/O12R C 5 8 I/O13R I/O15R 6 9 I/O14R 12 GND 10 WR R/ 15 OER D E 14 A5R 17 UBR 13 LBR CER F G 22 20 A11R 16 A8R 18 N/C H J A3R 24 A6R 19 A10R A1R 25 23 SEMR BUSYR 27 A2R 83 A1L 30 INTR 26 I/O4R INTL 36 M/S 29 A0R A2L 34 A0L 31 GND A4L 37 35 BUSYL VCC A5L 39 A6L 80 I/O6R A8L 41 WL A7L 40 A3L 78 I/O2R I/O5R 42 A10L 43 R/ VCC 74 GND I/O3R 84 01 53 GND 47 50 UBL I/O1L 46 LBL 73 77 82 02 I/O3L 49 48 SEML 38 I/O14L I/O1R 81 03 56 57 70 79 04 I/O6L 51 OEL I/O12L I/O0R 76 05 59 54 I/O0L I/O9L 71 I/O15L 75 06 55 I/O2L 68 I/O13L 72 07 62 I/O8L I/O11L 69 08 58 I/O4L 65 67 09 60 I/O5L A4R 21 A9R A7R K L 2911 drw 04 Index NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. This text does not indicate the actual part-marking. PIN NAMES Left Port Right Port Names CEL R/WL OEL CER R/WR OER A0L – A11L A0R – A11R Address I/O0L – I/O15L I/O0R – I/O15R Data Input/Output SEML UBL LBL INTL BUSYL SEMR UBR LBR INTR BUSYR M/S Chip Enable Read/Write Enable Output Enable Semaphore Enable Upper Byte Select Lower Byte Select Interrupt Flag Busy Flag Master or Slave Select VCC Power GND Ground 2911 tbl 1 6.38 3 IDT70V24S/L HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE TRUTH TABLE I – NON-CONTENTION READ/WRITE CONTROL Inputs(1) Outputs CE R/W OE UB LB SEM I/O8-15 I/O0-7 H X X X X H High-Z High-Z Deselected: Power Down X X X H H H High-Z High-Z Both Bytes Deselected L L X L H H DATAIN High-Z Write to Upper Byte Only L L X H L H High-Z DATAIN Write to Lower Byte Only L L X L L H DATAIN DATAIN Write to Both Bytes L H L L H H DATAOUT High-Z Read Upper Byte Only L H L H L H L H L L L H X X H X X X High-Z Mode DATAOUT Read Lower Byte Only DATAOUT DATAOUT Read Both Bytes HighZ High-Z Outputs Disabled NOTE: 2911 tbl 02 1. A0L — A11L ≠ A0R — A11R. TRUTH TABLE II – SEMAPHORE READ/WRITE CONTROL(1) Inputs CE R/W OE H H L X H L X H UB Outputs LB SEM X X L DATAOUT DATAOUT Read Data in Semaphore Flag H H L DATAOUT DATAOUT Read Data in Semaphore Flag X X L DATAIN DATAIN Write DIN0 into Semaphore Flag Write DIN0 into Semaphore Flag I/O8-15 I/O0-7 Mode X H H L DATAIN DATAIN L X X L X L — — Not Allowed L X X X L L — — Not Allowed X NOTE: 2911 tbl 03 1. There are eight semaphore flags written to via I/O0 and read from all of the I/O's (I/O0 - I/O15). These eight semaphores are addressed by A0 - A2. ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM(2) Rating RECOMMENDED DC OPERATING CONDITIONS Commercial Unit Terminal Voltage with Respect to GND –0.5 to +4.6 Symbol V TA Operating Temperature 0 to +70 °C TBIAS Temperature Under Bias –55 to +125 °C TSTG Storage Temperature –55 to +125 °C IOUT DC Output Current 50 mA RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Ambient Temperature GND VCC Commercial 0°C to +70°C 0V 3.3V ± 0.3 Min. Typ. 3.0 3.3 VCC Supply Voltage GND Supply Voltage 0 0 VIH Input High Voltage 2.0 — VIL Input Low Voltage -0.3(1) — Max. Unit 3.6 V 0 V Vcc+0.3 V 0.8 NOTES: 1. VIL≥ -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 0.5V. NOTES: 2911 tbl 04 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc +0.5V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20ma for the period over VTERM > Vcc + 0.5V. Grade Parameter V 2911 tbl 06 CAPACITANCE(1) (TA = +25°C, F = 1.0MHZ) TQFP ONLY Symbol Parameter Conditions(2) Max. CIN Input Capacitance VIN = 3dV COUT Output Capacitance VOUT = 3dV Unit 9 pF 11 pF NOTES: 2911 tbl 07 1. This parameter is determined by device characterization but is not production tested. 2. 3dV references the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V. 2911 tbl 05 6.38 4 IDT70V24S/L HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 3.3V ± 0.3V) IDT70V24S Symbol Parameter IDT70V24L Test Conditions Min. Max. Min. Max. Unit |ILI| (1) Input Leakage Current VCC = 3.6V, VIN = 0V to VCC — 10 — 5 µA |ILO| Output Leakage Current CE = VIH, VOUT = 0V to VCC — 10 — 5 µA VOL Output Low Voltage IOL = 4mA — 0.4 — 0.4 V VOH Output High Voltage IOH = -4mA 2.4 — 2.4 — V NOTE: 1. At Vcc ≤ 2.0V input leakages are undefined. 2911 tbl 08 DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (VCC = 3.3V ± 0.3V) 70V24X25 Symbol Parameter Dynamic Operating ICC Current ISB1 ISB2 ISB3 (Both Ports Active) f = fMAX(3) Standby Current (Both Ports — TTL CER = CEL = VIH SEMR = SEML = VIH Level Inputs) f = fMAX(3) Standby Current CE"A"=VIL and CE"B"=VIH(5) (One Port — TTL Active Port Outputs Open Level Inputs) f = fMAX(3) Full Standby Current (Both Ports — All CMOS Level Inputs) ISB4 Test Condition CE = VIL, Outputs Open SEM = VIH Full Standby Current (One Port — All CMOS Level Inputs) SEMR = SEML = VIH Both Ports CEL and CER >VCC - 0.2V 70V24X35 S L Typ.(2) 80 80 Max. 140 120 COM. S L 12 10 25 20 10 8 25 20 10 8 25 20 mA COM. S 40 82 35 72 35 72 mA L 40 72 35 62 35 62 COM. S L 1.0 0.2 5 2.5 1.0 0.2 5 2.5 1.0 0.2 5 2.5 mA COM. S L 50 50 81 71 45 45 71 61 45 45 71 61 mA Version COM. Typ.(2) Max. 70 115 70 100 70V24X55 Typ.(2) Max. Unit 70 115 mA 70 100 VIN > VCC - 0.2V or VIN < 0.2V, f = 0(4) SEMR = SEML > VCC-0.2V CE"A" < 0.2 and CE"B" > VCC - 0.2V(5) SEMR = SEML > VCC-0.2V VIN > VCC - 0.2V or VIN < 0.2V, Active Port Outputs Open, f = fMAX(3) NOTES: 2911 tbl 09 1. "X" in part numbers indicates power rating (S or L). 2. VCC = 3.3V, TA = +25°C, and are not production tested. ICC DC = 70mA (typ.) 3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions” of input levels of GND to 3V. 4. f = 0 means no address or control lines change. 5. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 6.38 5 IDT70V24S/L HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise/Fall Times 5ns Max. Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load Figures 1 and 2 2911 tbl 10 3.3V 3.3V 590Ω 590Ω DATAOUT BUSY INT DATAOUT 435Ω 30pF 435Ω 5pF 2911 drw 05 Figure 1. Output Test Load (for tLZ, tHZ, tWZ, tOW) Figure 2. Output Test Load (for tLZ, tHZ, tWZ, tOW) * Including scope and jig. AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4) IDT70V24X25 Symbol Parameter IDT70V24X35 IDT70V24X55 Min. Max. Min. Max. Min. Max. Unit 25 — 35 — 55 — ns READ CYCLE tRC Read Cycle Time tAA Address Access Time — 25 — 35 — 55 ns tACE Chip Enable Access Time(3) — 25 — 35 — 55 ns tABE Byte Enable Access Time(3) — 25 — 35 — 55 ns tAOE Output Enable Access Time — 15 — 20 — 30 ns tOH Output Hold from Address Change 3 — 3 — 3 — ns (1, 2) 3 — 3 — 3 — ns (1, 2) — 15 — 20 — 25 ns 0 — 0 — 0 — ns tLZ Output Low-Z Time tHZ Output High-Z Time tPU Chip Enable to Power Up Time(2) (2) tPD Chip Disable to Power Down Time — 25 — 35 — 50 ns tSOP Semaphore Flag Update Pulse (OE or SEM) 15 — 15 — 15 — ns tSAA Semaphore Address Access Time — 35 — 45 — 65 NOTES: 1. Transition is measured ±200mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semaphore, CE = VIH or UB and LB = VIH, and SEM = VIL. 4. "X" in part numbers indicates power rating (S or L). ns 2911 tbl 11 TIMING OF POWER-UP POWER-DOWN CE ICC tPU tPD 50% 50% ISB 2911 drw 06 6.38 6 IDT70V24S/L HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE WAVEFORM OF READ CYCLES(5) tRC ADDR (4) tAA (4) tACE CE tAOE OE (4) tABE (4) , LB UB W R/ tOH (1) tLZ DATAOUT VALID DATA (4) tHZ (2) BUSYOUT tBDD (3, 4) 2911 drw 07 NOTES: 1. Timing depends on which signal is asserted last, OE, CE, LB, or UB. 2. Timing depends on which signal is de-asserted firs CE, OE, LB, or UB . 3. tBDD delay is required only in cases where opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBDD. 5. SEM = VIH. AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE(5) Symbol Parameter IDT70V24X25 IDT70V24X35 IDT70V24X55 Min. Min. Min. Max. Max. Max. Unit WRITE CYCLE tWC Write Cycle Time 25 — 35 — 55 — ns tEW Chip Enable to End-of-Write(3) 20 — 30 — 45 — ns tAW Address Valid to End-of-Write 20 — 30 — 45 — ns tAS Address Set-up Time(3) 0 — 0 — 0 — ns tWP Write Pulse Width 20 — 25 — 40 — ns tWR Write Recovery Time 0 — 0 — 0 — ns tDW Data Valid to End-of-Write 15 — 20 — 30 — ns (1, 2) tHZ Output High-Z Time — 15 — 20 — 25 ns tDH Data Hold Time(4) 0 — 0 — 0 — ns tWZ Write Enable to Output in High-Z(1, 2) — 15 — 20 — 25 ns (1, 2, 4) tOW Output Active from End-of-Write 0 — 0 — 0 — ns tSWRD SEM Flag Write to Read Time SEM Flag Contention Window 5 — 5 — 5 — ns 5 — 5 — 5 — ns tSPS NOTES: 2911 tbl 12 1. Transition is measured ±200mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. 4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 5. "X" in part numbers indicates power rating (S or L). 6.38 7 IDT70V24S/L HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W CONTROLLED TIMING(1,5,8) tWC ADDRESS tHZ (7) OE tAW CE or SEM UB or LB (9) (9) (3) tWP(2) tAS (6) tWR W R/ tWZ (7) DATAOUT tOW (4) (4) tDW tDH DATAIN 2911 drw 08 TIMING WAVEFORM OF WRITE CYCLE NO. 2, CE, UB, LB CONTROLLED TIMING(1,5) tWC ADDRESS tAW CE or SEM (9) (6) tAS tWR(3) tEW (2) UB or LB (9) R/ W tDW tDH DATAIN 2911 drw 09 NOTES: 1. R/W or CE or UB & LB must be High during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a Low UB or LB and a Low CE and a Low R/W for memory array writing cycle. 3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going High to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM Low transition occurs simultaneously with or after the R/W low transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE, R/W or byte control. 7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured ±200mV from Low or High-impedance voltage with Output Test Load (Figure 2). 8. If OE is Low during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is High during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 9. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. 6.38 8 IDT70V24S/L HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1) tOH tSAA A0-A2 SEM VALID ADDRESS tWR tAW tEW tACE tSOP tDW DATAIN VALID I/O0 W VALID ADDRESS tAS tWP DATAOUT VALID(2) tDH R/ tSWRD tAOE OE Write Cycle Read Cycle 2911 drw 10 NOTES: 1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle). 2. "DATAOUT VALID" represents all I/O's (I/O0-I/O15) equal to the semaphore value. TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4) A0"A"-A2"A" SIDE(2) “A” MATCH W"A" R/ SEM"A" tSPS A0"B"-A2"B" SIDE(2) “B” MATCH W"B" R/ SEM"B" 2911 drw 11 NOTES: 1. D0R = D0L = VIL, CER = CEL = VIH, or Both UB & LB = VIH Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start. 2. “A” may be either left or right port. “B” is the opposite port from “A”. 3. This parameter is measured from R/WA or SEMA going High to R/WB or SEMB going High. 4. If tSPS is not satisfied there is no guarantee which side will be granted the semaphore flag. 6.38 9 IDT70V24S/L HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6) Symbol Parameter IDT70V24X25 IDT70V24X35 IDT70V24X55 Min. Max. Min. Max. Min. Max. Unit — 25 — 35 — 45 ns BUSY TIMING (M/S = VIH) BUSY Access Time from Address Match BUSY Disable Time from Address Not Matched BUSY Access Time from Chip Low BUSY Disable Time from Chip High tBAA tBDA tBAC tBDC Arbitration Priority Set-up Time tAPS (2) BUSY Disable to Valid Data(3) Write Hold After BUSY(5) tWH BUSY TIMING (M/S = VIL) tWB BUSY Input to Write(4) Write Hold After BUSY(5) tWH tBDD — 25 — 35 — 45 ns — 25 — 35 — 45 ns — 25 — 35 — 45 ns 5 — 5 — 5 — ns — 35 — 35 — 40 ns 20 — 25 — 25 — ns 0 — 0 — 0 — ns 20 — 25 — 25 — ns — 55 — 60 — 80 ns — 50 — 55 — 75 PORT-TO-PORT DELAY TIMING Write Pulse to Data Delay(1) tWDD Write Data Valid to Read Data Delay tDDD (1) NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With BUSY (M / of Write With Port-To-Port Delay (M / S = L)". 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0ns, tWDD – tWP (actual), or tDDD – tDW (actual). 4. To ensure that the write cycle is inhibited on port "B" during contention with port "A". 5. To ensure that a write cycle is completed on port "B" after contention with port "A". 6. "X" in part numbers indicates power rating (S or L). ns 2740 tbl 13 S = H)" or "Timing Waveform TIMING WAVEFORM OF READ WITH BUSY (M/S = VIH)(2,4,5) tWC MATCH ADDR"A" tWP R/ W"A" tDW tDH VALID DATAIN "A" tAPS (1) MATCH ADDR"B" tBAA tBDA tBDD BUSY"B" tWDD DATAOUT "B" VALID tDDD (3) NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave). 2. CEL = CER = VIL. 3. OE = VIL for the reading port. 4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above. 5. All timing is the same for both left and right ports. Port "A" may be either the left or right Port. Port "B" is the port opposite from port "A". 6.38 2911 drw 12 10 IDT70V24S/L HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF SLAVE WRITE (M/S = VIH) tWP W R/ "A" tWB(3) BUSY"B" tWH (1) W R/ "B" (2) 2911 drw 13 NOTES: 1. tWH must be met for both BUSY input (slave) and output (master). 2. Busy is asserted on port "B" Blocking R/W"B", until BUSY"B" goes High. 3. tWB is only for the "slave" version. WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING(M/S = VIH)(1) ADDR"A" and "B" ADDRESSES MATCH CE"A" tAPS(2) CE"B" tBAC tBDC BUSY"B" 2911 drw 14 WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH TIMING (M/S = VIH)(1) ADDRESS "N" ADDR"A" tAPS ADDR"B" (2) MATCHING ADDRESS "N" tBAA tBDA BUSY"B" 2911 drw 15 NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. If tAPS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted. 6.38 11 IDT70V24S/L HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) Symbol Parameter IDT70V24X25 IDT70V24X35 IDT70V24X55 Min. Min. Min. Max. Max. Max. Unit INTERRUPT TIMING tAS Address Set-up Time 0 — 0 — 0 — ns tWR Write Recovery Time 0 — 0 — 0 — ns tINS Interrupt Set Time — 25 — 30 — 40 ns tINR Interrupt Reset Time — 30 — 35 — 45 ns NOTE: 1. "X" in part numbers indicates power rating (S or L). 2911 tbl 14 WAVEFORM OF INTERRUPT TIMING(1) tWC INTERRUPT SET ADDRESS ADDR"A" (2) tAS(3) tWR(4) CE"A" W"A" R/ tINS(3) INT"B" 2911 drw 16 tRC INTERRUPT CLEAR ADDRESS (2) ADDR"B" tAS (3) CE"B" OE"B" tINR(3) INT"B" NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. See Interrupt truth table. 3. Timing depends on which enable signal ( CE or R/W ) is asserted last. 4. Timing depends on which enable signal ( CE or R/W ) is de-asserted first. 2911 drw 17 TRUTH TABLES TRUTH TABLE III — INTERRUPT FLAG(1) Left Port R/W L CEL OEL Right Port A11L-A0L INTL R/W R CER OER A11R-A0R INTR (2) L L X FFF X X X X X X X X X X X L L FFF H(3) (3) L L X FFE X H(2) X X X X X X X X X X L L FFE L NOTES: 1. Assumes BUSYL = BUSYR = VIH. 2. If BUSYL = VIL, then no change. 3. If BUSYR = VIL, then no change. L Function Set Right INTR Flag Reset Right INTR Flag Set Left INTL Flag Reset Left INTL Flag 2911 tbl 15 6.38 12 IDT70V24S/L HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE TRUTH TABLE IV — ADDRESS BUSY ARBITRATION Inputs Outputs CEL CER A0L-A11L A0R-A11R X X NO MATCH H H Normal H X MATCH H H Normal X H MATCH H H Normal L L MATCH (2) (2) Write Inhibit(3) BUSYL (1) (1) BUSYR Function NOTES: 2911 tbl 16 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70V24 are push pull, not open drain outputs. On slaves the BUSY input internally inhibits writes. 2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. H if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = Low will result. BUSYL and BUSYR outputs cannot be low simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving low regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving low regardless of actual logic level on the pin. TRUTH TABLE V — EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE(1,2) Functions No Action D0 - D15 Left D0 - D15 Right Status 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token Right Port Writes "1" to Semaphore 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Right port has semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V24. 2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0 - A2. 2911 tbl 17 FUNCTIONAL DESCRIPTION The IDT70V24 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT70V24 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE High). When a port is enabled, access to the entire memory array is permitted. memory location FFF (HEX) and to clear the interrupt flag (INTR), the right port must read the memory location FFF. The message (16 bits) at FFE or FFF is user-defined, since it is an addressable SRAM location. If the interrupt function is not used, address locations FFE and FFF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table for the interrupt operation. BUSY LOGIC INTERRUPTS If the user chooses to use the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location FFE (HEX), where a write is defined as the CE=R/W=VIL per the Truthe Table. The left port clears the interrupt by accessing address location FFE when CER=OE R=VIL, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is “Busy”. The busy pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding. The use of busy logic is not required or desirable for all 6.38 13 IDT70V24S/L HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM BUSYL MASTER Dual Port RAM BUSYL BUSYL CE SLAVE Dual Port RAM BUSYL BUSYR CE SLAVE Dual Port RAM BUSYL BUSYR CE BUSYR DECODER MASTER Dual Port RAM COMMERCIAL TEMPERATURE RANGE CE BUSYR BUSYR 2911 drw 18 Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V24 RAMs. applications. In some cases it may be useful to logically OR the busy outputs together and use any busy indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of busy logic is not desirable, the busy logic can be disabled by placing the part in slave mode with the M/S pin. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins high. If desired, unintended write operations can be prevented to a port by tying the busy pin for that port low. The busy outputs on the IDT 70V24 RAM in master mode, are push-pull type outputs and do not require pull up resistors to operate. If these RAMs are being expanded in depth, then the busy indication for the resulting array requires the use of an external AND gate. WIDTH EXPANSION WITH BUSY LOGIC MASTER/SLAVE ARRAYS When expanding an IDT70V24 RAM array in width while using busy logic, one master part is used to decide which side of the RAM array will receive a busy indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the busy signal as a write inhibit signal. Thus on the IDT70V24 RAM the busy pin is an output if the part is used as a master (M/S pin = H), and the busy pin is an input if the part used as a slave (M/S pin = L) as shown in Figure 3. If two or more master parts were used when expanding in width, a split decision could result with one master indicating busy on one side of the array and another master indicating busy on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The busy arbitration, on a master, is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a busy flag to be output from the master before the actual write pulse can be initiated with either the R/W signal or the byte enables. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. SEMAPHORES The IDT70V24 is an extremely fast Dual-Port 4K x 16 CMOS Static RAM with an additional 8 address locations dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the Dual-Port RAM to claim a privilege over the other processor for functions defined by the system designer’s software. As an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the Dual-Port RAM or any other shared resource. The Dual-Port RAM features a fast access time, and both ports are completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM and can be read from, or written to, at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/WRITE of, a non-semaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the Dual-Port RAM. These devices have an automatic power-down feature controlled by CE, the Dual-Port RAM enable, and SEM, the semaphore enable. The CE and SEM pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the condition which is shown in Truth Table where CE and SEM are both high. Systems which can best use the IDT70V24 contain multiple processors or controllers and are typically very highspeed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the IDT70V24's hardware semaphores, which provide a lockout mechanism without requiring complex programming. Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. The IDT70V24 does 6.38 14 IDT70V24S/L HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very high-speed systems. HOW THE SEMAPHORE FLAGS WORK The semaphore logic is a set of eight latches which are independent of the Dual-Port RAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called “Token Passing Allocation.” In this method, the state of a semaphore latch is used as a token indicating that shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphore’s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active low. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT70V24 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a low input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, OE, and R/W) as they would be used in accessing a standard Static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A0 – A2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D0 is used. If a low level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Table III). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (A thorough discussing on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one side’s output register when that side's semaphore select (SEM) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore in a test loop must cause either signal (SEM or OE) to go inactive or the output will never change. A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see Table III). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. Had a sequence of READ/WRITE been used instead, system contention problems could have occurred during the gap between the read and write cycles. It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag low and the other side high. This condition will continue until a one is written to the same semaphore request latch. Should the other side’s semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side’s request latch. The second side’s flag will now stay low until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming tech- 6.38 15 IDT70V24S/L HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE nique, if semaphores are misused or misinterpreted, a software error can easily happen. Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. USING SEMAPHORES—SOME EXAMPLES Perhaps the simplest application of semaphores is their application as resource markers for the IDT70V24’s Dual-Port RAM. Say the 4K x 16 RAM was to be divided into two 2K x 16 blocks which were to be dedicated at any one time to servicing either the left or right port. Semaphore 0 could be used to indicate the side which would control the lower section of memory, and Semaphore 1 could be defined as the indicator for the upper section of memory. To take a resource, in this example the lower 2K of Dual-Port RAM, the processor on the left port could write and then read a zero in to Semaphore 0. If this task were successfully completed (a zero was read back rather than a one), the left processor would assume control of the lower 2K. Meanwhile the right processor was attempting to gain control of the resource after the left processor, it would read back a one in response to the zero it had attempted to write into Semaphore 0. At this point, the software could choose to try and gain control of the second 2K section by writing, then reading a zero into Semaphore 1. If it succeeded in gaining control, it would lock out the left side. Once the left side was finished with its task, it would write a one to Semaphore 0 and may then try to gain access to Semaphore 1. If Semaphore 1 was still occupied by the right side, the left side could undo its semaphore request and perform other tasks until it was able to write, then read a zero into Semaphore 1. If the right processor performs a similar task with Semaphore 0, this protocol would allow the two processors to swap 2K blocks of Dual-Port RAM with each other. The blocks do not have to be any particular size and can even be variable, depending upon the complexity of the software using the semaphore flags. All eight semaphores could be used to divide the Dual-Port RAM or other shared resources into eight parts. Semaphores can even be assigned different meanings on different sides rather than being given a common meaning as was shown in the example above. Semaphores are a useful form of arbitration in systems like disk interfaces where the CPU must be locked out of a section of memory during a transfer and the I/O device cannot tolerate any wait states. With the use of semaphores, once the two devices has determined which memory area was “off-limits” to the CPU, both the CPU and the I/O devices could access their assigned portions of memory continuously without any wait states. Semaphores are also useful in applications where no memory “WAIT” state is available on one or both sides. Once a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed. Another application is in the area of complex data structures. In this case, block arbitration is very important. For this application one processor may be responsible for building and updating a data structure. The other processor then reads and interprets that data structure. If the interpreting processor reads an incomplete data structure, a major error condition may exist. Therefore, some sort of arbitration must be used between the two different processors. The building processor arbitrates for the block, locks it and then is able to go in and update the data structure. When the update is completed, the data structure block is released. This allows the interpreting processor to come back and read the complete data structure, thereby guaranteeing a consistent data structure. L PORT R PORT SEMAPHORE REQUEST FLIP FLOP D0 WRITE D SEMAPHORE REQUEST FLIP FLOP Q Q SEMAPHORE READ D D0 WRITE SEMAPHORE READ 2911 drw 19 Figure 4. IDT70V24 Semaphore Logic 6.38 16 IDT70V24S/L HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XXXXX Device Type A 999 A A Power Speed Package Process/ Temperature Range Blank Commercial (0°C to +70°C) PF G J 100-pin TQFP (PN100-1) 84-pin PGA (G84-3) 84-pin PLCC (J84-1) 25 35 55 S L Speed in nanoseconds Standard Power Low Power 70V24 64K (4K x 16) 3.3V Dual-Port RAM 2911 drw 20 6.38 17